KR20040004173A - 다층 회로기판 형성방법 및 다층 회로기판 - Google Patents

다층 회로기판 형성방법 및 다층 회로기판

Info

Publication number
KR20040004173A
KR20040004173A KR1020030045204A KR20030045204A KR20040004173A KR 20040004173 A KR20040004173 A KR 20040004173A KR 1020030045204 A KR1020030045204 A KR 1020030045204A KR 20030045204 A KR20030045204 A KR 20030045204A KR 20040004173 A KR20040004173 A KR 20040004173A
Authority
KR
South Korea
Prior art keywords
circuit
circuit board
forming
conductor
insulating material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020030045204A
Other languages
English (en)
Korean (ko)
Inventor
니시카와가즈히로
츠카하라노리히토
오타니히로유키
Original Assignee
마쯔시다덴기산교 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 마쯔시다덴기산교 가부시키가이샤 filed Critical 마쯔시다덴기산교 가부시키가이샤
Publication of KR20040004173A publication Critical patent/KR20040004173A/ko
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0179—Thin film deposited insulating layer, e.g. inorganic layer for printed capacitor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0376—Flush conductors, i.e. flush with the surface of the printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0278—Flat pressure, e.g. for connecting terminals with anisotropic conductive adhesive
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0582—Coating by resist, i.e. resist used as mask for application of insulating coating or of second resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/002—Etching of the substrate by chemical or physical means by liquid chemical etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0041—Etching of the substrate by chemical or physical means by plasma etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
KR1020030045204A 2002-07-05 2003-07-04 다층 회로기판 형성방법 및 다층 회로기판 Withdrawn KR20040004173A (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2002197033 2002-07-05
JPJP-P-2002-00197033 2002-07-05
JPJP-P-2003-00188290 2003-06-30
JP2003188290A JP4125644B2 (ja) 2002-07-05 2003-06-30 多層回路基板の形成方法および多層回路基板

Publications (1)

Publication Number Publication Date
KR20040004173A true KR20040004173A (ko) 2004-01-13

Family

ID=31190281

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020030045204A Withdrawn KR20040004173A (ko) 2002-07-05 2003-07-04 다층 회로기판 형성방법 및 다층 회로기판

Country Status (4)

Country Link
US (1) US6971167B2 (enExample)
JP (1) JP4125644B2 (enExample)
KR (1) KR20040004173A (enExample)
CN (1) CN100466885C (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6989327B2 (en) * 2004-01-31 2006-01-24 Hewlett-Packard Development Company, L.P. Forming a contact in a thin-film device
KR100817639B1 (ko) 2004-03-19 2008-03-27 에스에무케이 가부시키가이샤 스크린 프린팅 금속 마스크 판 및 진동부를 수지-밀봉하는방법
JP4345598B2 (ja) * 2004-07-15 2009-10-14 パナソニック株式会社 回路基板の接続構造体とその製造方法
JP2006128520A (ja) * 2004-10-29 2006-05-18 Tdk Corp 多層基板の製造方法
TWI363585B (en) * 2008-04-02 2012-05-01 Advanced Semiconductor Eng Method for manufacturing a substrate having embedded component therein
JP5903793B2 (ja) 2011-08-03 2016-04-13 日本電産株式会社 スピンドルモータの製造方法、スピンドルモータ、およびディスク駆動装置
JP6927665B2 (ja) * 2015-12-25 2021-09-01 日東電工株式会社 配線回路基板
US11089675B2 (en) * 2018-10-22 2021-08-10 Te Connectivity Corporation Tamper sensor
KR102112327B1 (ko) * 2018-12-04 2020-05-18 주식회사 엠디엠 입체 구조물의 표면에 회로 패턴을 형성하는 방법
CN112165767B (zh) * 2020-10-27 2021-12-07 惠州市特创电子科技股份有限公司 多层线路板以及移动通讯装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3324014A (en) * 1962-12-03 1967-06-06 United Carr Inc Method for making flush metallic patterns
US4221047A (en) * 1979-03-23 1980-09-09 International Business Machines Corporation Multilayered glass-ceramic substrate for mounting of semiconductor device
US4354895A (en) * 1981-11-27 1982-10-19 International Business Machines Corporation Method for making laminated multilayer circuit boards
US4789423A (en) * 1982-03-04 1988-12-06 E. I. Du Pont De Nemours And Company Method for manufacturing multi-layer printed circuit boards
US4606787A (en) * 1982-03-04 1986-08-19 Etd Technology, Inc. Method and apparatus for manufacturing multi layer printed circuit boards
US4915983A (en) * 1985-06-10 1990-04-10 The Foxboro Company Multilayer circuit board fabrication process
US4927477A (en) * 1985-08-26 1990-05-22 International Business Machines Corporation Method for making a flush surface laminate for a multilayer circuit board
JPH0716094B2 (ja) * 1986-03-31 1995-02-22 日立化成工業株式会社 配線板の製造法
US5114518A (en) * 1986-10-23 1992-05-19 International Business Machines Corporation Method of making multilayer circuit boards having conformal Insulating layers
TW210422B (enExample) * 1991-06-04 1993-08-01 Akzo Nv
US5199163A (en) * 1992-06-01 1993-04-06 International Business Machines Corporation Metal transfer layers for parallel processing
JP3758811B2 (ja) 1997-05-30 2006-03-22 京セラ株式会社 転写シート及びそれを用いた配線基板の製造方法

Also Published As

Publication number Publication date
CN1496216A (zh) 2004-05-12
CN100466885C (zh) 2009-03-04
JP2004088093A (ja) 2004-03-18
US20040020047A1 (en) 2004-02-05
US6971167B2 (en) 2005-12-06
JP4125644B2 (ja) 2008-07-30

Similar Documents

Publication Publication Date Title
JP4334996B2 (ja) 多層配線板用基材、両面配線板およびそれらの製造方法
EP0530840B1 (en) Electric circuit board module and method for producing electric circuit board module
US7839650B2 (en) Circuit board structure having embedded capacitor and fabrication method thereof
JP3964085B2 (ja) プリント配線基板、及びプリント配線基板の製造方法
US5625230A (en) Integrated circuit chip structure
TW201004521A (en) Solder ball mounting apparatus and wiring board manufacturing method
JP2014524671A (ja) 回路基板
US6374733B1 (en) Method of manufacturing ceramic substrate
KR100836653B1 (ko) 회로기판 및 그 제조방법
KR20040004173A (ko) 다층 회로기판 형성방법 및 다층 회로기판
US20110154661A1 (en) Method of fabricating printed circuit board assembly
TWI446841B (zh) 埋入式元件電路板與其製作方法
JP2542794B2 (ja) 配線板の製造方法
JP2006086153A (ja) フレキシブル配線板及びフレキシブル配線板の製造方法
TWI859613B (zh) 電路板及其製作方法
US5766499A (en) Method of making a circuitized substrate
JPH1065322A (ja) 電気部品に導電バンプを形成する方法
JP2954559B2 (ja) 配線基板の電極構造
JP2004087575A (ja) 半導体装置とその製造方法ならびに半導体装置の実装構造
KR100583977B1 (ko) 인쇄회로기판의 제조방법
JPH07304Y2 (ja) 半田ペ−スト印刷用マスク
JP2003324027A (ja) 積層型電子部品の製造方法
JP3582481B2 (ja) 電子部品の製造方法
JP2003234426A (ja) 集積回路パッケージ用のシーケンシャルビルドアップ基板の機械的平坦化を与えるシステム及び方法
US20070007637A1 (en) Multi-layered substrate assembly with vialess electrical interconnect scheme

Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 20030704

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid