JP4118320B1 - 実装基板およびそれを用いた薄型発光装置の製造方法 - Google Patents
実装基板およびそれを用いた薄型発光装置の製造方法 Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 72
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 239000011888 foil Substances 0.000 claims abstract description 125
- 229920005989 resin Polymers 0.000 claims abstract description 68
- 239000011347 resin Substances 0.000 claims abstract description 68
- 239000007788 liquid Substances 0.000 claims abstract description 43
- 238000000926 separation method Methods 0.000 claims abstract description 34
- 229910000679 solder Inorganic materials 0.000 claims abstract description 20
- 238000009713 electroplating Methods 0.000 claims abstract description 18
- 238000007747 plating Methods 0.000 claims description 20
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 16
- 239000010931 gold Substances 0.000 claims description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 13
- 229910052737 gold Inorganic materials 0.000 claims description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 11
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 10
- 229910052709 silver Inorganic materials 0.000 claims description 10
- 239000004332 silver Substances 0.000 claims description 10
- 239000011889 copper foil Substances 0.000 claims description 9
- 229910052759 nickel Inorganic materials 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 230000003014 reinforcing effect Effects 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 5
- 239000007858 starting material Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 67
- 238000000605 extraction Methods 0.000 description 11
- 238000000034 method Methods 0.000 description 9
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 238000009413 insulation Methods 0.000 description 5
- 229910001111 Fine metal Inorganic materials 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 238000007650 screen-printing Methods 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 239000004925 Acrylic resin Substances 0.000 description 2
- 229920000178 Acrylic resin Polymers 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 229920002050 silicone resin Polymers 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 238000007730 finishing process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- -1 nitride compound Chemical class 0.000 description 1
- 229920006267 polyester film Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- 230000037303 wrinkles Effects 0.000 description 1
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Abstract
【解決手段】 本発明の実装基板では、導電箔10の一主面に列状に多数個隣接して配列した電解メッキで形成した第1電極部11とマウント部17に近接した第2電極部12と、導電箔10を補強する液状樹脂13と、列を分離する分離用スリット孔14と、導電箔10の反対主面の第1電極部11と第2電極部12が電気的に分離される絶縁用スリット孔15と、絶縁用スリット孔15を覆い導電箔10を補強する半田レジスト層16とを具備し、導電箔10を出発材料として支持基板レスの実装基板を実現し、発光素子を少ない材料で大量に作れる薄型発光装置の製造方法を実現した。
【選択図】図1
Description
マーク7が設けられ、ダイシング時の位置合わせに用いる。これらは製造工程における各セル22との位置合わせに用いられ極めて精度の高い薄型発光装置の製造を実現する。
38列×125個=4750個
となり、基板1枚当たりの収量は4750個である。
55列×125個=6875個
となり、基板1枚当たりの収量は6875個である。これは従来の場合と単純に面積比で比較しても144.7%ととなり、44.7%の収量アップが実現できる。
10 導電箔
11 第1電極部
12 第2電極部
13 液状樹脂
14 分離用スリット孔
15 絶縁用スリット孔
16 半田レジスト層
17 マウント部
20 キャリアシート
21 レジスト層
22 セル
23 導電性金属層
24 第1外部取出電極
25 第2外部取出電極
26 発光素子
27 接着剤
28 金属細線
29 透明樹脂
Claims (10)
- 導電箔の一主面に列状に多数個隣接して配列した発光素子などを載置するマウント部、電解メッキで形成した第1電極部と前記マウント部に近接した第2電極部と、
前記第1電極部と前記第2電極部間の前記導電箔に付着し且つ前記導電箔を補強する液状樹脂と、
隣接する列の前記第1電極部と前記第2電極部間の前記導電箔に設けられ、前記導電箔を貫通して隣接する前記列を分離する分離用スリット孔と、
前記第1電極部と前記第2電極部の間に位置し、前記分離用スリット孔に並設して設けられ且つ前記第1電極部と前記第2電極部が電気的に分離されるように前記導電箔を貫通して設けられ且つ前記液状樹脂で補強された絶縁用スリット孔と、
前記絶縁用スリット孔を覆い前記導電箔の反対主面に設けられ、前記液状樹脂に対応する位置を覆い且つ前記導電箔を補強する半田レジスト層とを具備することを特徴とする実装基板。 - 前記分離用スリット孔を2個以上に分割して橋洛部を設けて前記導電箔の補強を行うことを特徴とする請求項1に記載の実装基板。
- 前記導電箔は厚さ12〜200μの銅箔を用いることを特徴とする請求項1に記載の実装基板。
- 前記導電箔、前記第1電極部及び前記第2電極部はニッケルメッキ及び金あるいは銀メッキ層で被覆されることを特徴とする請求項3に記載の実装基板。
- 前記分離用スリット孔はエッチングで形成されて0.5mm以下の幅であることを特徴とする請求項1に記載の実装基板。
- 導電箔上に形成する第1電極部と発光素子を載置するマウント部に近接して設ける第2電極部の予定の領域を露出してレジスト層で前記導電箔を被覆する工程と、
前記レジスト層をマスクとして前記導電箔に選択的に金属メッキを施し、列状に多数個のセルを隣接して配列した前記第1及び第2電極部を形成する工程と、
前記レジスト層を除去して前記第1及び第2電極部間の前記導電箔上に液状樹脂を付着する工程と、
前記導電箔を前記液状樹脂を付着した反対面より選択的にエッチングして前記各セルの前記第1及び第2電極部を電気的に分離する前記導電箔を貫通する絶縁用スリット孔と、隣接した前記列のセルを離間する前記導電箔を貫通する分離用スリット孔を設ける工程と、
前記絶縁用スリット孔を覆い前記導電箔の反対主面に設けられ、前記液状樹脂に対応する位置を覆い且つ前記導電箔を補強する半田レジスト層を形成して実装基板を形成する工程と、
前記マウント部に発光素子を載置し、前記発光素子の電極と前記第1電極部をボンディングワイヤで接続する工程と、
前記分離用スリット孔を露出して前記発光素子を列状に樹脂で被覆する工程と、
前記各セルを前記列状の樹脂をダイシングして前記分離用スリット孔を用いて個別に分離する工程とを具備することを特徴とする薄型発光装置の製造方法。 - 前記液状樹脂を付着する工程において、前記第1及び第2電極部と前記マウント部を少なくともホトレジスト層で覆った後に前記液状樹脂を少なくとも露出した前記導電箔上に付着することを特徴とする請求項6に記載の薄型発光装置の製造方法。
- 前記第1及び第2電極部を電気的に分離する工程において、前記分離用スリット孔と前記絶縁スリット孔とを同時に形成することを特徴とする請求項6に記載の薄型発光装置の製造方法。
- 前記第1及び第2電極部を電気的に分離する工程の後に、前記第1及び第2電極部と前記マウント部にニッケルメッキ層及び金あるいは銀メッキ層を形成することを特徴とする請求項6に記載の薄型発光装置の製造方法。
- 前記導電箔はロール状に巻かれた状態から供給をされることを特徴とする請求項6に記載の薄型発光装置の製造方法。
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