JP4054598B2 - メモリ制御回路、ｄｍａ要求ブロック及びメモリアクセスシステム - Google Patents

メモリ制御回路、ｄｍａ要求ブロック及びメモリアクセスシステム Download PDF

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Publication number
JP4054598B2
JP4054598B2 JP2002123811A JP2002123811A JP4054598B2 JP 4054598 B2 JP4054598 B2 JP 4054598B2 JP 2002123811 A JP2002123811 A JP 2002123811A JP 2002123811 A JP2002123811 A JP 2002123811A JP 4054598 B2 JP4054598 B2 JP 4054598B2
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JP
Japan
Prior art keywords
dma
burst
dma request
signal
memory
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Expired - Fee Related
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JP2002123811A
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English (en)
Japanese (ja)
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JP2003316642A (ja
JP2003316642A5 (enExample
Inventor
明 黒沼
亨 中山
拓二 勝
壮平 田中
雅文 綿谷
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Canon Inc
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Canon Inc
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Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2002123811A priority Critical patent/JP4054598B2/ja
Priority to US10/417,087 priority patent/US6859848B2/en
Priority to CN03123280.9A priority patent/CN1231844C/zh
Publication of JP2003316642A publication Critical patent/JP2003316642A/ja
Publication of JP2003316642A5 publication Critical patent/JP2003316642A5/ja
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Publication of JP4054598B2 publication Critical patent/JP4054598B2/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Memory System (AREA)
  • Dram (AREA)
JP2002123811A 2002-04-25 2002-04-25 メモリ制御回路、ｄｍａ要求ブロック及びメモリアクセスシステム Expired - Fee Related JP4054598B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2002123811A JP4054598B2 (ja) 2002-04-25 2002-04-25 メモリ制御回路、ｄｍａ要求ブロック及びメモリアクセスシステム
US10/417,087 US6859848B2 (en) 2002-04-25 2003-04-17 Circuit for controlling sequential access to SDRAM
CN03123280.9A CN1231844C (zh) 2002-04-25 2003-04-25 控制对sdram的连续访问的电路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002123811A JP4054598B2 (ja) 2002-04-25 2002-04-25 メモリ制御回路、ｄｍａ要求ブロック及びメモリアクセスシステム

Publications (3)

Publication Number Publication Date
JP2003316642A JP2003316642A (ja) 2003-11-07
JP2003316642A5 JP2003316642A5 (enExample) 2005-09-29
JP4054598B2 true JP4054598B2 (ja) 2008-02-27

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Family Applications (1)

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JP2002123811A Expired - Fee Related JP4054598B2 (ja) 2002-04-25 2002-04-25 メモリ制御回路、ｄｍａ要求ブロック及びメモリアクセスシステム

Country Status (3)

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US (1) US6859848B2 (enExample)
JP (1) JP4054598B2 (enExample)
CN (1) CN1231844C (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7107365B1 (en) * 2002-06-25 2006-09-12 Cypress Semiconductor Corp. Early detection and grant, an arbitration scheme for single transfers on AMBA advanced high-performance bus
US7899957B1 (en) * 2003-12-30 2011-03-01 Altera Corporation Memory controller having a buffer for providing beginning and end data
JP4882006B2 (ja) * 2007-01-05 2012-02-22 プロトン ワールド インターナショナル エヌ．ヴィ． 電子回路のリソースへのアクセス制限
JP5064336B2 (ja) * 2008-09-12 2012-10-31 株式会社リコー 画像形成システムおよびプログラム
KR101989860B1 (ko) 2012-12-21 2019-06-17 에스케이하이닉스 주식회사 메모리 컨트롤러 및 이를 포함하는 메모리 시스템
JP6210018B2 (ja) * 2014-04-25 2017-10-11 株式会社オートネットワーク技術研究所 スイッチのオン／オフ制御方法及びスイッチ回路
JP6316143B2 (ja) * 2014-08-22 2018-04-25 ルネサスエレクトロニクス株式会社 半導体装置、メモリアクセス制御方法、及び半導体装置システム

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10133998A (ja) 1996-11-05 1998-05-22 Canon Inc データ処理方法とその方法を用いた記録装置
US6366989B1 (en) * 1998-09-17 2002-04-02 Sun Microsystems, Inc. Programmable memory controller
JP3976927B2 (ja) 1999-01-25 2007-09-19 キヤノン株式会社 バス制御装置
US6622203B2 (en) * 2001-05-29 2003-09-16 Agilent Technologies, Inc. Embedded memory access method and system for application specific integrated circuits

Also Published As

Publication number Publication date
US6859848B2 (en) 2005-02-22
US20030204651A1 (en) 2003-10-30
JP2003316642A (ja) 2003-11-07
CN1462946A (zh) 2003-12-24
CN1231844C (zh) 2005-12-14

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