JP2003316642A5 - - Google Patents

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Publication number
JP2003316642A5
JP2003316642A5 JP2002123811A JP2002123811A JP2003316642A5 JP 2003316642 A5 JP2003316642 A5 JP 2003316642A5 JP 2002123811 A JP2002123811 A JP 2002123811A JP 2002123811 A JP2002123811 A JP 2002123811A JP 2003316642 A5 JP2003316642 A5 JP 2003316642A5
Authority
JP
Japan
Prior art keywords
dma
dma request
burst
signal
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002123811A
Other languages
English (en)
Japanese (ja)
Other versions
JP4054598B2 (ja
JP2003316642A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2002123811A priority Critical patent/JP4054598B2/ja
Priority claimed from JP2002123811A external-priority patent/JP4054598B2/ja
Priority to US10/417,087 priority patent/US6859848B2/en
Priority to CN03123280.9A priority patent/CN1231844C/zh
Publication of JP2003316642A publication Critical patent/JP2003316642A/ja
Publication of JP2003316642A5 publication Critical patent/JP2003316642A5/ja
Application granted granted Critical
Publication of JP4054598B2 publication Critical patent/JP4054598B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP2002123811A 2002-04-25 2002-04-25 メモリ制御回路、ｄｍａ要求ブロック及びメモリアクセスシステム Expired - Fee Related JP4054598B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2002123811A JP4054598B2 (ja) 2002-04-25 2002-04-25 メモリ制御回路、ｄｍａ要求ブロック及びメモリアクセスシステム
US10/417,087 US6859848B2 (en) 2002-04-25 2003-04-17 Circuit for controlling sequential access to SDRAM
CN03123280.9A CN1231844C (zh) 2002-04-25 2003-04-25 控制对sdram的连续访问的电路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002123811A JP4054598B2 (ja) 2002-04-25 2002-04-25 メモリ制御回路、ｄｍａ要求ブロック及びメモリアクセスシステム

Publications (3)

Publication Number Publication Date
JP2003316642A JP2003316642A (ja) 2003-11-07
JP2003316642A5 true JP2003316642A5 (enExample) 2005-09-29
JP4054598B2 JP4054598B2 (ja) 2008-02-27

Family

ID=29243698

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002123811A Expired - Fee Related JP4054598B2 (ja) 2002-04-25 2002-04-25 メモリ制御回路、ｄｍａ要求ブロック及びメモリアクセスシステム

Country Status (3)

Country Link
US (1) US6859848B2 (enExample)
JP (1) JP4054598B2 (enExample)
CN (1) CN1231844C (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7107365B1 (en) * 2002-06-25 2006-09-12 Cypress Semiconductor Corp. Early detection and grant, an arbitration scheme for single transfers on AMBA advanced high-performance bus
US7899957B1 (en) * 2003-12-30 2011-03-01 Altera Corporation Memory controller having a buffer for providing beginning and end data
JP4882006B2 (ja) * 2007-01-05 2012-02-22 プロトン ワールド インターナショナル エヌ．ヴィ． 電子回路のリソースへのアクセス制限
JP5064336B2 (ja) * 2008-09-12 2012-10-31 株式会社リコー 画像形成システムおよびプログラム
KR101989860B1 (ko) 2012-12-21 2019-06-17 에스케이하이닉스 주식회사 메모리 컨트롤러 및 이를 포함하는 메모리 시스템
JP6210018B2 (ja) * 2014-04-25 2017-10-11 株式会社オートネットワーク技術研究所 スイッチのオン／オフ制御方法及びスイッチ回路
JP6316143B2 (ja) * 2014-08-22 2018-04-25 ルネサスエレクトロニクス株式会社 半導体装置、メモリアクセス制御方法、及び半導体装置システム

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10133998A (ja) 1996-11-05 1998-05-22 Canon Inc データ処理方法とその方法を用いた記録装置
US6366989B1 (en) * 1998-09-17 2002-04-02 Sun Microsystems, Inc. Programmable memory controller
JP3976927B2 (ja) 1999-01-25 2007-09-19 キヤノン株式会社 バス制御装置
US6622203B2 (en) * 2001-05-29 2003-09-16 Agilent Technologies, Inc. Embedded memory access method and system for application specific integrated circuits

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