JP4051008B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4051008B2 JP4051008B2 JP2003274652A JP2003274652A JP4051008B2 JP 4051008 B2 JP4051008 B2 JP 4051008B2 JP 2003274652 A JP2003274652 A JP 2003274652A JP 2003274652 A JP2003274652 A JP 2003274652A JP 4051008 B2 JP4051008 B2 JP 4051008B2
- Authority
- JP
- Japan
- Prior art keywords
- macro
- memory
- signal
- mode
- active
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/26—Accessing multiple arrays
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/26—Accessing multiple arrays
- G11C2029/2602—Concurrent test
Landscapes
- Tests Of Electronic Circuits (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
- Dram (AREA)
Description
30 制御部
32 第1のメモリマクロ制御回路
34〜39 第2のメモリマクロ制御回路
42 第2のデータ出力回路
42A,42B EXORゲート(第2の一致判定回路)
42C NANDゲート(第2の論理積回路)
44〜49 第1のデータ出力回路
44C EXORゲート(第1の一致判定回路)
51〜53 ANDゲート(第1の論理積回路)
100 半導体装置
Claims (1)
- それぞれが複数のメモリセルを有し、対応する活性マクロ選択信号に従って活性化し、かつ、対応する活性モード制御信号に応じた活性モードで動作する複数のメモリマクロと、
前記複数のメモリマクロのうち、いずれか1つのメモリマクロが、通常の動作を行う正規活性モードで動作するように、その他の1つ以上のメモリマクロが、読み出されたデータをそのメモリマクロの外に出力しないダミー活性モードで前記いずれか1つのメモリマクロと同時に動作するように、入力された動作モード制御信号に応じて、前記複数のメモリマクロのそれぞれに対応する活性マクロ選択信号及び活性モード制御信号を生成して出力することが可能な制御部とを備える
半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003274652A JP4051008B2 (ja) | 2003-07-15 | 2003-07-15 | 半導体装置 |
CNB2004100698946A CN100414648C (zh) | 2003-07-15 | 2004-07-15 | 半导体装置 |
US10/891,041 US7379349B2 (en) | 2003-07-15 | 2004-07-15 | Simultaneous and selective memory macro testing |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003274652A JP4051008B2 (ja) | 2003-07-15 | 2003-07-15 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005038511A JP2005038511A (ja) | 2005-02-10 |
JP4051008B2 true JP4051008B2 (ja) | 2008-02-20 |
Family
ID=34056081
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003274652A Expired - Fee Related JP4051008B2 (ja) | 2003-07-15 | 2003-07-15 | 半導体装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7379349B2 (ja) |
JP (1) | JP4051008B2 (ja) |
CN (1) | CN100414648C (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070188261A1 (en) * | 2003-12-24 | 2007-08-16 | Brunker David L | Transmission line with a transforming impedance and solder lands |
KR100576454B1 (ko) * | 2004-03-22 | 2006-05-08 | 주식회사 하이닉스반도체 | 뱅크 선택이 가능한 병렬 테스트 회로 및 그 병렬 테스트방법 |
JP4773791B2 (ja) * | 2005-09-30 | 2011-09-14 | 富士通セミコンダクター株式会社 | 半導体記憶装置、およびメモリテスト回路 |
JP2011118972A (ja) * | 2009-12-02 | 2011-06-16 | Renesas Electronics Corp | 半導体集積回路のテスト方法及び半導体集積回路 |
US8400865B2 (en) * | 2010-09-08 | 2013-03-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory macro configuration and method |
GB2498980A (en) * | 2012-02-01 | 2013-08-07 | Inside Secure | Device and method to perform a parallel memory test |
US10892008B2 (en) | 2018-06-15 | 2021-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi word line assertion |
DE102019115978B4 (de) | 2018-06-15 | 2022-03-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Aktivierung mehrerer wortleitungen |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0215490A (ja) | 1988-07-01 | 1990-01-19 | Mitsubishi Electric Corp | 半導体ダイナミックram |
JPH0358375A (ja) | 1989-07-26 | 1991-03-13 | Hitachi Ltd | 半導体記憶装置 |
JPH07307100A (ja) | 1994-05-11 | 1995-11-21 | Nec Corp | メモリ集積回路 |
CN1137492C (zh) * | 1997-02-17 | 2004-02-04 | 株式会社日立制作所 | 半导体集成电路器件 |
US5959911A (en) * | 1997-09-29 | 1999-09-28 | Siemens Aktiengesellschaft | Apparatus and method for implementing a bank interlock scheme and related test mode for multibank memory devices |
JPH11231023A (ja) | 1998-02-16 | 1999-08-27 | Hitachi Ltd | 半導体集積回路装置およびその検査方法 |
JP4601737B2 (ja) | 1998-10-28 | 2010-12-22 | 株式会社東芝 | メモリ混載ロジックlsi |
JP2001101900A (ja) | 1999-10-01 | 2001-04-13 | Hitachi Ltd | 半導体集積回路装置 |
JP4212257B2 (ja) * | 2001-04-26 | 2009-01-21 | 株式会社東芝 | 半導体集積回路 |
JP2004039896A (ja) * | 2002-07-04 | 2004-02-05 | Matsushita Electric Ind Co Ltd | 半導体装置 |
-
2003
- 2003-07-15 JP JP2003274652A patent/JP4051008B2/ja not_active Expired - Fee Related
-
2004
- 2004-07-15 CN CNB2004100698946A patent/CN100414648C/zh not_active Expired - Fee Related
- 2004-07-15 US US10/891,041 patent/US7379349B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20050015690A1 (en) | 2005-01-20 |
US7379349B2 (en) | 2008-05-27 |
JP2005038511A (ja) | 2005-02-10 |
CN100414648C (zh) | 2008-08-27 |
CN1577634A (zh) | 2005-02-09 |
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