JP4014116B2 - フィールドプログラマブルプロセッサアレイ - Google Patents

フィールドプログラマブルプロセッサアレイ Download PDF

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Publication number
JP4014116B2
JP4014116B2 JP53175998A JP53175998A JP4014116B2 JP 4014116 B2 JP4014116 B2 JP 4014116B2 JP 53175998 A JP53175998 A JP 53175998A JP 53175998 A JP53175998 A JP 53175998A JP 4014116 B2 JP4014116 B2 JP 4014116B2
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Japan
Prior art keywords
switching section
processing means
signal path
switching
integrated circuit
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Expired - Lifetime
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JP53175998A
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English (en)
Japanese (ja)
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JP2001509337A5 (enExample
JP2001509337A (ja
Inventor
マーシャル，アラン
スタンスフィールド，トニー
ヴィルミン，ジャン
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Elixent Ltd
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Elixent Ltd
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Publication of JP2001509337A5 publication Critical patent/JP2001509337A5/ja
Application granted granted Critical
Publication of JP4014116B2 publication Critical patent/JP4014116B2/ja
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP53175998A 1997-01-29 1998-01-28 フィールドプログラマブルプロセッサアレイ Expired - Lifetime JP4014116B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP97300563.0 1997-01-29
EP97300563A EP0858168A1 (en) 1997-01-29 1997-01-29 Field programmable processor array
PCT/GB1998/000262 WO1998033277A1 (en) 1997-01-29 1998-01-28 Field programmable processor arrays

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2007165208A Division JP2007329936A (ja) 1997-01-29 2007-06-22 フィールドプログラマブルプロセッサアレイ

Publications (3)

Publication Number Publication Date
JP2001509337A JP2001509337A (ja) 2001-07-10
JP2001509337A5 JP2001509337A5 (enExample) 2006-03-30
JP4014116B2 true JP4014116B2 (ja) 2007-11-28

Family

ID=8229199

Family Applications (2)

Application Number Title Priority Date Filing Date
JP53175998A Expired - Lifetime JP4014116B2 (ja) 1997-01-29 1998-01-28 フィールドプログラマブルプロセッサアレイ
JP2007165208A Withdrawn JP2007329936A (ja) 1997-01-29 2007-06-22 フィールドプログラマブルプロセッサアレイ

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2007165208A Withdrawn JP2007329936A (ja) 1997-01-29 2007-06-22 フィールドプログラマブルプロセッサアレイ

Country Status (5)

Country Link
US (2) US6252792B1 (enExample)
EP (1) EP0858168A1 (enExample)
JP (2) JP4014116B2 (enExample)
DE (1) DE69812898T2 (enExample)
WO (1) WO1998033277A1 (enExample)

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DE19651075A1 (de) 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Einheit zur Verarbeitung von numerischen und logischen Operationen, zum Einsatz in Prozessoren (CPU's), Mehrrechnersystemen, Datenflußprozessoren (DFP's), digitalen Signal Prozessoren (DSP's) oder dergleichen
DE19654595A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
ATE243390T1 (de) 1996-12-27 2003-07-15 Pact Inf Tech Gmbh Verfahren zum selbständigen dynamischen umladen von datenflussprozessoren (dfps) sowie bausteinen mit zwei- oder mehrdimensionalen programmierbaren zellstrukturen (fpgas, dpgas, o.dgl.)
EP0858168A1 (en) 1997-01-29 1998-08-12 Hewlett-Packard Company Field programmable processor array
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
DE19861088A1 (de) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
US8230411B1 (en) 1999-06-10 2012-07-24 Martin Vorbach Method for interleaving a program over a plurality of cells
EP1061439A1 (en) 1999-06-15 2000-12-20 Hewlett-Packard Company Memory and instructions in computer architecture containing processor and coprocessor
US6600959B1 (en) * 2000-02-04 2003-07-29 International Business Machines Corporation Method and apparatus for implementing microprocessor control logic using dynamic programmable logic arrays
US6756811B2 (en) * 2000-03-10 2004-06-29 Easic Corporation Customizable and programmable cell array
US6331790B1 (en) * 2000-03-10 2001-12-18 Easic Corporation Customizable and programmable cell array
EP1342158B1 (de) 2000-06-13 2010-08-04 Richter, Thomas Pipeline ct-protokolle und -kommunikation
US7383424B1 (en) 2000-06-15 2008-06-03 Hewlett-Packard Development Company, L.P. Computer architecture containing processor and decoupled coprocessor
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US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US20070299993A1 (en) * 2001-03-05 2007-12-27 Pact Xpp Technologies Ag Method and Device for Treating and Processing Data
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US7581076B2 (en) * 2001-03-05 2009-08-25 Pact Xpp Technologies Ag Methods and devices for treating and/or processing data
EP1402382B1 (de) 2001-06-20 2010-08-18 Richter, Thomas Verfahren zur bearbeitung von daten
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US7577822B2 (en) 2001-12-14 2009-08-18 Pact Xpp Technologies Ag Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization
US8281108B2 (en) 2002-01-19 2012-10-02 Martin Vorbach Reconfigurable general purpose processor having time restricted configurations
DE50310198D1 (de) 2002-02-18 2008-09-04 Pact Xpp Technologies Ag Bussysteme und rekonfigurationsverfahren
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
AU2003286131A1 (en) 2002-08-07 2004-03-19 Pact Xpp Technologies Ag Method and device for processing data
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
WO2004038599A1 (de) 2002-09-06 2004-05-06 Pact Xpp Technologies Ag Rekonfigurierbare sequenzerstruktur
JP4423953B2 (ja) * 2003-07-09 2010-03-03 株式会社日立製作所 半導体集積回路
JP4700611B2 (ja) 2003-08-28 2011-06-15 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト データ処理装置およびデータ処理方法
WO2011061099A1 (en) 2004-04-02 2011-05-26 Panasonic Corporation Reset/load and signal distribution network
EP1974265A1 (de) 2006-01-18 2008-10-01 PACT XPP Technologies AG Hardwaredefinitionsverfahren
WO2008028330A1 (en) * 2006-08-31 2008-03-13 Beijing Xizheng Microelectronics Co. Ltd. A programmable interconnect network for logic array
US8964760B2 (en) 2009-03-09 2015-02-24 Nec Corporation Interprocessor communication system and communication method, network switch, and parallel calculation system
EP2326009A1 (en) 2009-11-20 2011-05-25 Panasonic Corporation Reset/load and signal distribution network
EP2328096A1 (en) 2009-11-27 2011-06-01 Panasonic Corporation Route-through in embedded functional units
EP2360601A1 (en) * 2010-02-16 2011-08-24 Panasonic Corporation Programmable logic device with custom blocks
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Also Published As

Publication number Publication date
WO1998033277A1 (en) 1998-07-30
DE69812898T2 (de) 2003-12-11
US6252792B1 (en) 2001-06-26
US6542394B2 (en) 2003-04-01
US20010035772A1 (en) 2001-11-01
DE69812898D1 (de) 2003-05-08
JP2001509337A (ja) 2001-07-10
JP2007329936A (ja) 2007-12-20
EP0858168A1 (en) 1998-08-12

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