DE69812898D1 - Nutzerprogrammierbare prozessorfelder - Google Patents

Nutzerprogrammierbare prozessorfelder

Info

Publication number
DE69812898D1
DE69812898D1 DE69812898T DE69812898T DE69812898D1 DE 69812898 D1 DE69812898 D1 DE 69812898D1 DE 69812898 T DE69812898 T DE 69812898T DE 69812898 T DE69812898 T DE 69812898T DE 69812898 D1 DE69812898 D1 DE 69812898D1
Authority
DE
Germany
Prior art keywords
programmable processor
user programmable
processor fields
fields
user
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69812898T
Other languages
English (en)
Other versions
DE69812898T2 (de
Inventor
Alan Marshall
Tony Stansfield
Jean Vuillemin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Elixent Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elixent Ltd filed Critical Elixent Ltd
Application granted granted Critical
Publication of DE69812898D1 publication Critical patent/DE69812898D1/de
Publication of DE69812898T2 publication Critical patent/DE69812898T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE69812898T 1997-01-29 1998-01-28 Nutzerprogrammierbare prozessorfelder Expired - Lifetime DE69812898T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP97300563A EP0858168A1 (de) 1997-01-29 1997-01-29 Feldprogrammierbarer Gatterprozessor
PCT/GB1998/000262 WO1998033277A1 (en) 1997-01-29 1998-01-28 Field programmable processor arrays

Publications (2)

Publication Number Publication Date
DE69812898D1 true DE69812898D1 (de) 2003-05-08
DE69812898T2 DE69812898T2 (de) 2003-12-11

Family

ID=8229199

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69812898T Expired - Lifetime DE69812898T2 (de) 1997-01-29 1998-01-28 Nutzerprogrammierbare prozessorfelder

Country Status (5)

Country Link
US (2) US6252792B1 (de)
EP (1) EP0858168A1 (de)
JP (2) JP4014116B2 (de)
DE (1) DE69812898T2 (de)
WO (1) WO1998033277A1 (de)

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DE19654595A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
JP3961028B2 (ja) 1996-12-27 2007-08-15 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト データフロープロセッサ（ｄｆｐ）の自動的なダイナミックアンロード方法並びに２次元または３次元のプログラミング可能なセルストラクチャを有するモジュール（ｆｐｇａ，ｄｐｇａ等）
EP0858168A1 (de) 1997-01-29 1998-08-12 Hewlett-Packard Company Feldprogrammierbarer Gatterprozessor
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
DE19861088A1 (de) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
WO2000077652A2 (de) 1999-06-10 2000-12-21 Pact Informationstechnologie Gmbh Sequenz-partitionierung auf zellstrukturen
EP1061439A1 (de) 1999-06-15 2000-12-20 Hewlett-Packard Company Speicher und Befehlen in Rechnerarchitektur mit Prozessor und Coprozessor
US6600959B1 (en) * 2000-02-04 2003-07-29 International Business Machines Corporation Method and apparatus for implementing microprocessor control logic using dynamic programmable logic arrays
US6331790B1 (en) * 2000-03-10 2001-12-18 Easic Corporation Customizable and programmable cell array
US6756811B2 (en) * 2000-03-10 2004-06-29 Easic Corporation Customizable and programmable cell array
EP2226732A3 (de) 2000-06-13 2016-04-06 PACT XPP Technologies AG Cachehierarchie für einen Multicore-Prozessor
US7383424B1 (en) 2000-06-15 2008-06-03 Hewlett-Packard Development Company, L.P. Computer architecture containing processor and decoupled coprocessor
AU2001289737A1 (en) * 2000-07-24 2002-02-05 Pact Informationstechnolgie Gmbh Integrated circuit
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
ATE437476T1 (de) * 2000-10-06 2009-08-15 Pact Xpp Technologies Ag Zellenanordnung mit segmentierter zwischenzellstruktur
US7581076B2 (en) * 2001-03-05 2009-08-25 Pact Xpp Technologies Ag Methods and devices for treating and/or processing data
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US20070299993A1 (en) * 2001-03-05 2007-12-27 Pact Xpp Technologies Ag Method and Device for Treating and Processing Data
EP1402382B1 (de) 2001-06-20 2010-08-18 Richter, Thomas Verfahren zur bearbeitung von daten
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
DE10392560D2 (de) 2002-01-19 2005-05-12 Pact Xpp Technologies Ag Reconfigurierbarer Prozessor
DE10390689D2 (de) 2002-02-18 2005-02-10 Pact Xpp Technologies Ag Bussysteme und Rekonfigurationsverfahren
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
WO2004021176A2 (de) 2002-08-07 2004-03-11 Pact Xpp Technologies Ag Verfahren und vorrichtung zur datenverarbeitung
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
AU2003289844A1 (en) 2002-09-06 2004-05-13 Pact Xpp Technologies Ag Reconfigurable sequencer structure
JP4423953B2 (ja) * 2003-07-09 2010-03-03 株式会社日立製作所 半導体集積回路
EP1676208A2 (de) 2003-08-28 2006-07-05 PACT XPP Technologies AG Datenverarbeitungseinrichtung und verfahren
WO2011061099A1 (en) 2004-04-02 2011-05-26 Panasonic Corporation Reset/load and signal distribution network
US8250503B2 (en) 2006-01-18 2012-08-21 Martin Vorbach Hardware definition method including determining whether to implement a function as hardware or software
WO2008028330A1 (en) * 2006-08-31 2008-03-13 Beijing Xizheng Microelectronics Co. Ltd. A programmable interconnect network for logic array
US8964760B2 (en) 2009-03-09 2015-02-24 Nec Corporation Interprocessor communication system and communication method, network switch, and parallel calculation system
EP2326009A1 (de) 2009-11-20 2011-05-25 Panasonic Corporation Rückstellung-/Lade- und Signalverteilungsnetzwerk
EP2328096A1 (de) 2009-11-27 2011-06-01 Panasonic Corporation Durchführung in eingebetteten Funktionseinheiten
EP2360601A1 (de) * 2010-02-16 2011-08-24 Panasonic Corporation Programmierbare logische Vorrichtung mit maßgeschneiderten Blöcken
EP2367117A1 (de) 2010-03-10 2011-09-21 Panasonic Corporation Heterogenes Routingnetzwerk
WO2012016597A1 (en) 2010-08-05 2012-02-09 Panasonic Corporation Overridable elements in reconfigurable logic devices
EP2416241A1 (de) 2010-08-06 2012-02-08 Panasonic Corporation Konfigurierbare arithmetisch-logische Einheit
WO2012059704A1 (en) 2010-11-04 2012-05-10 Panasonic Corporation Signal propagation control in programmable logic devices

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US4236204A (en) 1978-03-13 1980-11-25 Motorola, Inc. Instruction set modifier register
US4698751A (en) 1984-07-13 1987-10-06 Ford Aerospace & Communications Corporation Systolic array for solving cyclic loop dependent algorithms
JPS62192094A (ja) 1986-02-18 1987-08-22 Nec Corp Ｅｐｒｏｍ装置
US4775952A (en) 1986-05-29 1988-10-04 General Electric Company Parallel processing system apparatus
US4766566A (en) 1986-08-18 1988-08-23 International Business Machines Corp. Performance enhancement scheme for a RISC type VLSI processor using dual execution units for parallel instruction processing
US5233539A (en) * 1989-08-15 1993-08-03 Advanced Micro Devices, Inc. Programmable gate array with improved interconnect structure, input/output structure and configurable logic block
US5204556A (en) * 1991-05-06 1993-04-20 Lattice Semiconductor Corporation Programmable interconnect structure for logic blocks
US5291431A (en) 1991-06-03 1994-03-01 General Electric Company Array multiplier adapted for tiled layout by silicon compiler
US5208491A (en) * 1992-01-07 1993-05-04 Washington Research Foundation Field programmable gate array
US5498975A (en) * 1992-11-19 1996-03-12 Altera Corporation Implementation of redundancy on a programmable logic device
US5457644A (en) 1993-08-20 1995-10-10 Actel Corporation Field programmable digital signal processing array integrated circuit
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US5586277A (en) 1994-03-01 1996-12-17 Intel Corporation Method for parallel steering of fixed length fields containing a variable length instruction from an instruction buffer to parallel decoders
GB2289354B (en) 1994-05-03 1997-08-27 Advanced Risc Mach Ltd Multiple instruction set mapping
US5426379A (en) 1994-07-29 1995-06-20 Xilinx, Inc. Field programmable gate array with built-in bitstream data expansion
JPH08185320A (ja) 1994-12-28 1996-07-16 Mitsubishi Electric Corp 半導体集積回路
US5680597A (en) 1995-01-26 1997-10-21 International Business Machines Corporation System with flexible local control for modifying same instruction partially in different processor of a SIMD computer system to execute dissimilar sequences of instructions
US5493239A (en) 1995-01-31 1996-02-20 Motorola, Inc. Circuit and method of configuring a field programmable gate array
US5659785A (en) 1995-02-10 1997-08-19 International Business Machines Corporation Array processor communication architecture with broadcast processor instructions
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KR100212142B1 (ko) 1996-09-12 1999-08-02 윤종용 매크로 명령기능을 가진 동기식 반도체 메모리장치와 매크로 명령의 저장 및 실행방법
EP0858168A1 (de) 1997-01-29 1998-08-12 Hewlett-Packard Company Feldprogrammierbarer Gatterprozessor
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JP3123977B2 (ja) 1998-06-04 2001-01-15 日本電気株式会社 プログラマブル機能ブロック

Also Published As

Publication number Publication date
US6252792B1 (en) 2001-06-26
DE69812898T2 (de) 2003-12-11
US20010035772A1 (en) 2001-11-01
US6542394B2 (en) 2003-04-01
EP0858168A1 (de) 1998-08-12
WO1998033277A1 (en) 1998-07-30
JP2001509337A (ja) 2001-07-10
JP4014116B2 (ja) 2007-11-28
JP2007329936A (ja) 2007-12-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC EUROPE LTD., UXBRIDGE, MIDDLESEX, GB

8327 Change in the person/name/address of the patent owner

Owner name: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., KADO, JP

8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP