DE69812898T2 - Nutzerprogrammierbare prozessorfelder - Google Patents

Nutzerprogrammierbare prozessorfelder

Info

Publication number
DE69812898T2
DE69812898T2 DE69812898T DE69812898T DE69812898T2 DE 69812898 T2 DE69812898 T2 DE 69812898T2 DE 69812898 T DE69812898 T DE 69812898T DE 69812898 T DE69812898 T DE 69812898T DE 69812898 T2 DE69812898 T2 DE 69812898T2
Authority
DE
Germany
Prior art keywords
integrated circuit
column
input
switching
row
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69812898T
Other languages
German (de)
English (en)
Other versions
DE69812898D1 (de
Inventor
Alan Marshall
Tony Stansfield
Jean Vuillemin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Elixent Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elixent Ltd filed Critical Elixent Ltd
Application granted granted Critical
Publication of DE69812898D1 publication Critical patent/DE69812898D1/de
Publication of DE69812898T2 publication Critical patent/DE69812898T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE69812898T 1997-01-29 1998-01-28 Nutzerprogrammierbare prozessorfelder Expired - Lifetime DE69812898T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP97300563A EP0858168A1 (en) 1997-01-29 1997-01-29 Field programmable processor array
PCT/GB1998/000262 WO1998033277A1 (en) 1997-01-29 1998-01-28 Field programmable processor arrays

Publications (2)

Publication Number Publication Date
DE69812898D1 DE69812898D1 (de) 2003-05-08
DE69812898T2 true DE69812898T2 (de) 2003-12-11

Family

ID=8229199

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69812898T Expired - Lifetime DE69812898T2 (de) 1997-01-29 1998-01-28 Nutzerprogrammierbare prozessorfelder

Country Status (5)

Country Link
US (2) US6252792B1 (enExample)
EP (1) EP0858168A1 (enExample)
JP (2) JP4014116B2 (enExample)
DE (1) DE69812898T2 (enExample)
WO (1) WO1998033277A1 (enExample)

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DE19654595A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
DE59710317D1 (de) 1996-12-27 2003-07-24 Pact Inf Tech Gmbh VERFAHREN ZUM SELBSTÄNDIGEN DYNAMISCHEN UMLADEN VON DATENFLUSSPROZESSOREN (DFPs) SOWIE BAUSTEINEN MIT ZWEI- ODER MEHRDIMENSIONALEN PROGRAMMIERBAREN ZELLSTRUKTUREN (FPGAs, DPGAs, o.dgl.)
EP0858168A1 (en) 1997-01-29 1998-08-12 Hewlett-Packard Company Field programmable processor array
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
DE19861088A1 (de) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
EP1228440B1 (de) 1999-06-10 2017-04-05 PACT XPP Technologies AG Sequenz-partitionierung auf zellstrukturen
EP1061439A1 (en) 1999-06-15 2000-12-20 Hewlett-Packard Company Memory and instructions in computer architecture containing processor and coprocessor
US6600959B1 (en) * 2000-02-04 2003-07-29 International Business Machines Corporation Method and apparatus for implementing microprocessor control logic using dynamic programmable logic arrays
US6331790B1 (en) * 2000-03-10 2001-12-18 Easic Corporation Customizable and programmable cell array
US6756811B2 (en) * 2000-03-10 2004-06-29 Easic Corporation Customizable and programmable cell array
DE50115584D1 (de) 2000-06-13 2010-09-16 Krass Maren Pipeline ct-protokolle und -kommunikation
US7383424B1 (en) 2000-06-15 2008-06-03 Hewlett-Packard Development Company, L.P. Computer architecture containing processor and decoupled coprocessor
EP1377919A2 (de) * 2000-07-24 2004-01-07 PACT XPP Technologies AG Integrierter schaltkreis
US7595659B2 (en) * 2000-10-09 2009-09-29 Pact Xpp Technologies Ag Logic cell array and bus system
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US7581076B2 (en) * 2001-03-05 2009-08-25 Pact Xpp Technologies Ag Methods and devices for treating and/or processing data
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US20070299993A1 (en) * 2001-03-05 2007-12-27 Pact Xpp Technologies Ag Method and Device for Treating and Processing Data
EP2224330B1 (de) 2001-06-20 2012-05-09 Krass, Maren Verfahren und gerät zum partitionieren von grossen rechnerprogrammen
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US7577822B2 (en) 2001-12-14 2009-08-18 Pact Xpp Technologies Ag Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization
US8281108B2 (en) 2002-01-19 2012-10-02 Martin Vorbach Reconfigurable general purpose processor having time restricted configurations
EP1514193B1 (de) 2002-02-18 2008-07-23 PACT XPP Technologies AG Bussysteme und rekonfigurationsverfahren
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
WO2004021176A2 (de) 2002-08-07 2004-03-11 Pact Xpp Technologies Ag Verfahren und vorrichtung zur datenverarbeitung
WO2004038599A1 (de) 2002-09-06 2004-05-06 Pact Xpp Technologies Ag Rekonfigurierbare sequenzerstruktur
JP4423953B2 (ja) * 2003-07-09 2010-03-03 株式会社日立製作所 半導体集積回路
JP4700611B2 (ja) 2003-08-28 2011-06-15 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト データ処理装置およびデータ処理方法
WO2011061099A1 (en) 2004-04-02 2011-05-26 Panasonic Corporation Reset/load and signal distribution network
WO2007082730A1 (de) 2006-01-18 2007-07-26 Pact Xpp Technologies Ag Hardwaredefinitionsverfahren
US7928764B2 (en) * 2006-08-31 2011-04-19 Agate Logic (Beijing), Inc. Programmable interconnect network for logic array
US8964760B2 (en) 2009-03-09 2015-02-24 Nec Corporation Interprocessor communication system and communication method, network switch, and parallel calculation system
EP2326009A1 (en) 2009-11-20 2011-05-25 Panasonic Corporation Reset/load and signal distribution network
EP2328096A1 (en) 2009-11-27 2011-06-01 Panasonic Corporation Route-through in embedded functional units
EP2360601A1 (en) 2010-02-16 2011-08-24 Panasonic Corporation Programmable logic device with custom blocks
EP2367117A1 (en) 2010-03-10 2011-09-21 Panasonic Corporation Heterogeneous routing network
WO2012016597A1 (en) 2010-08-05 2012-02-09 Panasonic Corporation Overridable elements in reconfigurable logic devices
EP2416241A1 (en) 2010-08-06 2012-02-08 Panasonic Corporation Configurable arithmetic logic unit
WO2012059704A1 (en) 2010-11-04 2012-05-10 Panasonic Corporation Signal propagation control in programmable logic devices

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US4766566A (en) 1986-08-18 1988-08-23 International Business Machines Corp. Performance enhancement scheme for a RISC type VLSI processor using dual execution units for parallel instruction processing
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US5208491A (en) * 1992-01-07 1993-05-04 Washington Research Foundation Field programmable gate array
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US5457644A (en) 1993-08-20 1995-10-10 Actel Corporation Field programmable digital signal processing array integrated circuit
EP0698312A1 (en) * 1994-02-15 1996-02-28 Xilinx, Inc. Tile based architecture for fpga
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Also Published As

Publication number Publication date
US6252792B1 (en) 2001-06-26
WO1998033277A1 (en) 1998-07-30
JP2001509337A (ja) 2001-07-10
DE69812898D1 (de) 2003-05-08
US6542394B2 (en) 2003-04-01
US20010035772A1 (en) 2001-11-01
JP2007329936A (ja) 2007-12-20
JP4014116B2 (ja) 2007-11-28
EP0858168A1 (en) 1998-08-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC EUROPE LTD., UXBRIDGE, MIDDLESEX, GB

8327 Change in the person/name/address of the patent owner

Owner name: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., KADO, JP

8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP