JP4001700B2 - Ｃａｓレイテンシー制御回路及びこれを採用したｓｄｒａｍ - Google Patents

Ｃａｓレイテンシー制御回路及びこれを採用したｓｄｒａｍ Download PDF

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Publication number
JP4001700B2
JP4001700B2 JP33109399A JP33109399A JP4001700B2 JP 4001700 B2 JP4001700 B2 JP 4001700B2 JP 33109399 A JP33109399 A JP 33109399A JP 33109399 A JP33109399 A JP 33109399A JP 4001700 B2 JP4001700 B2 JP 4001700B2
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JP
Japan
Prior art keywords
data
cas latency
signal
control circuit
control signal
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Expired - Fee Related
Application number
JP33109399A
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English (en)
Japanese (ja)
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JP2000163954A (ja
Inventor
金東均
金聖勲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
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Hynix Semiconductor Inc
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Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of JP2000163954A publication Critical patent/JP2000163954A/ja
Application granted granted Critical
Publication of JP4001700B2 publication Critical patent/JP4001700B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
JP33109399A 1998-11-24 1999-11-22 Ｃａｓレイテンシー制御回路及びこれを採用したｓｄｒａｍ Expired - Fee Related JP4001700B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR50441/1998 1998-11-24
KR1019980050441A KR100308119B1 (ko) 1998-11-24 1998-11-24 카스(CAS)레이턴시(Latency)제어회로

Publications (2)

Publication Number Publication Date
JP2000163954A JP2000163954A (ja) 2000-06-16
JP4001700B2 true JP4001700B2 (ja) 2007-10-31

Family

ID=19559487

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33109399A Expired - Fee Related JP4001700B2 (ja) 1998-11-24 1999-11-22 Ｃａｓレイテンシー制御回路及びこれを採用したｓｄｒａｍ

Country Status (3)

Country Link
JP (1) JP4001700B2 (de)
KR (1) KR100308119B1 (de)
DE (1) DE19953323B4 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6292428B1 (en) 1998-02-03 2001-09-18 Fujitsu Limited Semiconductor device reconciling different timing signals
KR100428759B1 (ko) * 2001-06-25 2004-04-28 삼성전자주식회사 반도체 메모리 장치 및 이 장치의 데이터 리드 방법
KR100562645B1 (ko) * 2004-10-29 2006-03-20 주식회사 하이닉스반도체 반도체 기억 소자
KR100609621B1 (ko) * 2005-07-19 2006-08-08 삼성전자주식회사 메모리 블락별로 레이턴시 제어가 가능한 동기식 반도체메모리 장치
KR101013555B1 (ko) * 2008-10-09 2011-02-14 주식회사 하이닉스반도체 반도체 패키지 및 이의 제조 방법
JP6054017B2 (ja) * 2011-07-13 2016-12-27 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体記憶装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03222192A (ja) * 1990-01-26 1991-10-01 Hitachi Ltd 半導体集積回路装置
US5802005A (en) * 1996-09-23 1998-09-01 Texas Instruments Incorporated Four bit pre-fetch sDRAM column select architecture

Also Published As

Publication number Publication date
KR100308119B1 (ko) 2001-10-20
DE19953323B4 (de) 2008-04-24
JP2000163954A (ja) 2000-06-16
KR20000033542A (ko) 2000-06-15
DE19953323A1 (de) 2000-05-25

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