JP3992786B2 - 論理検証方法、論理検証装置及び記録媒体 - Google Patents

論理検証方法、論理検証装置及び記録媒体 Download PDF

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Publication number
JP3992786B2
JP3992786B2 JP14951997A JP14951997A JP3992786B2 JP 3992786 B2 JP3992786 B2 JP 3992786B2 JP 14951997 A JP14951997 A JP 14951997A JP 14951997 A JP14951997 A JP 14951997A JP 3992786 B2 JP3992786 B2 JP 3992786B2
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JP
Japan
Prior art keywords
event
logic
incoming
time
oscillation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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JP14951997A
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English (en)
Japanese (ja)
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JPH10340279A5 (enExample
JPH10340279A (ja
Inventor
隆昌 奥村
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Fujitsu Ltd
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Fujitsu Ltd
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Publication date
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Priority to JP14951997A priority Critical patent/JP3992786B2/ja
Priority to US09/026,530 priority patent/US6032277A/en
Publication of JPH10340279A publication Critical patent/JPH10340279A/ja
Publication of JPH10340279A5 publication Critical patent/JPH10340279A5/ja
Application granted granted Critical
Publication of JP3992786B2 publication Critical patent/JP3992786B2/ja
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Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
JP14951997A 1997-06-06 1997-06-06 論理検証方法、論理検証装置及び記録媒体 Expired - Lifetime JP3992786B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP14951997A JP3992786B2 (ja) 1997-06-06 1997-06-06 論理検証方法、論理検証装置及び記録媒体
US09/026,530 US6032277A (en) 1997-06-06 1998-02-20 Method and apparatus for logic testing an integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14951997A JP3992786B2 (ja) 1997-06-06 1997-06-06 論理検証方法、論理検証装置及び記録媒体

Publications (3)

Publication Number Publication Date
JPH10340279A JPH10340279A (ja) 1998-12-22
JPH10340279A5 JPH10340279A5 (enExample) 2005-04-14
JP3992786B2 true JP3992786B2 (ja) 2007-10-17

Family

ID=15476921

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14951997A Expired - Lifetime JP3992786B2 (ja) 1997-06-06 1997-06-06 論理検証方法、論理検証装置及び記録媒体

Country Status (2)

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US (1) US6032277A (enExample)
JP (1) JP3992786B2 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6226765B1 (en) * 1999-02-26 2001-05-01 Advantest Corp. Event based test system data memory compression
US7171602B2 (en) 2001-12-31 2007-01-30 Advantest Corp. Event processing apparatus and method for high speed event based test system
CN100477528C (zh) * 2002-07-03 2009-04-08 艾利森电话股份有限公司 锁相环电路、包括锁相环电路的电子设备以及产生周期信号的方法
KR100910086B1 (ko) 2004-12-29 2009-07-30 텔레폰악티에볼라겟 엘엠 에릭슨(펍) 위상 고정 루프 회로, 위상 고정 루프 회로를 포함하는전자 장치 및 주기 신호를 발생시키는 방법

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5212443A (en) * 1990-09-05 1993-05-18 Schlumberger Technologies, Inc. Event sequencer for automatic test equipment
JPH095397A (ja) * 1995-06-21 1997-01-10 Fujitsu Ltd 論理シミュレーション方法

Also Published As

Publication number Publication date
US6032277A (en) 2000-02-29
JPH10340279A (ja) 1998-12-22

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