JP3947750B2 - 半導体装置の製造方法及び半導体装置 - Google Patents

半導体装置の製造方法及び半導体装置 Download PDF

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Publication number
JP3947750B2
JP3947750B2 JP2005214601A JP2005214601A JP3947750B2 JP 3947750 B2 JP3947750 B2 JP 3947750B2 JP 2005214601 A JP2005214601 A JP 2005214601A JP 2005214601 A JP2005214601 A JP 2005214601A JP 3947750 B2 JP3947750 B2 JP 3947750B2
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JP
Japan
Prior art keywords
semiconductor device
surface side
semiconductor element
lead frame
frame material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2005214601A
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English (en)
Japanese (ja)
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JP2005317998A5 (enExample
JP2005317998A (ja
Inventor
高士 中島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui High Tec Inc
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Mitsui High Tec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui High Tec Inc filed Critical Mitsui High Tec Inc
Priority to JP2005214601A priority Critical patent/JP3947750B2/ja
Publication of JP2005317998A publication Critical patent/JP2005317998A/ja
Publication of JP2005317998A5 publication Critical patent/JP2005317998A5/ja
Application granted granted Critical
Publication of JP3947750B2 publication Critical patent/JP3947750B2/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP2005214601A 2005-07-25 2005-07-25 半導体装置の製造方法及び半導体装置 Expired - Lifetime JP3947750B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005214601A JP3947750B2 (ja) 2005-07-25 2005-07-25 半導体装置の製造方法及び半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005214601A JP3947750B2 (ja) 2005-07-25 2005-07-25 半導体装置の製造方法及び半導体装置

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP19322599A Division JP3780122B2 (ja) 1999-07-07 1999-07-07 半導体装置の製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2007067330A Division JP4137981B2 (ja) 2007-03-15 2007-03-15 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2005317998A JP2005317998A (ja) 2005-11-10
JP2005317998A5 JP2005317998A5 (enExample) 2007-02-01
JP3947750B2 true JP3947750B2 (ja) 2007-07-25

Family

ID=35445024

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005214601A Expired - Lifetime JP3947750B2 (ja) 2005-07-25 2005-07-25 半導体装置の製造方法及び半導体装置

Country Status (1)

Country Link
JP (1) JP3947750B2 (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101651126A (zh) * 2008-08-12 2010-02-17 三星电子株式会社 芯片封装件及其制造方法
WO2012005435A1 (en) * 2010-07-08 2012-01-12 Lg Innotek Co., Ltd. Manufacturing method of chip package and chip package manufactured using the same
KR101445759B1 (ko) 2010-03-30 2014-10-06 해성디에스 주식회사 리드 프레임 및 이를 사용한 집적회로 소자

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090230524A1 (en) 2008-03-14 2009-09-17 Pao-Huei Chang Chien Semiconductor chip package having ground and power regions and manufacturing methods thereof
TWI372458B (en) 2008-05-12 2012-09-11 Advanced Semiconductor Eng Stacked type chip package structure
US20100044850A1 (en) 2008-08-21 2010-02-25 Advanced Semiconductor Engineering, Inc. Advanced quad flat non-leaded package structure and manufacturing method thereof
US8659131B2 (en) 2008-09-25 2014-02-25 Lg Innotek Co., Ltd. Structure for multi-row lead frame and semiconductor package capable of minimizing an under-cut
KR101064755B1 (ko) 2008-12-24 2011-09-15 엘지이노텍 주식회사 다열 리드형 리드프레임 및 이를 이용한 반도체 패키지의 제조방법
WO2010099673A1 (en) 2009-03-06 2010-09-10 Kaixin Inc. Leadless integrated circuit package having high density contacts
US7858443B2 (en) 2009-03-09 2010-12-28 Utac Hong Kong Limited Leadless integrated circuit package having standoff contacts and die attach pad
KR101753416B1 (ko) 2009-04-03 2017-07-19 카이씬, 인코포레이티드 Ｉｃ 패키지용 리드프레임 및 제조방법
US8124447B2 (en) 2009-04-10 2012-02-28 Advanced Semiconductor Engineering, Inc. Manufacturing method of advanced quad flat non-leaded package
KR101668141B1 (ko) 2009-09-02 2016-10-20 카이씬, 인코포레이티드 Ｉｃ 패키지 및 이의 제조방법
JP2016171101A (ja) * 2015-03-11 2016-09-23 Ａｍテクノワークス株式会社 放熱基板の製造方法および放熱基板
US9570381B2 (en) 2015-04-02 2017-02-14 Advanced Semiconductor Engineering, Inc. Semiconductor packages and related manufacturing methods

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101651126A (zh) * 2008-08-12 2010-02-17 三星电子株式会社 芯片封装件及其制造方法
KR101445759B1 (ko) 2010-03-30 2014-10-06 해성디에스 주식회사 리드 프레임 및 이를 사용한 집적회로 소자
WO2012005435A1 (en) * 2010-07-08 2012-01-12 Lg Innotek Co., Ltd. Manufacturing method of chip package and chip package manufactured using the same

Also Published As

Publication number Publication date
JP2005317998A (ja) 2005-11-10

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