JP3946874B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP3946874B2
JP3946874B2 JP19080998A JP19080998A JP3946874B2 JP 3946874 B2 JP3946874 B2 JP 3946874B2 JP 19080998 A JP19080998 A JP 19080998A JP 19080998 A JP19080998 A JP 19080998A JP 3946874 B2 JP3946874 B2 JP 3946874B2
Authority
JP
Japan
Prior art keywords
electrode
semiconductor chip
substrate
electrically connected
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP19080998A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000021926A (ja
JP2000021926A5 (https=
Inventor
岩道 神代
栄 菊池
康弘 布川
静雄 近藤
徹朗 安達
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP19080998A priority Critical patent/JP3946874B2/ja
Priority to TW088110698A priority patent/TW473882B/zh
Priority to US09/345,505 priority patent/US6330165B1/en
Priority to DE69935182T priority patent/DE69935182T2/de
Priority to EP06027122A priority patent/EP1770777A3/en
Priority to EP99112588A priority patent/EP0971411B1/en
Publication of JP2000021926A publication Critical patent/JP2000021926A/ja
Priority to US09/970,668 priority patent/US6489680B2/en
Priority to US10/291,840 priority patent/US6943441B2/en
Priority to US11/194,701 priority patent/US7068521B2/en
Publication of JP2000021926A5 publication Critical patent/JP2000021926A5/ja
Priority to US11/451,579 priority patent/US20070001300A1/en
Application granted granted Critical
Publication of JP3946874B2 publication Critical patent/JP3946874B2/ja
Priority to US11/905,421 priority patent/US7525813B2/en
Priority to US12/394,421 priority patent/US7817437B2/en
Priority to US12/787,154 priority patent/US8295057B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07554—Controlling the environment, e.g. atmosphere composition or temperature changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Wire Bonding (AREA)
JP19080998A 1998-07-06 1998-07-06 半導体装置 Expired - Lifetime JP3946874B2 (ja)

Priority Applications (13)

Application Number Priority Date Filing Date Title
JP19080998A JP3946874B2 (ja) 1998-07-06 1998-07-06 半導体装置
TW088110698A TW473882B (en) 1998-07-06 1999-06-25 Semiconductor device
DE69935182T DE69935182T2 (de) 1998-07-06 1999-07-01 Halbleiteranordnung
EP06027122A EP1770777A3 (en) 1998-07-06 1999-07-01 Semiconductor device with a shielding bond wire
EP99112588A EP0971411B1 (en) 1998-07-06 1999-07-01 Semiconductor device
US09/345,505 US6330165B1 (en) 1998-07-06 1999-07-01 Semiconductor device
US09/970,668 US6489680B2 (en) 1998-07-06 2001-10-05 Semiconductor device
US10/291,840 US6943441B2 (en) 1998-07-06 2002-11-12 Semiconductor device
US11/194,701 US7068521B2 (en) 1998-07-06 2005-08-02 Semiconductor device
US11/451,579 US20070001300A1 (en) 1998-07-06 2006-06-13 Semiconductor device
US11/905,421 US7525813B2 (en) 1998-07-06 2007-10-01 Semiconductor device
US12/394,421 US7817437B2 (en) 1998-07-06 2009-02-27 Semiconductor device
US12/787,154 US8295057B2 (en) 1998-07-06 2010-05-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19080998A JP3946874B2 (ja) 1998-07-06 1998-07-06 半導体装置

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP2006339318A Division JP2007074001A (ja) 2006-12-18 2006-12-18 半導体装置
JP2006339316A Division JP2007074000A (ja) 2006-12-18 2006-12-18 半導体装置

Publications (3)

Publication Number Publication Date
JP2000021926A JP2000021926A (ja) 2000-01-21
JP2000021926A5 JP2000021926A5 (https=) 2005-10-27
JP3946874B2 true JP3946874B2 (ja) 2007-07-18

Family

ID=16264117

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19080998A Expired - Lifetime JP3946874B2 (ja) 1998-07-06 1998-07-06 半導体装置

Country Status (1)

Country Link
JP (1) JP3946874B2 (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW594888B (en) 2001-09-05 2004-06-21 Hitachi Ltd Semiconductor device and manufacturing method thereof and wireless communication device
CN101292349B (zh) * 2005-10-19 2011-09-28 Nxp股份有限公司 包括具有与接线耦接的电极的元件的器件
KR100950511B1 (ko) 2009-09-22 2010-03-30 테세라 리써치 엘엘씨 와이어 본딩 및 도전성 기준 소자에 의해 제어되는 임피던스를 포함하는 마이크로전자 어셈블리
KR100935854B1 (ko) 2009-09-22 2010-01-08 테세라 리써치 엘엘씨 와이어 본딩 및 기준 와이어 본딩에 의해 제어되는 임피던스를 가진 마이크로전자 어셈블리
US9136197B2 (en) 2010-09-16 2015-09-15 Tessera, Inc. Impedence controlled packages with metal sheet or 2-layer RDL
US8786083B2 (en) 2010-09-16 2014-07-22 Tessera, Inc. Impedance controlled packages with metal sheet or 2-layer RDL
US8581377B2 (en) 2010-09-16 2013-11-12 Tessera, Inc. TSOP with impedance control
US8853708B2 (en) 2010-09-16 2014-10-07 Tessera, Inc. Stacked multi-die packages with impedance control

Also Published As

Publication number Publication date
JP2000021926A (ja) 2000-01-21

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