JP3895884B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP3895884B2 JP3895884B2 JP08178699A JP8178699A JP3895884B2 JP 3895884 B2 JP3895884 B2 JP 3895884B2 JP 08178699 A JP08178699 A JP 08178699A JP 8178699 A JP8178699 A JP 8178699A JP 3895884 B2 JP3895884 B2 JP 3895884B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- back surface
- external connection
- semiconductor device
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP08178699A JP3895884B2 (ja) | 1999-03-25 | 1999-03-25 | 半導体装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP08178699A JP3895884B2 (ja) | 1999-03-25 | 1999-03-25 | 半導体装置 |
Related Child Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004285690A Division JP4017625B2 (ja) | 2004-09-30 | 2004-09-30 | 半導体装置の製造方法 |
| JP2006311131A Division JP2007073987A (ja) | 2006-11-17 | 2006-11-17 | 半導体モジュール |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2000277542A JP2000277542A (ja) | 2000-10-06 |
| JP2000277542A5 JP2000277542A5 (enExample) | 2005-06-23 |
| JP3895884B2 true JP3895884B2 (ja) | 2007-03-22 |
Family
ID=13756181
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP08178699A Expired - Lifetime JP3895884B2 (ja) | 1999-03-25 | 1999-03-25 | 半導体装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3895884B2 (enExample) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6744124B1 (en) * | 1999-12-10 | 2004-06-01 | Siliconix Incorporated | Semiconductor die package including cup-shaped leadframe |
| US7595547B1 (en) | 2005-06-13 | 2009-09-29 | Vishay-Siliconix | Semiconductor die package including cup-shaped leadframe |
| JP2002252318A (ja) | 2001-02-27 | 2002-09-06 | Nec Kansai Ltd | チップ型半導体装置 |
| JP3942500B2 (ja) | 2002-07-02 | 2007-07-11 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
| JP3853263B2 (ja) * | 2002-07-08 | 2006-12-06 | Necエレクトロニクス株式会社 | 半導体装置 |
| DE10249205B3 (de) * | 2002-10-22 | 2004-08-05 | Siemens Ag | Leistungsbauelementanordnung zur mechatronischen Integration von Leistungsbauelementen |
| DE10249206B3 (de) * | 2002-10-22 | 2004-07-01 | Siemens Ag | Verfahren zum Zusammenbau eines Leistungsbauelements |
| US6841865B2 (en) * | 2002-11-22 | 2005-01-11 | International Rectifier Corporation | Semiconductor device having clips for connecting to external elements |
| JP4222092B2 (ja) | 2003-05-07 | 2009-02-12 | 富士電機デバイステクノロジー株式会社 | 半導体ウェハ、半導体装置および半導体装置の製造方法 |
| US20070215997A1 (en) * | 2006-03-17 | 2007-09-20 | Martin Standing | Chip-scale package |
| EP4044226A1 (en) * | 2021-02-16 | 2022-08-17 | Nexperia B.V. | A semiconductor device and a method of manufacturing of a semiconductor device |
-
1999
- 1999-03-25 JP JP08178699A patent/JP3895884B2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000277542A (ja) | 2000-10-06 |
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