JP3889311B2 - プリント配線板 - Google Patents

プリント配線板 Download PDF

Info

Publication number
JP3889311B2
JP3889311B2 JP2002143609A JP2002143609A JP3889311B2 JP 3889311 B2 JP3889311 B2 JP 3889311B2 JP 2002143609 A JP2002143609 A JP 2002143609A JP 2002143609 A JP2002143609 A JP 2002143609A JP 3889311 B2 JP3889311 B2 JP 3889311B2
Authority
JP
Japan
Prior art keywords
printed wiring
wiring board
solder
solid pattern
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2002143609A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003338666A5 (enExample
JP2003338666A (ja
Inventor
剛 羽立
高宏 長嶺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2002143609A priority Critical patent/JP3889311B2/ja
Publication of JP2003338666A publication Critical patent/JP2003338666A/ja
Publication of JP2003338666A5 publication Critical patent/JP2003338666A5/ja
Application granted granted Critical
Publication of JP3889311B2 publication Critical patent/JP3889311B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Structure Of Printed Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
JP2002143609A 2002-05-17 2002-05-17 プリント配線板 Expired - Fee Related JP3889311B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002143609A JP3889311B2 (ja) 2002-05-17 2002-05-17 プリント配線板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002143609A JP3889311B2 (ja) 2002-05-17 2002-05-17 プリント配線板

Publications (3)

Publication Number Publication Date
JP2003338666A JP2003338666A (ja) 2003-11-28
JP2003338666A5 JP2003338666A5 (enExample) 2005-08-11
JP3889311B2 true JP3889311B2 (ja) 2007-03-07

Family

ID=29703566

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002143609A Expired - Fee Related JP3889311B2 (ja) 2002-05-17 2002-05-17 プリント配線板

Country Status (1)

Country Link
JP (1) JP3889311B2 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5186741B2 (ja) * 2006-08-18 2013-04-24 富士通セミコンダクター株式会社 回路基板及び半導体装置
DE102008054932B4 (de) * 2008-12-18 2011-12-01 Infineon Technologies Ag Leistungshalbleitermodul mit versteifter Bodenplatte
KR102059478B1 (ko) * 2017-09-15 2019-12-26 스템코 주식회사 회로 기판 및 그 제조 방법

Also Published As

Publication number Publication date
JP2003338666A (ja) 2003-11-28

Similar Documents

Publication Publication Date Title
US6541848B2 (en) Semiconductor device including stud bumps as external connection terminals
KR100445072B1 (ko) 리드 프레임을 이용한 범프 칩 캐리어 패키지 및 그의제조 방법
US6836011B2 (en) Semiconductor chip mounting structure with movable connection electrodes
JP4308608B2 (ja) 半導体装置
KR100541649B1 (ko) 테이프 배선 기판과 그를 이용한 반도체 칩 패키지
JP3679199B2 (ja) 半導体パッケージ装置
US7923835B2 (en) Package, electronic device, substrate having a separation region and a wiring layers, and method for manufacturing
JP2003007902A (ja) 電子部品の実装基板及び実装構造
WO2009130958A1 (ja) 配線基板、半導体装置、ならびに半導体装置の製造方法
JP2000068328A (ja) フリップチップ実装用配線基板
JP2001250876A (ja) 半導体装置及びその製造方法
JP3889311B2 (ja) プリント配線板
CN101866889B (zh) 无基板芯片封装及其制造方法
TWI387067B (zh) 無基板晶片封裝及其製造方法
JP3801188B2 (ja) 半導体装置および半導体装置の製造方法
JP4045708B2 (ja) 半導体装置、電子回路装置および製造方法
JP2005183868A (ja) 半導体装置およびその実装構造
JP2000031630A (ja) 半導体集積回路素子と配線基板との接続構造
JP3417292B2 (ja) 半導体装置
JP2000164786A (ja) 半導体パッケージ及び半導体装置
WO2017043480A1 (ja) 半導体パッケージ
JP2006128429A (ja) 回路基板および半導体装置
JP3692810B2 (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
KR100749592B1 (ko) 반도체 장치 및 그 제조방법
KR100246848B1 (ko) 랜드 그리드 어레이 및 이를 채용한 반도체 패키지

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050125

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050125

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060815

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20061005

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20061031

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20061129

R150 Certificate of patent (=grant) or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091208

Year of fee payment: 3

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101208

Year of fee payment: 4

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111208

Year of fee payment: 5

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111208

Year of fee payment: 5

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121208

Year of fee payment: 6

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121208

Year of fee payment: 6

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131208

Year of fee payment: 7

LAPS Cancellation because of no payment of annual fees