JP3889311B2 - プリント配線板 - Google Patents
プリント配線板 Download PDFInfo
- Publication number
- JP3889311B2 JP3889311B2 JP2002143609A JP2002143609A JP3889311B2 JP 3889311 B2 JP3889311 B2 JP 3889311B2 JP 2002143609 A JP2002143609 A JP 2002143609A JP 2002143609 A JP2002143609 A JP 2002143609A JP 3889311 B2 JP3889311 B2 JP 3889311B2
- Authority
- JP
- Japan
- Prior art keywords
- printed wiring
- wiring board
- solder
- solid pattern
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Structure Of Printed Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002143609A JP3889311B2 (ja) | 2002-05-17 | 2002-05-17 | プリント配線板 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002143609A JP3889311B2 (ja) | 2002-05-17 | 2002-05-17 | プリント配線板 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2003338666A JP2003338666A (ja) | 2003-11-28 |
| JP2003338666A5 JP2003338666A5 (enExample) | 2005-08-11 |
| JP3889311B2 true JP3889311B2 (ja) | 2007-03-07 |
Family
ID=29703566
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002143609A Expired - Fee Related JP3889311B2 (ja) | 2002-05-17 | 2002-05-17 | プリント配線板 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3889311B2 (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5186741B2 (ja) * | 2006-08-18 | 2013-04-24 | 富士通セミコンダクター株式会社 | 回路基板及び半導体装置 |
| DE102008054932B4 (de) * | 2008-12-18 | 2011-12-01 | Infineon Technologies Ag | Leistungshalbleitermodul mit versteifter Bodenplatte |
| KR102059478B1 (ko) * | 2017-09-15 | 2019-12-26 | 스템코 주식회사 | 회로 기판 및 그 제조 방법 |
-
2002
- 2002-05-17 JP JP2002143609A patent/JP3889311B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2003338666A (ja) | 2003-11-28 |
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