JP3872339B2

JP3872339B2 - Multilayer wiring board

Info

Publication number: JP3872339B2
Application number: JP2001395099A
Authority: JP
Inventors: 武志窪田
Original assignee: Kyocera Corp
Current assignee: Kyocera Corp
Priority date: 2001-12-26
Filing date: 2001-12-26
Publication date: 2007-01-24
Anticipated expiration: 2021-12-26
Also published as: JP2003198137A

Description

【０００１】
【発明の属する技術分野】
本発明は多層配線基板に関し、より詳細には混成集積回路装置や半導体素子を収容する半導体素子収納用パッケージ等に使用される多層配線基板に関するものである。
【０００２】
【従来の技術】
従来、混成集積回路装置や半導体素子収納用パッケージ等に使用される多層配線基板としては、配線導体を高密度に形成することを目的として、基板上に薄膜の絶縁層と配線導体層とから成る多層配線部を形成した多層配線基板が採用されていた。
【０００３】
かかる多層配線基板は、酸化アルミニウム質焼結体等から成る基板の上面に、スピンコート法等によって形成されるポリイミド樹脂等から成る薄膜の絶縁層と、銅やアルミニウム等の金属から成り、めっき法や蒸着法等の薄膜形成技術およびフォトリソグラフィー技術を採用することによって形成される配線導体層とを交互に多層に積層させた構造を有している。
【０００４】
しかしながら、スピンコート法によってポリイミド樹脂から成る絶縁層を形成した場合、所望の厚みに絶縁層を形成するには多数回に分けてポリイミド樹脂の前駆体を塗布する必要があり、さらにその後にポリイミド樹脂の前駆体をポリイミド化させるキュア工程が必要となるため、製造工程が長くなるという問題点があった。
【０００５】
そこで、ポリイミド樹脂等から成る複数の絶縁フィルム層を間にビスマレイミドトリアジン樹脂等から成る絶縁性接着剤層を介して積層して成る絶縁層を用いる多層配線基板が採用されてきている。
【０００６】
かかる多層配線基板における絶縁層の形成は、まず絶縁フィルムに絶縁性接着剤をドクターブレード法等を用いて塗布し乾燥させたものを準備し、この絶縁フィルム層を基板や下層の絶縁フィルム層の上面に間に絶縁性接着剤層が配されるように積み重ね、これを加熱プレス装置を用いて加熱加圧し接着することにより行なわれる。
【０００７】
また、上下に位置する配線導体層間の電気的接続は、レーザやドライエッチング等の手法により絶縁フィルム層および絶縁性接着剤層に貫通孔を形成し、その後、貫通孔の内壁に真空成膜法やめっき法により貫通導体を形成することにより行なわれている。
【０００８】
これら配線導体層および貫通導体は以下の（１）〜（５）の工程を含む製造方法で形成されている。
（１）絶縁フィルム層および絶縁性接着剤層にレーザやプラズマにより方形や円形に開口した貫通孔を形成し、その内部を過マンガン酸カリウム溶液等の粗化液で粗化する。
（２）この粗化した面にめっき触媒としてＰｄ等を付与し、その後、無電解めっきにより下地導体膜を形成する。
（３）次に、下地導体膜の上にフォトレジストを塗布するとともにこれに露光・現像を施すことによって、下地導体層のうち上層の主導体層を形成する部分に所定形状の窓部を形成する。
（４）次に、フォトレジストの窓部に露出させた下地導体層を電極として電解めっき皮膜を３〜10μｍの厚みに形成する。これによって上層の主導体層の部分に相当する露出した下地導体層上にめっき皮膜が形成され、その他の部分はフォトレジストに覆われているためにめっき皮膜が形成されず、上層の配線導体層および貫通導体に相当する部分にのみ主導体層が形成される。
（５）このようにして所定の厚さの主導体層を形成した後、フォトレジストを剥離除去し、次に、主導体層をエッチングレジストとして先に電解めっき用電極として使用した下地導体層の一部をエッチングすることによって、上層の配線導体層および貫通導体が形成される。
【０００９】
【発明が解決しようとする課題】
しかしながら、上記のような絶縁フィルム層を間に絶縁性接着剤層を介して加熱加圧し接着する多層配線基板においては、基板，貫通導体，絶縁フィルム層，絶縁性接着剤層のそれぞれの材質の違いにより熱膨張係数に差があるため、多層配線基板にチップ部品等を実装する際の加熱工程や温度サイクル試験等の耐環境試験の熱により部分的に応力が集中する様になる。例えば、絶縁フィルム層や絶縁性接着剤層と貫通導体との熱膨張差による応力は配線導体層の上面と貫通孔とが接する部分に集中することとなる。また、基板，絶縁性接着剤層，絶縁フィルム層の熱膨張差による応力はそれぞれの界面、とりわけ材質の大きく異なる基板と絶縁性接着剤層との界面で基板の外周部に近い部分により大きい応力が生じることとなる。そのため、これらの応力の集中により基板の外周部に近い基板直上にある配線導体層の上面と貫通孔とが接する部分を基点として、配線導体層と貫通導体との界面において、その界面の接着力が低い場合には界面方向にクラックが生じ、配線導体層と貫通導体との剥離が発生するという問題点があった。
【００１０】
本発明は上記従来技術における問題点に鑑みてなされたものであり、その目的は、チップ部品等を実装する際の加熱工程や温度サイクル試験等の耐環境試験において発生する配線導体層と貫通導体との剥離を抑制した、電気的接続信頼性に優れた多層配線基板を提供することにある。
【００１１】
【課題を解決するための手段】
本発明の多層配線基板は、基板上に有機樹脂から成る複数の絶縁フィルム層と配線導体層とを前記絶縁フィルム層間に絶縁性接着剤層を介して多層に積層接着するとともに、上下に位置する前記配線導体層同士をその間の前記絶縁フィルム層および前記絶縁性接着剤層に設けた貫通孔に貫通導体を配して電気的に接続して成る多層配線基板であって、前記基板側の最下層に配された前記貫通導体は、横断面の形状が長穴形状であるとともにその長径方向が前記基板の中心部に向かっていることを特徴とするものである。
【００１２】
また、本発明の多層配線基板は、上記構成において、前記長穴形状の長径を前記基板の外周部にある前記貫通導体よりも前記基板の中心部にある前記貫通導体において小さくしてあることを特徴とするものである。
【００１３】
また、本発明の多層配線基板は、上記各構成において、前記最下層の他の層に配された前記貫通導体も横断面の形状が長穴形状であるとともにその長径方向が前記基板の中心部に向かっており、前記長穴形状の長径を前記最下層に配された前記貫通導体よりも前記他の層に配された前記貫通導体において小さくしてあることを特徴とするものである。
【００１４】
また、本発明の多層配線基板は、上記構成において、前記最下層から最上層に向かって、前記長穴形状の長径を順次小さくしてあることを特徴とするものである。
【００１５】
本発明の多層配線基板によれば、基板側の最下層に配された貫通孔の横断面の形状が長穴形状であるとともに、その長径方向が基板の中心部に向かっているため、チップ部品等を実装する際の加熱工程や温度サイクル試験等の耐環境試験において、基板側の最下層に配された配線導体層の上面と貫通導体の底面との界面に応力が生じた場合にも応力のかかる方向に対して長い接触面積があるため、配線導体層の上面と貫通導体の底面との界面における接着強度を上げることができ、配線導体層と貫通導体との剥離がなくなる。
【００１６】
これにより、上下に位置する配線導体層間の導通不良の発生がなくなり、電気的接続信頼性の優れた多層配線基板となる。
【００１７】
さらに、本発明の多層配線基板によれば、長穴形状の長径を基板の外周部にある貫通導体よりも基板の中心部にある貫通導体において小さくしたときには、チップ部品等を実装する際の加熱工程や温度サイクル試験等の耐環境試験において、基板の中心部に比べて外周部に応力が強くかかるため、その傾向に沿って貫通導体の長径を調節しておくことができ、基板側の最下層に配された配線導体層の上面と貫通導体の底面との界面に応力が生じた場合にも応力に対して十分な接触面積があるので、配線導体層の上面と貫通導体の底面との界面における接着強度を上げることができ、配線導体層と貫通導体との剥離がなくなるとともに、基板の中心部における貫通導体の占有面積を小さくすることができ高密度な配線導体層を形成することができるようになる。
【００１８】
さらに、本発明の多層配線基板によれば、最下層の他の層に配された貫通導体も横断面の形状が長穴形状であるとともにその長径方向が基板の中心部に向かっており、長穴形状の長径を最下層に配された貫通導体よりも他の層に配された貫通導体において小さくしたときには、チップ部品等を実装する際の加熱工程や温度サイクル試験等の耐環境試験において、基板側の最下層に比べてそれより上層部にある他の層にかかる応力は弱くなるため、その応力に合わせて貫通導体の長径を調節しておくことができ、配線導体層の上面と貫通導体の底面との界面に応力が生じた場合にも応力に対して十分な接触面積があるので、配線導体層の上面と貫通導体の底面との界面における接着強度を上げることができ、配線導体層と貫通導体との剥離を有効になくすことができるとともに、基板側の最下層以外の層においては貫通導体の占有面積を小さくすることができ、それにより高密度な配線導体層を形成することができるようになる。
【００１９】
さらに、本発明の多層配線基板によれば、基板側の最下層から最上層に向かって、長穴形状の長径を順次小さくしたときには、チップ部品等を実装する際の加熱工程や温度サイクル試験等の耐環境試験においても、基板側の最下層から最上層に向かって弱くなる応力を各層毎に応力に見合った接触面積で受けることができるため、配線導体層の上面と貫通導体の底面との界面における接着強度を上げることができ、配線導体層と貫通導体との剥離を有効になくすことができるとともに、各層で貫通導体の占有面積を小さくすることができ、各層においてより有効に高密度な配線導体層を形成することができるようになる。
【００２０】
これらのことにより、上下に位置する配線導体層間の導通不良の発生がなくなるとともに高密度な配線導体層を形成することができるようになるため、電気的接続信頼性の優れた高密度な多層配線基板となる。
【００２１】
【発明の実施の形態】
以下、図面に基づいて本発明を詳細に説明する。
【００２２】
図１は本発明の多層配線基板の実施の形態の一例を示す断面図であり、図２は本発明の多層配線基板の実施の形態の一例における基板側の最下層の絶縁フィルム層を示す上面図である。これらの図において、１は基板、２は多層配線部、３は配線導体層、４は絶縁フィルム層、５は絶縁性接着剤層、６は貫通孔、７は貫通導体である。
【００２３】
基板１は、その上面に複数の絶縁フィルム層４を間に絶縁性接着剤層５を介して積層した絶縁層と配線導体層３とを多層に積層した多層配線部２が配設されており、この多層配線部２を支持する支持部材として機能する。
【００２４】
基板１は、酸化アルミニウム質焼結体，ムライト質焼結体等の酸化物系セラミックス、あるいは表面に酸化物膜を有する窒化アルミニウム質焼結体，炭化珪素質焼結体，窒化珪素質焼結体等の非酸化物系セラミックス、さらにはガラス繊維から成る基材にエポキシ樹脂を含浸させたガラスエポキシ樹脂やガラス繊維から成る基材にビスマレイミドトリアジン樹脂を含浸させたもの等の電気絶縁材料で形成されている。
【００２５】
例えば、酸化アルミニウム質焼結体で形成されている場合には、アルミナ，シリカ，カルシア，マグネシア等の原料粉末に適当な有機溶剤，溶媒を添加混合して泥漿状となすとともにこれを従来周知のドクターブレード法やカレンダーロール法を採用することによってセラミックグリーンシート（セラミック生シート）を形成し、しかる後、このセラミックグリーンシートに適当な打ち抜き加工を施し、所定形状となすとともに高温（約1600℃）で焼成することによって、あるいはアルミナ等の原料粉末に適当な有機溶剤，溶媒を添加混合して原料粉末を調整するとともにこの原料粉末をプレス成形機によって所定形状に成形し、最後にこの成形体を高温（約1600℃）で焼成することによって製作される。また、ガラスエポキシ樹脂から成る場合は、例えばガラス繊維から成る基材にエポキシ樹脂の前駆体を含浸させ、このエポキシ樹脂前駆体を所定の温度で熱硬化させることによって製作される。
【００２６】
また、基板１には、その上面に複数の絶縁フィルム層４を間に絶縁性接着剤層５を介して積層した絶縁層と配線導体層３とを多層に積層した多層配線部２が配設されている。この多層配線部２を構成する絶縁フィルム層４は上下に位置する配線導体層３を電気的に絶縁し、配線導体層３は電気信号を伝達するための伝達路として機能する。
【００２７】
多層配線部２の絶縁層は絶縁フィルム層４と絶縁性接着剤層５とから構成され、絶縁フィルム層４はポリイミド樹脂，ポリフェニレンサルファイド樹脂，全芳香族ポリエステル樹脂，フッ素樹脂等から成る。また、絶縁性接着剤層５はポリアミドイミド樹脂，ポリイミドシロキサン樹脂，ビスマレイミドトリアジン樹脂，エポキシ樹脂等から成る。
【００２８】
絶縁層は、まず12.5〜50μｍ程度の絶縁フィルムに絶縁性接着剤をドクターブレード法等を用いて乾燥厚みで５〜20μｍ程度に塗布し乾燥させたものを準備し、この絶縁フィルムを基板１や下層の絶縁層の上面に間に絶縁性接着剤が配されるように積み重ね、これを加熱プレス装置を用いて加熱加圧し接着することによって形成される。
【００２９】
中でも、貫通導体７を銅または銅合金で形成し、絶縁フィルム層４をポリイミド樹脂とし、絶縁性接着剤層５をポリイミドシロキサン樹脂あるいはシロキサン変性ポリアミドイミド樹脂とする組合せにおいては、ポリイミドシロキサン樹脂あるいはシロキサン変性ポリアミドイミド樹脂が絶縁フィルム層４との接着性も良好で、かつ耐熱性が高く、また熱膨張係数が銅と比較的近いため、貫通導体７と絶縁層との熱膨張差も小さくなる。このような構成にしておくと熱負荷により発生する応力も小さいため貫通導体７の長径を小さくすることができる。すなわち、貫通導体７の占有面積を小さくすることができるため高密度な配線導体層３を形成することができ本発明に好適となる。
【００３０】
絶縁層には所定位置に絶縁フィルム層４および絶縁性接着剤層５を貫通する貫通孔６が形成されており、この貫通孔６内には貫通導体７が被着形成されることにより絶縁フィルム層４を挟んで上下に位置する配線導体層３の各々を電気的に接続する接続路が形成される。
【００３１】
貫通孔６は、例えばレーザを使い絶縁フィルム層４および絶縁性接着剤層５の一部を除去することにより形成される。特に、貫通孔６の開口径が小さな場合は、貫通孔６の内壁面の角度をコントロールすることが容易で貫通孔６の内壁面が滑らかに加工される紫外線レーザで形成することが望ましい。
【００３２】
このとき、基板１側の最下層に配される貫通導体７が形成される貫通孔６は長穴形状にしておくのがよい。長穴形状としては略楕円形状や略四角形状でその角が丸まった形状のものを用い、その長径（楕円形状の場合は径の長い方、四角形状でその角が丸まったものの場合はその辺の長い方）方向を基板１の中心部に向けて配列しておくと、基板１側の最下層に配された配線導体層３の上面と貫通導体７の底面との界面に応力が生じた場合にも応力のかかる方向に対して長い接触面積があるため、配線導体層３の上面と貫通導体の底面との界面における接着強度を上げることができ、その界面における剥離をなくすことができるようになる。
【００３３】
また、基板１の外周部にある長穴形状の貫通導体７の長径よりも基板１の中心部にある長穴形状の貫通導体７において長径を小さくしておくのがよい。これにより、基板１の中心部に比べ外周部に応力が強くかかるのに対して、その傾向に沿って貫通導体７の長径を調節しておくことができ、基板１の中心部における貫通導体７の占有面積を小さくすることができるようになる。
【００３４】
さらに、基板１側の最下層の他の層に配された貫通導体７も横断面の形状が長穴形状であるとともにその長径方向が基板１の中心部に向かっているものとし、基板１側の最下層にある長穴形状の貫通導体７の長径よりも他の層にある長穴形状の貫通導体７においてその長径を小さくしておくのがよい。基板１側の最下層に比べ、それより上層部にある他の層にかかる応力は弱くなるため、その応力に合わせて貫通導体７の長径を調節しておくことができ、基板１側の最下層以外の他の層においては貫通導体７の占有面積を小さくすることができるようになる。
【００３５】
さらに、基板１側の最下層から最上層に向かって、長穴形状の貫通導体７の長径を順次小さくしておくのがよい。これにより、基板１側の最下層から最上層に向かって弱くなる応力を各層毎に応力に見合った接触面積で受けることができ、各層で貫通導体７の占有面積を小さくすることができるようになる。
【００３６】
各絶縁フィルム層４の上面に配設される配線導体層３および貫通孔６内に配設される貫通導体７は、銅，金，アルミニウム，ニッケル，クロム，モリブデン，チタンおよびそれらの合金等の金属材料をスパッタリング法，蒸着法，めっき法等の薄膜形成技術を採用することによって形成することができる。
【００３７】
貫通導体７は配線導体層３と別々に形成してもよいが、これらは同時に形成した方が工程数を少なくできるとともに両者の電気的な接続信頼性の点でも良好である。また、配線導体層３と貫通導体７とを一体形成する場合には、それぞれに所望の厚みのめっき膜を調整して形成することができるように、主として電解めっき法を用いて形成しておくのがよい。
【００３８】
配線導体層３および貫通導体７の形成方法は、例えば、まず広面積に銅層を主体としこの銅層の少なくとも一方の主面に拡散防止層（バリア層）としてのクロム，モリブデン，チタン等を被着させて下地導体層を形成する。次に、この上に所望のパターンにフォトレジストを形成し、このフォトレジストをマスクにして主導体層部分をメッキにて所望の厚みまで形成する。その後、フォトレジストを剥離し、下地導体層をエッチングにて除去することにより所望のパターンに加工することができる。
【００３９】
なお、絶縁フィルム層４の最上層の主導体層には、チップ部品の実装性および耐環境性の点から、主導体層が銅層から成る場合には表面の酸化防止あるいは酸化による抵抗値の増大を防止するため、その上にニッケル層や金層を形成するとよい。
【００４０】
かくして、本発明の多層配線基板によれば、基板１の上面に被着させた多層配線部２の上に半導体素子や容量素子，抵抗器等の電子部品を搭載実装し、電子部品の各電極を配線導体層３に電気的に接続することによって半導体装置や混成集積回路装置等となる。
【００４１】
なお、本発明は上記の例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能である。例えば、上述の例においては基板１の上面にのみ絶縁層と配線導体層３とから成る多層配線部２を設けたが、多層配線部２を基板１の下面側のみに設けても、上下の両面に設けてもよい。
【００４２】
【発明の効果】
以上のように、本発明の多層配線基板によれば、基板側の最下層に配された貫通孔の横断面の形状が長穴形状であるとともに、その長径方向が基板の中心部に向かっているため、チップ部品等を実装する際の加熱工程や温度サイクル試験等の耐環境試験において、基板側の最下層に配された配線導体層の上面と貫通導体の底面との界面に応力が生じた場合にも応力のかかる方向に対して長い接触面積があるため、配線導体層の上面と貫通導体の底面との界面における接着強度を上げることができ、配線導体層と貫通導体との剥離がなくなる。
【００４３】
これにより、上下に位置する配線導体層間の導通不良の発生がなくなり、電気的接続信頼性の優れた多層配線基板となる。
【００４４】
さらに、本発明の多層配線基板によれば、長穴形状の長径を基板の外周部にある貫通導体よりも基板の中心部にある貫通導体において小さくしたときには、チップ部品等を実装する際の加熱工程や温度サイクル試験等の耐環境試験において、基板の中心部に比べて外周部に応力が強くかかるため、その傾向に沿って貫通導体の長径を調節しておくことができ、基板側の最下層に配された配線導体層の上面と貫通導体の底面との界面に応力が生じた場合にも応力に対して十分な接触面積があるので、配線導体層の上面と貫通導体の底面との界面における接着強度を上げることができ、配線導体層と貫通導体との剥離がなくなるとともに、基板の中心部における貫通導体の占有面積を小さくすることができ高密度な配線導体層を形成することができるようになる。
【００４５】
さらに、本発明の多層配線基板によれば、最下層の他の層に配された貫通導体も横断面の形状が長穴形状であるとともにその長径方向が基板の中心部に向かっており、長穴形状の長径を最下層に配された貫通導体よりも他の層に配された貫通導体において小さくしたときには、チップ部品等を実装する際の加熱工程や温度サイクル試験等の耐環境試験において、基板側の最下層に比べてそれより上層部にある他の層にかかる応力は弱くなるため、その応力に合わせて貫通導体の長径を調節しておくことができ、配線導体層の上面と貫通導体の底面との界面に応力が生じた場合にも応力に対して十分な接触面積があるので、配線導体層の上面と貫通導体の底面との界面における接着強度を上げることができ、配線導体層と貫通導体との剥離を有効になくすことができるとともに、基板側の最下層以外の層においては貫通導体の占有面積を小さくすることができ、それにより高密度な配線導体層を形成することができるようになる。
【００４６】
さらに、本発明の多層配線基板によれば、基板側の最下層から最上層に向かって、長穴形状の長径を順次小さくしたときには、チップ部品等を実装する際の加熱工程や温度サイクル試験等の耐環境試験においても、基板側の最下層から最上層に向かって弱くなる応力を各層毎に応力に見合った接触面積で受けることができるため、配線導体層の上面と貫通導体の底面との界面における接着強度を上げることができ、配線導体層と貫通導体との剥離を有効になくすことができるとともに、各層で貫通導体の占有面積を小さくすることができ、各層においてより有効に高密度な配線導体層を形成することができるようになる。
【００４７】
これらのことにより、上下に位置する配線導体層間の導通不良の発生がなくなるとともに高密度な配線導体層を形成することができるようになるため、電気的接続信頼性の優れた高密度な多層配線基板となる。
【図面の簡単な説明】
【図１】本発明の多層配線基板の実施の形態の一例を示す断面図である。
【図２】本発明の多層配線基板の実施の形態の一例における基板側の最下層の絶縁フィルム層を示す上面図である。
【符号の説明】
１・・・・基板
２・・・・多層配線部
３・・・・配線導体層
４・・・・絶縁フィルム層
５・・・・絶縁性接着剤層
６・・・・貫通孔
７・・・・貫通導体[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multilayer wiring board, and more particularly to a multilayer wiring board used for a hybrid integrated circuit device, a semiconductor element housing package for housing semiconductor elements, and the like.
[0002]
[Prior art]
Conventionally, a multilayer wiring board used for a hybrid integrated circuit device, a package for housing a semiconductor element, and the like includes a thin insulating layer and a wiring conductor layer on the substrate for the purpose of forming wiring conductors at a high density. A multilayer wiring board in which a multilayer wiring portion is formed has been adopted.
[0003]
Such a multilayer wiring board is composed of a thin film insulating layer made of polyimide resin or the like formed by a spin coating method or the like on a top surface of a substrate made of an aluminum oxide sintered body or the like, and a metal such as copper or aluminum, and a plating method. And a wiring conductor layer formed by adopting a thin film forming technique such as vapor deposition or a photolithography technique, and having a multilayer structure alternately.
[0004]
However, when an insulating layer made of polyimide resin is formed by a spin coating method, it is necessary to apply a polyimide resin precursor in a number of times to form the insulating layer in a desired thickness. This requires a curing process for polyimidating the precursor of the above, and thus the manufacturing process becomes long.
[0005]
Therefore, a multilayer wiring board using an insulating layer formed by laminating a plurality of insulating film layers made of polyimide resin or the like via an insulating adhesive layer made of bismaleimide triazine resin or the like has been adopted.
[0006]
In order to form an insulating layer in such a multilayer wiring board, first, an insulating film is prepared by applying an insulating adhesive using a doctor blade method and drying, and this insulating film layer is used as a substrate or a lower insulating film layer. It is carried out by stacking the insulating adhesive layers so as to be disposed between the upper surfaces and bonding them by applying heat and pressure using a hot press device.
[0007]
In addition, the electrical connection between the upper and lower wiring conductor layers is achieved by forming through holes in the insulating film layer and the insulating adhesive layer by a method such as laser or dry etching, and then forming a vacuum film on the inner walls of the through holes. Or by forming through conductors by plating.
[0008]
These wiring conductor layers and through conductors are formed by a manufacturing method including the following steps (1) to (5).
(1) A through-hole having a square or circular opening is formed in the insulating film layer and the insulating adhesive layer by laser or plasma, and the inside is roughened with a roughening solution such as a potassium permanganate solution.
(2) Pd or the like is applied as a plating catalyst to the roughened surface, and then a base conductor film is formed by electroless plating.
(3) Next, by applying a photoresist on the underlying conductor film and exposing / developing it, a window having a predetermined shape is formed in the portion of the underlying conductor layer where the upper main conductor layer is to be formed. To do.
(4) Next, an electrolytic plating film is formed to a thickness of 3 to 10 μm using the underlying conductor layer exposed at the window portion of the photoresist as an electrode. As a result, a plating film is formed on the exposed underlying conductor layer corresponding to the portion of the upper main conductor layer, and no plating film is formed because the other portions are covered with the photoresist, so that the upper wiring conductor layer The main conductor layer is formed only in the portion corresponding to the through conductor.
(5) After the main conductor layer having a predetermined thickness is formed in this way, the photoresist is peeled and removed, and then the main conductor layer is used as an etching resist for the underlying conductor layer previously used as an electrode for electrolytic plating. By etching a part, an upper wiring conductor layer and a through conductor are formed.
[0009]
[Problems to be solved by the invention]
However, in the multilayer wiring board in which the insulating film layer as described above is bonded by heating and pressing through the insulating adhesive layer, the materials of the substrate, the through conductor, the insulating film layer, and the insulating adhesive layer are different. Since there is a difference in thermal expansion coefficient due to the difference, the stress is partially concentrated by the heat of the environmental test such as the heating process and the temperature cycle test when mounting the chip parts on the multilayer wiring board. For example, the stress due to the difference in thermal expansion between the insulating film layer or the insulating adhesive layer and the through conductor is concentrated on the portion where the upper surface of the wiring conductor layer is in contact with the through hole. Also, the stress due to the difference in thermal expansion of the substrate, insulating adhesive layer, and insulating film layer is greater at each interface, especially at the interface between the substrate and the insulating adhesive layer, which are greatly different in material, near the outer periphery of the substrate. Will occur. Therefore, the adhesive strength of the interface at the interface between the wiring conductor layer and the through-conductor, starting from the portion where the upper surface of the wiring conductor layer just above the substrate near the outer periphery of the substrate and the through-hole contact due to the concentration of these stresses When the thickness is low, there is a problem that cracks are generated in the direction of the interface and peeling between the wiring conductor layer and the through conductor occurs.
[0010]
The present invention has been made in view of the above problems in the prior art, and its purpose is to provide a wiring conductor layer and a through conductor generated in an environmental resistance test such as a heating process or a temperature cycle test when mounting a chip component or the like. It is an object of the present invention to provide a multilayer wiring board that is excellent in electrical connection reliability and is prevented from peeling.
[0011]
[Means for Solving the Problems]
The multilayer wiring board of the present invention is formed by laminating and bonding a plurality of insulating film layers made of an organic resin and a wiring conductor layer on the substrate in a multilayer manner via an insulating adhesive layer between the insulating film layers, and positioned above and below. A multilayer wiring board in which the wiring conductor layers are electrically connected by arranging through conductors in through holes provided in the insulating film layer and the insulating adhesive layer between the wiring conductor layers. The through conductor disposed in the lower layer is characterized in that the cross-sectional shape is an elongated hole shape and the major axis direction is toward the center of the substrate.
[0012]
In the multilayer wiring board of the present invention, in the above configuration, the long diameter of the elongated hole shape is made smaller in the through conductor in the central portion of the substrate than in the through conductor in the outer peripheral portion of the substrate. It is a feature.
[0013]
In the multilayer wiring board according to the present invention, in each of the above-described configurations, the through conductors arranged in the other layers of the lowermost layer also have a cross-sectional shape of a long hole, and a major axis direction thereof is a central portion of the substrate. The long diameter of the long hole shape is smaller in the through conductor disposed in the other layer than in the through conductor disposed in the lowermost layer.
[0014]
The multilayer wiring board of the present invention is characterized in that, in the above configuration, the long diameter of the elongated hole shape is sequentially reduced from the lowermost layer to the uppermost layer.
[0015]
According to the multilayer wiring board of the present invention, the cross-sectional shape of the through hole arranged in the lowermost layer on the substrate side is a long hole shape, and the major axis direction thereof is directed toward the center of the substrate. In an environmental resistance test such as a heating process or temperature cycle test when mounting etc., stress also occurs when stress is generated at the interface between the upper surface of the wiring conductor layer arranged on the bottom layer on the board side and the bottom surface of the through conductor Since there is a long contact area in such a direction, the adhesive strength at the interface between the upper surface of the wiring conductor layer and the bottom surface of the through conductor can be increased, and the wiring conductor layer and the through conductor are not separated.
[0016]
This eliminates the occurrence of poor conduction between the upper and lower wiring conductor layers, resulting in a multilayer wiring board with excellent electrical connection reliability.
[0017]
Furthermore, according to the multilayer wiring board of the present invention, when the long diameter of the long hole shape is made smaller in the through conductor in the central portion of the substrate than in the through conductor in the outer peripheral portion of the substrate, the heating at the time of mounting the chip component etc. In environmental resistance tests such as process and temperature cycle tests, stress is more strongly applied to the outer periphery than the center of the substrate.Therefore, the long diameter of the through conductor can be adjusted in accordance with this tendency. Even when stress is generated at the interface between the upper surface of the wiring conductor layer disposed in the lower layer and the bottom surface of the through conductor, there is a sufficient contact area against the stress. The adhesive strength at the interface can be increased, the wiring conductor layer and the through conductor are not separated, and the area occupied by the through conductor at the center of the substrate can be reduced, thereby forming a high density wiring conductor layer. so It becomes so that.
[0018]
Furthermore, according to the multilayer wiring board of the present invention, the through conductors arranged in the other layers of the lowermost layer also have a cross-sectional shape of a long hole, and the long diameter direction is directed toward the center of the substrate. When the hole-shaped major axis is made smaller in the through conductor arranged in the other layer than the through conductor arranged in the lowermost layer, in an environmental resistance test such as a heating process or a temperature cycle test when mounting a chip component or the like, Since the stress applied to other layers in the upper layer is weaker than the lowest layer on the board side, the long diameter of the through conductor can be adjusted according to the stress, and the upper surface of the wiring conductor layer Even when stress is generated at the interface with the bottom surface of the conductor, there is a sufficient contact area with respect to the stress, so that the adhesive strength at the interface between the upper surface of the wiring conductor layer and the bottom surface of the through conductor can be increased. Peeling between layer and through conductor It is possible to eliminate, in the layers other than the lowermost layer on the substrate side can reduce the occupied area of the through conductors, made thereby be able to form a high-density wiring conductor layers.
[0019]
Furthermore, according to the multilayer wiring board of the present invention, when the long diameter of the long hole shape is sequentially reduced from the lowermost layer on the substrate side to the uppermost layer, a heating process and a temperature cycle test when mounting chip parts and the like are performed. Also in the environmental resistance test, since the stress that weakens from the bottom layer on the substrate side toward the top layer can be received in the contact area corresponding to the stress for each layer, the top surface of the wiring conductor layer and the bottom surface of the through conductor Adhesive strength at the interface can be increased, peeling between the wiring conductor layer and the penetrating conductor can be effectively eliminated, and the area occupied by the penetrating conductor can be reduced in each layer. A wiring conductor layer can be formed.
[0020]
As a result, the occurrence of poor conduction between the upper and lower wiring conductor layers can be eliminated and a high-density wiring conductor layer can be formed. Therefore, high-density multilayer wiring with excellent electrical connection reliability. It becomes a substrate.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the drawings.
[0022]
FIG. 1 is a cross-sectional view showing an example of an embodiment of a multilayer wiring board according to the present invention, and FIG. 2 is a top view showing a lowermost insulating film layer on the substrate side in an example of an embodiment of the multilayer wiring board according to the present invention. FIG. In these drawings, 1 is a substrate, 2 is a multilayer wiring portion, 3 is a wiring conductor layer, 4 is an insulating film layer, 5 is an insulating adhesive layer, 6 is a through hole, and 7 is a through conductor.
[0023]
The substrate 1 is provided with a multilayer wiring portion 2 in which an insulating layer in which a plurality of insulating film layers 4 are stacked with an insulating adhesive layer 5 interposed therebetween and a wiring conductor layer 3 are stacked in multiple layers. This functions as a support member for supporting the multilayer wiring portion 2.
[0024]
The substrate 1 is made of an oxide ceramic such as an aluminum oxide sintered body or a mullite sintered body, or an aluminum nitride sintered body having an oxide film on its surface, a silicon carbide sintered body, or a silicon nitride sintered body. Non-oxide ceramics such as body, and glass insulation resin impregnated with glass fiber base material or electrical insulation material such as glass fiber base material impregnated with bismaleimide triazine resin Is formed.
[0025]
For example, when it is formed of an aluminum oxide sintered body, an appropriate organic solvent or solvent is added to and mixed with raw material powders such as alumina, silica, calcia, and magnesia to form a slurry, and this is conventionally known. A ceramic green sheet (green ceramic sheet) is formed by adopting the doctor blade method or the calender roll method, and then the ceramic green sheet is appropriately punched into a predetermined shape and at a high temperature (about 1600 ° C). Or by adding a suitable organic solvent and solvent to the raw material powder such as alumina to adjust the raw material powder, and forming this raw material powder into a predetermined shape by a press molding machine. Manufactured by firing at high temperature (about 1600 ° C). Moreover, when it consists of glass epoxy resins, it manufactures, for example by impregnating the base material which consists of glass fiber with the precursor of an epoxy resin, and thermosetting this epoxy resin precursor at predetermined temperature.
[0026]
Further, the substrate 1 is provided with a multilayer wiring portion 2 in which an insulating layer in which a plurality of insulating film layers 4 are laminated with an insulating adhesive layer 5 interposed therebetween and a wiring conductor layer 3 are laminated in multiple layers on the upper surface thereof. Has been. The insulating film layer 4 constituting the multilayer wiring portion 2 electrically insulates the wiring conductor layer 3 positioned above and below, and the wiring conductor layer 3 functions as a transmission path for transmitting an electrical signal.
[0027]
The insulating layer of the multilayer wiring part 2 is composed of an insulating film layer 4 and an insulating adhesive layer 5, and the insulating film layer 4 is made of polyimide resin, polyphenylene sulfide resin, wholly aromatic polyester resin, fluorine resin, or the like. The insulating adhesive layer 5 is made of polyamide-imide resin, polyimide siloxane resin, bismaleimide triazine resin, epoxy resin, or the like.
[0028]
First, an insulating layer is prepared by applying an insulating adhesive to an insulating film of about 12.5 to 50 μm using a doctor blade method to a dry thickness of about 5 to 20 μm and drying the insulating film. It is formed by stacking the insulating adhesive on the upper surface of the lower insulating layer so that the insulating adhesive is disposed between them, and heating and pressurizing them using a heating press device.
[0029]
In particular, in a combination in which the through conductor 7 is formed of copper or a copper alloy, the insulating film layer 4 is a polyimide resin, and the insulating adhesive layer 5 is a polyimide siloxane resin or a siloxane-modified polyamideimide resin, a polyimide siloxane resin or siloxane is used. Since the modified polyamideimide resin has good adhesion to the insulating film layer 4 and has high heat resistance, and the thermal expansion coefficient is relatively close to copper, the thermal expansion difference between the through conductor 7 and the insulating layer is also reduced. With such a configuration, since the stress generated by the thermal load is small, the long diameter of the through conductor 7 can be reduced. That is, since the occupation area of the through conductor 7 can be reduced, the high-density wiring conductor layer 3 can be formed, which is suitable for the present invention.
[0030]
A through hole 6 penetrating the insulating film layer 4 and the insulating adhesive layer 5 is formed at a predetermined position in the insulating layer, and a through conductor 7 is deposited in the through hole 6 to form an insulating film. A connection path that electrically connects each of the wiring conductor layers 3 positioned above and below the layer 4 is formed.
[0031]
The through-hole 6 is formed by removing a part of the insulating film layer 4 and the insulating adhesive layer 5 using a laser, for example. In particular, when the opening diameter of the through hole 6 is small, it is desirable to control the angle of the inner wall surface of the through hole 6 and to form an ultraviolet laser that smoothly processes the inner wall surface of the through hole 6.
[0032]
At this time, the through hole 6 in which the through conductor 7 disposed in the lowermost layer on the substrate 1 side is formed is preferably a long hole shape. As the long hole shape, use an approximately oval shape or an approximately quadrilateral shape with rounded corners, and its long diameter (the longer diameter for an oval shape, the side for a square shape with rounded corners) If the direction is oriented toward the center of the substrate 1, stress is generated at the interface between the upper surface of the wiring conductor layer 3 and the bottom surface of the through conductor 7 disposed on the lowermost layer on the substrate 1 side. In some cases, since there is a long contact area with respect to the direction in which the stress is applied, the adhesive strength at the interface between the upper surface of the wiring conductor layer 3 and the bottom surface of the through conductor can be increased, and peeling at the interface can be eliminated. become.
[0033]
Further, it is preferable that the long diameter of the long hole-shaped through conductor 7 in the central portion of the substrate 1 is made smaller than the long diameter of the long hole-shaped through conductor 7 in the outer peripheral portion of the substrate 1. As a result, stress is more strongly applied to the outer peripheral portion than the central portion of the substrate 1, whereas the long diameter of the through conductor 7 can be adjusted in accordance with this tendency, and the through conductor 7 in the central portion of the substrate 1 can be adjusted. The area occupied by can be reduced.
[0034]
Further, it is assumed that the through conductors 7 arranged in the other layers on the lowermost layer on the substrate 1 side also have a cross-sectional shape of a long hole and the long diameter direction is directed toward the center of the substrate 1. It is preferable to make the long diameter of the long hole-shaped through conductor 7 in another layer smaller than the long diameter of the long hole-shaped through conductor 7 in the lowermost layer. Compared with the lowermost layer on the substrate 1 side, the stress applied to the other layers in the upper layer is weaker. Therefore, the long diameter of the through conductor 7 can be adjusted in accordance with the stress, and the lowermost layer on the substrate 1 side can be adjusted. In other layers other than the lower layer, the occupation area of the through conductor 7 can be reduced.
[0035]
Furthermore, it is preferable that the long diameter of the through-hole-shaped through conductor 7 is made smaller in order from the lowermost layer on the substrate 1 side to the uppermost layer. Thereby, the stress that weakens from the lowermost layer on the substrate 1 side toward the uppermost layer can be received with a contact area corresponding to the stress for each layer, and the occupied area of the through conductor 7 can be reduced in each layer. Become.
[0036]
The wiring conductor layer 3 disposed on the upper surface of each insulating film layer 4 and the through conductor 7 disposed in the through hole 6 are made of copper, gold, aluminum, nickel, chromium, molybdenum, titanium, and alloys thereof. The metal material can be formed by adopting a thin film forming technique such as sputtering, vapor deposition or plating.
[0037]
The through conductors 7 may be formed separately from the wiring conductor layer 3, but forming them simultaneously can reduce the number of processes and is excellent in terms of electrical connection reliability between them. When the wiring conductor layer 3 and the through conductor 7 are integrally formed, the wiring conductor layer 3 and the through conductor 7 are formed mainly using an electrolytic plating method so that a plating film having a desired thickness can be adjusted for each. It is good.
[0038]
The method for forming the wiring conductor layer 3 and the through conductor 7 is, for example, a method in which a copper layer is mainly used in a large area and chromium, molybdenum, titanium or the like as a diffusion prevention layer (barrier layer) is formed on at least one main surface of the copper layer. A base conductor layer is formed by deposition. Next, a photoresist is formed in a desired pattern thereon, and the main conductor layer portion is formed to a desired thickness by plating using this photoresist as a mask. Thereafter, the photoresist can be peeled off and the underlying conductor layer can be removed by etching to be processed into a desired pattern.
[0039]
The uppermost main conductor layer of the insulating film layer 4 has a resistance value due to oxidation prevention or oxidation of the surface when the main conductor layer is made of a copper layer from the viewpoint of mountability and environmental resistance of chip parts. In order to prevent the increase, a nickel layer or a gold layer may be formed thereon.
[0040]
Thus, according to the multilayer wiring board of the present invention, electronic components such as semiconductor elements, capacitive elements, resistors, and the like are mounted and mounted on the multilayer wiring portion 2 deposited on the upper surface of the substrate 1. Is electrically connected to the wiring conductor layer 3 to obtain a semiconductor device, a hybrid integrated circuit device, or the like.
[0041]
It should be noted that the present invention is not limited to the above example, and various modifications can be made without departing from the gist of the present invention. For example, in the above-described example, the multilayer wiring portion 2 composed of the insulating layer and the wiring conductor layer 3 is provided only on the upper surface of the substrate 1, but even if the multilayer wiring portion 2 is provided only on the lower surface side of the substrate 1, It may be provided on both sides.
[0042]
【The invention's effect】
As described above, according to the multilayer wiring board of the present invention, the shape of the cross section of the through hole arranged in the lowermost layer on the substrate side is an elongated hole shape, and the major axis direction is directed toward the center of the substrate. Therefore, stress is generated at the interface between the upper surface of the wiring conductor layer disposed on the bottom layer on the substrate side and the bottom surface of the through conductor in environmental resistance tests such as the heating process and temperature cycle test when mounting chip parts, etc. In this case, since the contact area is long with respect to the direction in which the stress is applied, the adhesive strength at the interface between the upper surface of the wiring conductor layer and the bottom surface of the through conductor can be increased, and the separation between the wiring conductor layer and the through conductor can be prevented. Disappear.
[0043]
This eliminates the occurrence of poor conduction between the upper and lower wiring conductor layers, resulting in a multilayer wiring board with excellent electrical connection reliability.
[0044]
Furthermore, according to the multilayer wiring board of the present invention, when the long diameter of the long hole shape is made smaller in the through conductor in the central portion of the substrate than in the through conductor in the outer peripheral portion of the substrate, the heating at the time of mounting the chip component etc. In environmental resistance tests such as process and temperature cycle tests, stress is more strongly applied to the outer periphery than the center of the substrate.Therefore, the long diameter of the through conductor can be adjusted in accordance with this tendency. Even when stress is generated at the interface between the upper surface of the wiring conductor layer disposed in the lower layer and the bottom surface of the through conductor, there is a sufficient contact area against the stress. The adhesive strength at the interface can be increased, the wiring conductor layer and the through conductor are not separated, and the area occupied by the through conductor at the center of the substrate can be reduced, thereby forming a high density wiring conductor layer. so It becomes so that.
[0045]
Furthermore, according to the multilayer wiring board of the present invention, the through conductors arranged in the other layers of the lowermost layer also have a cross-sectional shape of a long hole, and the long diameter direction is directed toward the center of the substrate. When the hole-shaped major axis is made smaller in the through conductor arranged in the other layer than the through conductor arranged in the lowermost layer, in an environmental resistance test such as a heating process or a temperature cycle test when mounting a chip component or the like, Since the stress applied to other layers in the upper layer is weaker than the lowest layer on the board side, the long diameter of the through conductor can be adjusted according to the stress, and the upper surface of the wiring conductor layer Even when stress is generated at the interface with the bottom surface of the conductor, there is a sufficient contact area with respect to the stress, so that the adhesive strength at the interface between the upper surface of the wiring conductor layer and the bottom surface of the through conductor can be increased. Peeling between layer and through conductor It is possible to eliminate, in the layers other than the lowermost layer on the substrate side can reduce the occupied area of the through conductors, made thereby be able to form a high-density wiring conductor layers.
[0046]
Furthermore, according to the multilayer wiring board of the present invention, when the long diameter of the long hole shape is sequentially reduced from the lowermost layer on the substrate side to the uppermost layer, a heating process and a temperature cycle test when mounting chip parts and the like are performed. Also in the environmental resistance test, since the stress that weakens from the bottom layer on the substrate side toward the top layer can be received in the contact area corresponding to the stress for each layer, the top surface of the wiring conductor layer and the bottom surface of the through conductor Adhesive strength at the interface can be increased, peeling between the wiring conductor layer and the penetrating conductor can be effectively eliminated, and the area occupied by the penetrating conductor can be reduced in each layer. A wiring conductor layer can be formed.
[0047]
As a result, the occurrence of poor conduction between the upper and lower wiring conductor layers can be eliminated and a high-density wiring conductor layer can be formed. Therefore, high-density multilayer wiring with excellent electrical connection reliability. It becomes a substrate.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an example of an embodiment of a multilayer wiring board according to the present invention.
FIG. 2 is a top view showing a lowermost insulating film layer on the substrate side in an example of an embodiment of a multilayer wiring board of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ...... Board | substrate 2 ... Multi-layer wiring part 3 ... Wiring conductor layer 4 ... Insulating film layer 5 ... Insulating adhesive layer 6 ... Through-hole 7 ... ..Penetration conductor

Claims

A plurality of insulating film layers made of an organic resin and a wiring conductor layer on a substrate are laminated and bonded between the insulating film layers via an insulating adhesive layer, and the wiring conductor layers positioned above and below are sandwiched therebetween. A multilayer wiring board in which through conductors are arranged and electrically connected to through holes provided in the insulating film layer and the insulating adhesive layer, and the through conductors are arranged in the lowermost layer on the board side Is a multilayer wiring board characterized in that the cross-sectional shape is an elongated hole shape and the major axis direction is toward the center of the substrate.

The multilayer wiring board according to claim 1, wherein a long diameter of the elongated hole shape is made smaller in the through conductor in the center of the substrate than in the through conductor in the outer peripheral portion of the substrate.

The through conductors arranged in the other layers of the lowermost layer also have a cross-sectional shape of a long hole and a long diameter direction toward the center of the substrate, and the long diameter of the long hole shape is the bottom layer. 3. The multilayer wiring board according to claim 1, wherein the through conductor disposed in the other layer is made smaller than the through conductor disposed in the first layer.

4. The multilayer wiring board according to claim 3, wherein a major axis of the elongated hole shape is sequentially reduced from the lowermost layer toward the uppermost layer.