JP2005268259A - Multilayer wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent exfoliation caused by a difference between linear expansion coefficients of a wiring conductor and an insulating layer and raise the flatness of the surface of a multilayer wiring board, in the mutilayer wiring board obtained by laminating an insulating layer comprising organic resin and a wiring conductor into a multilayer. <P>SOLUTION: The multilayer wiring board is obtained by laminating the insulating layer 2 comprising resin and the wiring conductor 3 in plural layers. The wiring conductor 3 is partly embedded in the insulating layer 2 at an external peripheral part of the insulating layer 2 as viewed in a plan vision. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a multilayer wiring board, and more specifically, a package for storing an electronic component such as a package for housing a semiconductor element for housing a semiconductor integrated circuit element, or a probe card for performing an electrical inspection of a semiconductor integrated circuit or the like. The present invention relates to a multilayer wiring board used for, for example.

  2. Description of the Related Art In recent years, in semiconductor integrated circuits, the number of terminals formed on a semiconductor substrate has increased and the pitch of terminals has been reduced due to higher integration of semiconductor elements and an increase in the number of processing signals. As a result, the pitch of the connection terminals of the package for housing the semiconductor element that houses the semiconductor integrated circuit element and the probe of the probe card that performs electrical inspection of the semiconductor integrated circuit is also required.

  In response to this demand for narrow pitches, in the package for housing semiconductor devices, the mounting form of the semiconductor devices is changed from wire bonding connection to flip chip connection, and the probe card is a cantilever type, and needle-like probes are finely latticed. It has changed to something arranged in a shape.

  In addition, the structure of the multilayer wiring board used in the semiconductor element storage package and the probe card is formed by forming a wiring conductor layer obtained by patterning a copper foil on an insulating layer obtained by impregnating and curing an organic resin on a substrate made of glass fiber. Multi-layer consisting of a thin insulating layer and a wiring conductor layer on the top surface of the substrate, which is excellent in narrowing the pitch of the wiring conductor layer and can be arranged in a fine lattice pattern. It is changing to a build-up type multilayer wiring board in which a wiring part is formed.

Such a build-up type multilayer wiring board is made of an epoxy resin, a polyimide resin, or the like on the upper surface of the substrate, and is formed by applying a resin precursor by a curtain coating method, a spin coating method, or the like and then heat-curing the insulating layer. And a structure in which a wiring conductor layer made of a metal such as copper or aluminum is alternately laminated in multiple layers by adopting a thin film formation technique such as a plating method or a vapor deposition method and a photolithography technique. It has become.
JP-A-11-163520 Japanese Unexamined Patent Publication No. 11-38044

  However, in a multilayer wiring board having a multilayer wiring portion composed of an insulating layer and a wiring conductor layer as described above, stress due to a difference in linear expansion coefficient between the insulating layer and the wiring conductor layer is likely to occur. There is a problem that the stress is large at the portion, and the wiring conductor layer is easily peeled off from the insulating layer.

  In addition, since the thickness of the insulating layer made of organic resin follows the unevenness of the surface on which the precursor of the organic resin is applied almost uniformly, the wiring conductor layer formed on the insulating layer is formed on the insulating layer. A step is likely to occur on the surface of the insulating layer. Further, when the insulating layer is multilayered, the surface of the insulating layer formed on the uppermost surface of the multilayer wiring board may have a complicated uneven shape reflecting the unevenness in each layer. Furthermore, in order to reduce the conductor resistance value, the thickness of the conductor layer tends to be increased, and the upper surface of the multilayer wiring board may have a more complicated uneven shape.

  When a semiconductor substrate is mounted on the top surface of a wiring conductor layer formed on the top surface of a multilayer wiring board having such a concavo-convex shape, the surface roughness of the insulating layer formed on the top surface of the multilayer wiring board is absorbed. For example, the upper surface of the solder for connecting to the semiconductor substrate formed on the wiring conductor layer must be located on the same plane parallel to the surface of the semiconductor substrate, which complicates the process. Since the solder height more than necessary is necessary for the adjustment, there is a problem that the narrow pitch of the wiring conductor layer on the uppermost surface of the multilayer wiring board is hindered as a result.

  Also, when the probe is brought into contact or connected like a probe card, the height variation of the probe tip increases due to the height variation of the upper surface of the wiring conductor layer, and the contact pressure of the probe with respect to the terminal of the semiconductor substrate is increased. There was a problem that variations occurred and the connection resistance was likely to fluctuate.

  Further, if there is a variation in the height of the upper surface of the wiring conductor layer, there is a problem that the pressure is concentrated on a specific probe due to the variation in the contact pressure of the probe, which tends to shorten the life of the probe.

  The present invention has been made in view of the above-described problems in the prior art, and the object thereof is to provide a narrow pitch of the wiring conductor layer in which the insulating layer formed on the uppermost surface of the multilayer wiring board has a high flatness. An object of the present invention is to provide a multilayer wiring board that can cope with the manufacturing process.

  The multilayer wiring board of the present invention is a multilayer wiring board in which a plurality of insulating layers made of resin and wiring conductors are alternately stacked, and the wiring conductor is formed on the insulating layer at an outer peripheral portion of the insulating layer in a plan view. It is characterized in that a part is embedded in.

  In the multilayer wiring board of the present invention, preferably, the wiring conductor is formed between the insulating layers and embedded in the insulating layers on both the upper side and the lower side of the wiring conductor. It is what.

  According to the multilayer wiring board of the present invention, since the wiring conductor is partially embedded in the insulating layer at the outer peripheral portion of the insulating layer in plan view, the wiring conductor can be firmly fixed to the insulating layer. In particular, it is possible to effectively prevent the wiring conductor from being separated from the insulating layer at the outer peripheral portion where stress due to the difference in linear expansion coefficient between the insulating layer and the wiring conductor is easily applied.

  In addition, the amount of protrusion of the wiring conductor protruding from the insulating layer can be reduced as compared with the conventional case where the wiring conductor is disposed on the upper surface of the insulating layer, and the flatness of the surface of the multilayer wiring board can be increased. it can. Furthermore, even if the thickness of the wiring conductor is made thicker than before, the influence of the protrusion of the wiring conductor on the flatness of the insulating layer formed on the uppermost surface of the multilayer wiring board can be suppressed, and the electrical characteristics can be improved. it can.

  In the multilayer wiring board of the present invention, preferably, the wiring conductor is formed between the insulating layers and embedded in both the upper and lower insulating layers of the wiring conductor, thereby further increasing the amount of protrusion of the wiring conductor. It is possible to reduce the level, and the flatness of the surface of the multilayer wiring board can be further increased, and the wiring conductor can be more firmly fixed to the insulating layer.

  In addition, by embedding in the insulating layer, the thickness of the wiring conductor can be increased while maintaining the flatness of the multilayer wiring board. However, when embedded only in the upper or lower insulating layer, the thickness of the wiring conductor is increased. Therefore, in order to ensure insulation, it is necessary to increase the thickness of the insulating layer accordingly, whereas the thickness of each insulating layer is reduced by embedding the wiring conductor in both the upper and lower sides. Since the insulation can be maintained, the thickness of the wiring conductor can be increased without increasing the thickness of the multilayer wiring board.

  As a result, the wiring conductor formed on the flat top surface of the multilayer wiring board formed by laminating a plurality of insulating layers and wiring conductors in multiple layers can be easily arranged in parallel with the connection portion of the semiconductor substrate. Therefore, it is not necessary to adjust the height of the solder for connecting the semiconductor substrate. As a result, the multilayer wiring board can cope with the narrowing of the pitch of the wiring conductor in which the flatness of the insulating layer formed on the uppermost surface of the multilayer wiring board is high.

  When the multilayer wiring board of the present invention is used as a probe card, the wiring conductor and the probe formed on the uppermost surface of the multilayer wiring board formed by laminating a plurality of insulating layers and wiring conductors in multiple layers. As a result, the load applied to the probe during the inspection of the semiconductor integrated circuit is not concentrated on a part of the upper surface of the wiring conductor, and the life of the multilayer wiring board due to the wear of the wiring conductor is shortened. Can be eliminated. Thereby, it becomes a multilayer wiring board excellent in electrical connectivity which can make contact resistance with a probe stable for a long time.

  Further, even when the wiring conductor is miniaturized by narrowing the pitch of the wiring conductor of the multilayer wiring board, the connection strength between the wiring conductor of the multilayer wiring board and the bump of the semiconductor substrate can be strengthened. As a result, the pitch of the wiring conductors of the multilayer wiring board can be reduced, and the multilayer wiring board with high connection reliability with the semiconductor substrate can be obtained.

  Hereinafter, a multilayer wiring board of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a cross-sectional view showing an example of an embodiment of a multilayer wiring board according to the present invention, and FIG. 2 is an enlarged cross-sectional view of a main part showing a state around a wiring conductor in the multilayer wiring board shown in FIG. In these drawings, 1 is a substrate, 2 is an insulating layer, 3 is a wiring conductor, 4 is an insulating film layer as a part of the insulating layer 2, 5 is an insulating adhesive layer as a part of the insulating layer 2, 6 Is a through conductor, and 7 is a through hole.

  The substrate 1 is provided with a multilayer wiring portion in which a plurality of insulating film layers 4 are laminated with an insulating adhesive layer 5 therebetween and an insulating layer 2 and a wiring conductor 3 are laminated in multiple layers on the upper surface. It functions as a support member that supports the multilayer wiring portion.

  The substrate 1 is made of an oxide ceramic such as an aluminum oxide sintered body or a mullite sintered body, or a non-oxide type such as an aluminum nitride sintered body or silicon carbide sintered body having an oxide film on the surface. It is formed of an electrically insulating material such as ceramics, a glass epoxy resin obtained by impregnating a glass fiber base material with an epoxy resin, or a glass fiber base material impregnated with a bismaleimide triazine resin.

  When the substrate 1 is formed of, for example, an aluminum oxide sintered body, an appropriate organic solvent or solvent is added to and mixed with raw material powders such as alumina, silica, calcia, and magnesia to form a slurry. A ceramic green sheet (ceramic green sheet) is formed by adopting the doctor blade method and the calender roll method. After that, the ceramic green sheet is appropriately punched into a predetermined shape and at a high temperature (about 1600 ° C). ). Alternatively, a raw material powder is prepared by adding an appropriate organic solvent and solvent to a raw material powder such as alumina, and the raw material powder is formed into a predetermined shape by a press molding machine. Finally, the compact is heated to a high temperature (about 1600 ° C). ). Moreover, when it consists of glass epoxy resins, it manufactures, for example by impregnating the base material which consists of glass fiber with the precursor of an epoxy resin, and thermosetting this epoxy resin precursor at predetermined temperature.

  In addition, the substrate 1 is provided with a multilayer wiring portion in which a plurality of insulating layers 2 and wiring conductors 3 are laminated in a multilayer manner on the upper surface thereof. The insulating layer 2 electrically insulates the wiring conductors 3 positioned above and below, and the wiring conductor 3 functions as a transmission path for transmitting electrical signals.

  The insulating layer 2 of the multilayer wiring portion is composed of, for example, an insulating film layer 4 and an insulating adhesive layer 5, and the insulating film layer 4 is made of polyimide resin, polyphenylene sulfide resin, wholly aromatic polyester resin, fluororesin, or the like. Consists of. The insulating adhesive layer 5 is made of siloxane-modified polyamideimide resin, siloxane-modified polyimide resin, polyimide resin, bismaleimide triazine resin, or the like.

  The insulating layer 2 is prepared, for example, by first applying an insulating adhesive to an insulating film of about 12.5 to 50 μm to a dry thickness of about 5 to 20 μm using a doctor blade method or the like, and then drying the insulating film layer. 4 are stacked such that the insulating adhesive layer 5 is disposed between the upper surfaces of the substrate 1 and the lower insulating layer 2, and this is heated and pressed using a hot press device to be bonded.

  As a combination of the insulating film layer 4 and the insulating adhesive layer 5 used for these, for example, there is a combination in which the insulating film layer 4 is a polyimide resin and the insulating adhesive layer 5 is a siloxane-modified polyamideimide resin. According to this combination, the adhesion between the siloxane-modified polyamideimide resin and the polyimide resin is good and the heat resistance is high, so that the multi-layer wiring board formed by these is resistant to being mounted on a printed board or the like. Good solder heat resistance and the like.

  Further, as a combination having particularly high heat resistance, it is preferable to use the insulating film layer 4 as a polyimide resin and the insulating adhesive layer 5 as a thermoplastic polyimide resin. In the case of this combination, the heat resistance is high and the stress due to the difference in linear expansion coefficient for reducing the difference in linear expansion coefficient between the insulating film layer 4 and the insulating adhesive layer 5 can be reduced. As a result, the stress that causes separation at the interface between the wiring conductor 3 and the through conductor 6 can be reduced. In addition, since it becomes possible to reduce the overall warpage of the multilayer wiring board, the multilayer wiring can better cope with the narrow pitch of the terminals of the semiconductor integrated circuit element mounted on the surface thereof. It can be a substrate.

  Further, the wiring conductor 3 is disposed on the surface of each insulating layer 2, and the wiring conductors 3 positioned above and below the insulating layer 2 are electrically connected to each other. A through conductor 6 is embedded in the hole 7. These wiring conductors 3 and through conductors 6 are formed by adopting a thin film forming technique such as sputtering, vapor deposition or plating using a metal material such as copper, gold, aluminum, nickel, chromium, molybdenum, titanium and alloys thereof. Can be formed.

  The through conductor 6 may be formed separately from the wiring conductor 3, but it is preferable that these are formed at the same time from the viewpoint that the number of steps can be reduced, and the electrical connection reliability between them is also good. It will be something. In addition, when the wiring conductor 3 and the through conductor 6 are integrally formed, the wiring conductor 3 and the through conductor 6 are mainly formed by using an electrolytic plating method so that each can be adjusted to a desired thickness and formed by a plating film. It is good to leave.

  In the multilayer wiring board of the present invention, the wiring conductor 3 is partially embedded in the insulating layer 2 at the outer peripheral portion of the insulating layer 2 in plan view. As a result, the wiring conductor 3 can be firmly fixed to the insulating layer 2, and the wiring conductor 3 is formed on the insulating layer, particularly in the outer peripheral portion where the stress due to the difference in linear expansion coefficient between the insulating layer 2 and the wiring conductor 3 is easily applied. Peeling from 2 can be effectively prevented.

  Further, the amount of protrusion of the wiring conductor 3 protruding from the insulating layer 2 can be reduced as compared with the case where the wiring conductor 3 is disposed on the upper surface of the insulating layer 2 as in the prior art, and the flatness of the surface of the multilayer wiring board is reduced. Can be increased. Furthermore, even if the wiring conductor 3 is made thicker than before, the influence of the protrusion of the wiring conductor 3 on the flatness of the insulating layer 2 formed on the uppermost surface of the multilayer wiring board can be suppressed, and the electrical characteristics are improved. Can be made.

  When the insulating layer 2 is composed of the insulating film layer 4 and the insulating adhesive layer 5, the wiring conductor 3 is preferably embedded in the insulating film layer 4. Thereby, since the wiring conductor 3 is firmly fixed to the insulating film layer 4 having higher strength than the insulating adhesive layer 5, the wiring conductor 3 is caused by stress due to a difference in linear expansion coefficient between the wiring conductor 3 and the insulating layer 2. It can prevent peeling very effectively.

  Preferably, the wiring conductor 3 is formed between the insulating layers 2 and embedded in both the upper and lower insulating layers 2 of the wiring conductor 3. Thereby, the protrusion amount of the wiring conductor 3 can be further reduced, the flatness of the surface of the multilayer wiring board can be further increased, and the wiring conductor 3 can be more firmly fixed to the insulating layer 2.

  Further, by embedding in the insulating layer 2, the thickness of the wiring conductor 3 can be increased while maintaining the flatness of the multilayer wiring board. However, when the wiring conductor 3 is embedded only in the upper or lower insulating layer 2, As the thickness increases, in order to ensure insulation, it is necessary to increase the thickness of the insulating layer 2, whereas each wiring layer 3 is embedded in both the upper side and the lower side to saturate each insulating layer. Since the insulation can be maintained even if the thickness of 2 is reduced, the thickness of the wiring conductor 3 can be increased without increasing the thickness of the multilayer wiring board.

  The method for forming the wiring conductor 3 and the through conductor 6 is, for example, first forming a wiring pattern-shaped recess for the wiring conductor 3 so that the wiring conductor 3 is embedded in the surface of the insulating layer 2 and through holes for the through conductor 6. 7 is formed.

  The recess for the wiring conductor 3 is formed, for example, by removing a part on the upper surface side of the insulating layer 2 by performing oxygen plasma treatment on the upper surface side of the insulating layer 2 using a metal film as a mask. Further, the through hole 7 is formed by removing the insulating layer 2 at a predetermined position of the concave portion for the wiring conductor 3 using, for example, a laser. In particular, when the opening diameter of the through hole 7 is small, it is desirable to control the angle of the inner wall surface of the through hole 7 and to form the inner wall surface of the through hole 7 with an ultraviolet laser or the like that is processed smoothly. .

  Next, an underlying conductor layer composed of a diffusion prevention layer (barrier layer) made of chromium, molybdenum, titanium or the like and a copper layer mainly made of copper deposited thereon on the entire upper surface of the insulating layer 2 Is formed by electroless plating or sputtering. Then, a resist pattern is formed on the substrate 1 on which the base conductor layer is formed so as to cover the portion other than the portion that becomes the wiring conductor 3 by using a photolithography method, and then the main conductor layer portion of the wiring conductor 3 and the through conductor 6 is formed. And formed by electrolytic plating. Thereafter, the resist pattern is removed, and the excess underlying conductor layer covered with the resist pattern is removed by a chemical etching method, a dry etching method, or the like, whereby the wiring conductor 3 partially embedded in the insulating layer 2 of the present invention. Is formed.

  In order to embed the wiring conductor 3 in both the upper and lower insulating layers 2, a concave portion having a wiring pattern shape for the wiring conductor 3 is formed in the upper insulating layer 2. After the wiring conductor 3 is formed by the same method as described above, the upper and lower insulating layers 2 are laminated, so that the wiring conductor 3 embedded in both the upper and lower insulating layers 2 of the present invention is formed. Can be processed. The degree of embedding of the wiring conductor 3 can be adjusted by adjusting the depth of the recess formed in the insulating layer 2.

  In addition, the main conductor layer of the wiring conductor 3 formed on the surface of the insulating layer 2 which is the uppermost layer of the multilayer wiring board is composed of a copper layer from the viewpoint of electrical characteristics and connection reliability. In that case, a nickel layer or a gold layer is preferably formed on the main conductor layer from the viewpoint of connection reliability and environmental resistance reliability.

  Thus, according to the multilayer wiring board of the present invention, the through hole 7 positioned in the uppermost layer is embedded with the through conductor 6, and the semiconductor integrated circuit is mounted on the wiring conductor 3 immediately above the uppermost through hole 7, and A semiconductor device is obtained by electrically connecting the wiring board to an external electric circuit.

  According to the multilayer wiring board of the present invention, the probe is arranged and fixed in contact with the wiring conductor 3 formed so that a part of the wiring conductor 3 is embedded in the insulating layer 2 positioned at the uppermost layer. By connecting the multilayer wiring board electrically and mechanically to an external electric circuit, a probe card for electrically inspecting a semiconductor integrated circuit or the like corresponding to a large current is obtained.

  It should be noted that the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the present invention. For example, in the above-mentioned example, the insulating layer 2 has a two-layer structure of the insulating film layer 4 and the insulating adhesive layer 5 laminated in multiple layers. You may use what formed the agent layer 5 and laminated | stacked in multiple layers.

It is sectional drawing which shows an example of embodiment of the multilayer wiring board of this invention. FIG. 2 is an enlarged cross-sectional view of a main part showing a state around a wiring conductor in the multilayer wiring board of FIG. 1.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... substrate 2 ... insulating layer 3 ... wiring conductor 4 ... insulating film layer 5 ... insulating adhesive layer 6 ... penetrating conductor 7 ... penetrating Hole

Claims (2)

A multilayer wiring board in which a plurality of insulating layers made of resin and wiring conductors are alternately stacked, wherein the wiring conductor is partially embedded in the insulating layer at an outer peripheral portion of the insulating layer in plan view A multilayer wiring board characterized by that. 2. The multilayer wiring board according to claim 1, wherein the wiring conductor is formed between layers of the insulating layer and embedded in both of the insulating layers above and below the wiring conductor.

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