JP3854160B2

JP3854160B2 - Multilayer wiring board

Info

Publication number: JP3854160B2
Application number: JP2002014790A
Authority: JP
Inventors: 敏彦前田
Original assignee: Kyocera Corp
Current assignee: Kyocera Corp
Priority date: 2002-01-23
Filing date: 2002-01-23
Publication date: 2006-12-06
Anticipated expiration: 2022-01-23
Also published as: JP2003218531A

Description

【０００１】
【発明の属する技術分野】
本発明は多層配線基板に関し、より詳細には混成集積回路装置や半導体素子を収容する半導体素子収納用パッケージ等に使用される多層配線基板に関するものである。
【０００２】
【従来の技術】
従来、混成集積回路装置や半導体素子収納用パッケージ等に使用される多層配線基板としては、配線導体を高密度に形成することを目的として、基板上に絶縁層と配線導体層とから成る多層配線部を形成した多層配線基板が採用されていた。
【０００３】
かかる多層配線基板は、酸化アルミニウム質焼結体等から成る基板の上面に、スピンコート法等によって形成されるポリイミド樹脂等から成る絶縁層と、銅やアルミニウム等の金属から成り、めっき法や蒸着法等の薄膜形成技術およびフォトリソグラフィー技術を採用することによって形成される配線導体層とを交互に多層に積層させた構造を有している。
【０００４】
しかしながら、スピンコート法によってポリイミド樹脂から成る絶縁層を形成した場合、所望の厚みに絶縁層を形成するには多数回に分けてポリイミド樹脂の前駆体を塗布する必要があり、さらにその後にポリイミド樹脂の前駆体をポリイミド化させるキュア工程が必要となるため、製造工程が長くなるという問題点があった。
【０００５】
そこで、ポリイミド樹脂等から成る複数の絶縁フィルム層を間にビスマレイミドトリアジン樹脂等から成る絶縁性接着剤層を介して積層した多層配線基板や、あるいは液晶ポリマー等の熱可塑性樹脂を積層した多層配線基板が採用されてきている。
【０００６】
かかる多層配線基板における絶縁層の形成は、まず絶縁フィルムに絶縁性接着剤をドクターブレード法等を用いて塗布し乾燥させたものを準備し、この絶縁フィルム層を基板や下層の絶縁フィルム層の上面に間に絶縁性接着剤層が配されるように積み重ね、これを加熱プレス装置を用いて加熱加圧し接着することにより行なわれる。
【０００７】
また、上下に位置する配線導体層間の電気的接続は、レーザやドライエッチング等の手法により絶縁フィルム層および絶縁性接着剤層に貫通孔を形成し、その後、貫通孔の内壁に真空成膜法やめっき法により貫通導体を形成することにより行なわれている。
【０００８】
この配線導体層や貫通導体は以下の（１）〜（５）の工程を含む製造方法で形成されている。
（１）レーザにより開口された貫通孔の内部を過マンガン酸カリウム溶液等の粗化液で粗化する。
（２）この粗化した面にめっき触媒としてＰｄ等を付与し、その後、無電解めっきにより下地導体膜を形成する。
（３）次に、下地導体膜の上にフォトレジストを塗布するとともにこれに露光・現像を施すことによって、下地導体層のうち上層の主導体層を形成する部分に所定形状の窓部を形成する。
（４）次に、フォトレジストの窓部に露出させた下地導体層を電極として電解めっき皮膜を３〜10μｍの厚みに形成する。これによって上層の主導体層の部分に相当する露出した下地導体層上にめっき皮膜が形成され、その他の部分はフォトレジストに覆われているためにめっき皮膜が形成されず、上層の配線導体層および貫通導体に相当する部分にのみ主導体層が形成される。
（５）このようにして所定の厚さの主導体層を形成した後、フォトレジストを剥離除去し、次に、主導体層をエッチングレジストとして先に電解めっき用電極として使用した下地導体層の一部をエッチングすることによって、上層の配線導体層および貫通導体が形成される。
【０００９】
また、近年このように形成される貫通導体の一部は、基板の更なる高密度化を図るため、貫通孔をめっきにより導体金属を充填して貫通導体を形成し、上下に位置する絶縁層に形成された貫通導体を積み重ねるようにして接続された、いわゆるスタックトビア構造で形成されることがある。
【００１０】
【発明が解決しようとする課題】
しかしながら、上記のような絶縁フィルムおよび絶縁性接着剤層から成る絶縁層を加熱加圧し接着する多層配線基板においては、貫通導体と絶縁層との熱膨張係数に大きな差があるため、多層配線基板にチップ部品等を実装する際の加熱工程や温度サイクル試験等の耐環境試験の熱により応力が生じる。その応力は配線導体層の上面と貫通導体の底面との間に集中し、特に貫通導体上に貫通導体が形成されたいわゆるスタックトビア構造をとる場合、下方の貫通導体が形成されている貫通孔とその貫通導体の底面が接続されている配線導体層の上面との間に最大応力がかかることになる。その理由は、スタックトビア構造の場合、上下に重ねられた貫通導体とその貫通導体が形成されている絶縁層との接する距離が長くなり、熱膨張差による熱応力はその距離に比例するので、その結果、下方の貫通孔とそれに形成されている貫通導体の底面が接続されている配線導体層の上面との間に働く応力が大きくなることによる。つまり、上下に２つの貫通導体が重なっており、上下の絶縁層の厚みが同一である場合は、上下に重なった貫通導体とその貫通導体が形成されている上下の絶縁層との接する距離が上方の貫通導体とその貫通導体が形成されている上方の絶縁層との接する距離の約２倍となるので、下方の貫通導体の底面とその底面が接続されている配線導体層の上面との間に働く熱応力は、上方の貫通導体の底面とその底面が接続されている下方の貫通導体の上面に働く熱応力の約２倍の熱応力となる。そのため、スタックトビアの下方の貫通導体の底面とその底面が接続されている配線導体層の上面との間にクラックが生じ、配線導体層と貫通導体の剥離が発生して、多層配線基板内で配線導体層間の電気的導通が取れなくなってしまうという問題点があった。
【００１１】
本発明は上記従来の技術における問題点に鑑みてなされたものであり、その目的は、チップ部品等を実装する際の加熱工程や温度サイクル試験等の耐環境試験において発生する配線導体層とスタックトビアの下方の貫通導体との剥離を抑制した、電気的接続信頼性に優れた多層配線基板を提供することにある。
【００１２】
【課題を解決するための手段】
本発明の多層配線基板は、基板上に有機樹脂から成る複数の絶縁層と配線導体層とを多層に積層するとともに、上下に位置する前記配線導体層同士をその間の前記絶縁層に設けた貫通孔に貫通導体を配して電気的に接続して成る多層配線基板であって、前記貫通導体の一部は、第１の絶縁層に形成された第１の貫通導体がその直下の第２の絶縁層に形成された第２の貫通導体の上に重なるように形成されているとともに、前記第１および第２の絶縁層の高さをＴａおよびＴｂとし、前記第１および第２の貫通導体の底面の面積をＳａおよびＳｂとしたとき、Ｓｂ≧｛（Ｔａ＋Ｔｂ）／Ｔａ｝Ｓａを満たすことを特徴とするものである。
【００１３】
また、本発明の多層配線基板は、上記構成において、前記第２の貫通導体の底面が、この底面が接続されている前記配線導体層に0.1μｍ以上の深さで埋入していることを特徴とするものである。
【００１４】
本発明の多層配線基板によれば、第１の絶縁層に形成された第１の貫通導体がその直下の第２の絶縁層に形成された第２の貫通導体の上に重なるように形成されているとともに、第１の絶縁層および第２の絶縁層の高さをＴａおよびＴｂとし、第１および第２の貫通導体の底面の面積をＳａおよびＳｂとしたとき、Ｓｂ≧｛（Ｔａ＋Ｔｂ）／Ｔａ｝Ｓａを満たすものとしたことにより、第２の貫通導体の底面の面積Ｓｂが、第２の貫通導体の底面とこの底面が接続されている配線導体層の上面との間の接着強度がそこに働く熱応力を超えるような面積となり、第２の貫通導体の底面とこの底面が接続されている配線導体層の上面との間の剥離を防止することができる。その結果として、チップ部品等を実装する際の加熱工程や温度サイクル試験等の耐環境試験において上下に位置する配線導体層間の導通不良の発生がなくなり、電気的接続信頼性の優れた多層配線基板となる。
【００１５】
さらに、本発明の多層配線基板によれば、第２の貫通導体の底面がこの底面が接続されている配線導体層に0.1μｍ以上の深さで埋入しているときには、第２の貫通導体の底面とこの底面が接続されている配線導体層の上面との間に集中した応力を、配線導体層に埋入した貫通導体の底部の側面方向に分散することができるようになる。このことにより、多層配線基板にチップ部品等を実装する際の加熱工程や温度サイクル試験等の耐環境試験において発生する配線導体層の上面と貫通導体の底面との接する界面方向に発生するクラックの進行が抑えられ、配線導体層と貫通導体との剥離を有効になくすことができる。
【００１６】
これにより、上下に位置する配線導体層間の導通不良の発生がなくなり、より一層、電気的接続信頼性の優れた多層配線基板となる。
【００１７】
【発明の実施の形態】
以下、図面に基づいて本発明を詳細に説明する。
【００１８】
図１は本発明の多層配線基板の実施の形態の一例を示す断面図であり、図２は図１に示す多層配線基板における貫通導体が重ねて形成されている部位の周辺の構成を示す要部拡大断面図である。これらの図において、１は基板、２は多層配線部、３は配線導体層、４は絶縁フィルム層、５は絶縁性接着剤層、６は貫通孔、７は貫通導体、８は絶縁層である。
【００１９】
基板１は、その上面に複数の絶縁フィルム層４を間に絶縁性接着剤層５を介して積層した絶縁層８と配線導体層３とを多層に積層した多層配線部２が配設されており、この多層配線部２を支持する支持部材として機能する。
【００２０】
基板１は、酸化アルミニウム質焼結体，ムライト質焼結体等の酸化物系セラミックス、あるいは表面に酸化物膜を有する窒化アルミニウム質焼結体，炭化珪素質焼結体等の非酸化物系セラミックス、さらにはガラス繊維から成る基材にエポキシ樹脂を含浸させたガラスエポキシ樹脂やガラス繊維から成る基材にビスマレイミドトリアジン樹脂を含浸させたもの等の電気絶縁材料で形成されている。
【００２１】
例えば、酸化アルミニウム質焼結体で形成されている場合には、アルミナ，シリカ，カルシア，マグネシア等の原料粉末に適当な有機溶剤，溶媒を添加混合して泥漿状となすとともにこれを従来周知のドクターブレード法やカレンダーロール法を採用することによってセラミックグリーンシート（セラミック生シート）を形成し、しかる後、このセラミックグリーンシートに適当な打ち抜き加工を施し、所定形状となすとともに高温（約1600℃）で焼成することによって、あるいはアルミナ等の原料粉末に適当な有機溶剤、溶媒を添加混合して原料粉末を調整するとともにこの原料粉末をプレス成形機によって所定形状に成形し、最後にこの成形体を高温（約1600℃）で焼成することによって製作される。また、ガラスエポキシ樹脂から成る場合は、例えばガラス繊維から成る基材にエポキシ樹脂の前駆体を含浸させ、このエポキシ樹脂前駆体を所定の温度で熱硬化させることによって製作される。
【００２２】
また、基板１には、その上面に複数の絶縁フィルム層４を間に絶縁性接着剤層５を介して積層した絶縁層８と配線導体層３とを多層に積層した多層配線部２が配設されている。この多層配線部２を構成する絶縁フィルム層４は上下に位置する配線導体層３を電気的に絶縁し、配線導体層３は電気信号を伝達するための伝達路として機能する。
【００２３】
多層配線部２の絶縁層８は絶縁フィルム層４と絶縁性接着剤層５とから構成され、絶縁フィルム層４はポリイミド樹脂，ポリフェニレンサルファイド樹脂，全芳香族ポリエステル樹脂，フッ素樹脂等の有機樹脂から成る。また、絶縁性接着剤層５はポリアミドイミド樹脂，ポリイミドシロキサン樹脂，ビスマレイミドトリアジン樹脂，エポキシ樹脂等の有機樹脂から成る。
【００２４】
絶縁層８は、まず12.5〜50μｍ程度の絶縁フィルムに絶縁性接着剤をドクターブレード法等を用いて乾燥厚みで５〜20μｍ程度に塗布し乾燥させたものを準備し、この絶縁フィルムを基板１や下層の絶縁層８の上面に間に絶縁性接着剤が配されるように積み重ね、これを加熱プレス装置を用いて加熱加圧し接着することによって形成される。
【００２５】
中でも、貫通導体７を銅または銅合金で形成し、絶縁フィルム層４をポリイミド樹脂とし、絶縁性接着剤層５をポリイミドシロキサン樹脂あるいはシロキサン変性ポリアミドイミド樹脂とする組み合わせにおいては、ポリイミドシロキサン樹脂あるいはシロキサン変性ポリアミドイミド樹脂が絶縁フィルム層４との接着性も良好で、かつ耐熱性が高く、また熱膨張係数が銅と比較的近いため、貫通導体７と絶縁層８との熱膨張差も小さくなるため本発明に好適である。
【００２６】
絶縁層８には所定位置に絶縁フィルム層４および絶縁性接着剤層５を貫通する貫通孔６が形成されており、この貫通孔６内に貫通導体７が被着形成されることにより、絶縁フィルム層４を挟んで上下に位置する配線導体層３の各々を電気的に接続する接続路が形成される。
【００２７】
また、複数の貫通孔６および貫通導体７のうちの一部については、上方に位置する第１の絶縁層８ａに形成された第１の貫通孔６ａがその直下の第２の絶縁層８ｂに形成された第２の貫通孔６ｂの上に形成されており、上下で重なるように配置された第１および第２の貫通孔６ａ・６ｂの内部にはそれぞれ硫酸銅めっきにて充填された第１および第２の貫通導体７ａ・７ｂが形成される。これにより、第１の絶縁層８ａに形成された第１の貫通導体７ａが、その直下の第２の絶縁層８ｂに形成された第２の貫通導体７ｂの上に重なるように形成されている。
【００２８】
貫通孔６は、例えばレーザを使い絶縁フィルム層４および絶縁性接着剤層５から成る絶縁層８の一部を除去することにより形成される。特に、貫通孔６の開口径が小さな場合は、貫通孔６の内壁面の角度をコントロールすることが容易で貫通孔６の内壁面が滑らかに加工される紫外線レーザで形成することが望ましい。
【００２９】
各絶縁層８の絶縁フィルム層４の上面に配設される配線導体層３および貫通孔６内に配設される貫通導体７は、銅，金，アルミニウム，ニッケルおよびそれらの合金等の金属材料をスパッタリング法，蒸着法，めっき法等の薄膜形成技術を採用することによって形成することができるが、安価で電気抵抗も低い銅をめっき法にて形成することが望ましい。
【００３０】
貫通導体７は配線導体層３と別々に形成してもよいが、これらは同時に形成した方が工程数を少なくできるとともに両者の電気的な接続信頼性の点でも良好である。また、配線導体層３と貫通導体７とを一体形成する場合には、それぞれに所望の厚みのめっき膜を調整して形成することができるように、主として電解めっき法を用いて形成しておくのがよい。
【００３１】
なお、絶縁層８の最上層に形成された配線導体層３には、チップ部品の実装性および耐環境性の点から、その配線導体層３が銅層から成る場合にはその上にニッケル層や金層を形成するとよい。
【００３２】
本発明の多層配線基板においては、第１の絶縁層８ａに形成された第１の貫通導体７ａがその直下の第２の絶縁層８ｂに形成された第２の貫通導体７ｂの上に重なるように形成されているとともに、第１の絶縁層８ａおよび第２の絶縁層８ｂの高さをＴａおよびＴｂとし、第１の貫通導体７ａおよび第２の貫通導体７ｂの底面の面積をＳａおよびＳｂとしたとき、
Ｓｂ≧｛（Ｔａ＋Ｔｂ）／Ｔａ｝Ｓａ・・・・（１）
を満たすことが重要である。
【００３３】
第１の貫通孔６ａに形成された第１の貫通導体７ａの底面とその直下の第２の貫通孔６ｂに形成された第２の貫通導体７ｂの上面との間に働く応力をσＡとし、第２の貫通孔６ｂに形成された第２の貫通導体７ｂの底面とその底面が接続されている配線導体層３ｂの上面との間に働く応力をσＢとすると、これらは、絶縁層８の材料と貫通導体７の材料との熱膨張係数の差δα、貫通導体７が形成された時の温度と応力発生時の温度との差δＴ、および絶縁層８のヤング率Ｅを用いて以下のように記述できる。
【００３４】
σＡ∝ＥδαＴａδＴ・・・・・・・・・（２）
σＢ∝Ｅδα（Ｔａ＋Ｔｂ）δＴ・・・・（３）
これらの応力σＡ，σＢが貫通導体７の底面と配線導体層３の上面との接着強度を超えるとき、貫通導体７の底面と配線導体層３の上面との間で剥離が発生すると考えられる。
【００３５】
単位面積あたりの貫通導体７の底面とその底面が接続されている配線導体層３の上面との接着力をＣとすると、貫通導体が１個の場合の貫通導体の底面とこの底面が接続されている配線導体層の上面との間では、貫通導体の底面の面積をＳとし、この底面と底面が接続されている配線導体層の上面との間に働く応力をσとしたとき、その間が剥離しない条件はＣＳ≧σである。従って、第２の貫通導体７ｂの底面がその直下の配線導体層３ｂの上面から剥離しないためには、ＣＳｂ≧σＢでなければならない。ここで、接着力Ｃは貫通導体の底面がその直下の貫通導体の上面に接続されている場合についても同じであるから、第１の貫通導体７ａの底面と第２の貫通導体７ｂの上面との間では剥離が発生していないことに基づいてその部分の接着力ＣをＣＳａ≧σＡを満たす最小値として求めてそれを代入すると、σＡ（Ｓｂ／Ｓａ）≧σＢとなるから、これより式（２）および式（３）から式（１）の関係となる。従って、第２の貫通導体７ｂは、その底面の面積ＳｂがＳｂ≧｛（Ｔａ＋Ｔｂ）／Ｔａ｝Ｓａを満たすように形成することにより、第２の貫通導体８ｂの底面と配線導体３ｂの上面との間での剥離を防止することができる。また、第２の貫通導体７ｂの底面の面積Ｓｂの上限は、接続信頼性の観点からは特に上限はないが、高密度に貫通導体を配置するためには上記関係式を満たす範囲でできるだけ小さく形成するのが望ましい。
【００３６】
なお、以上のような第２の貫通導体７ｂの底面とこの底面が接続されている配線導体３ｂの上面との関係は、第２の貫通導体７ｂの底面がその直下に形成された貫通導体７に重なるように形成されている場合には、その第２の貫通導体７ｂの底面とこの底面が接続されている貫通導体の上面との間についても同様である。これにより、第２の貫通導体７ｂの底面とこの底面が接続されている貫通導体７の上面との間でも剥離が発生しないものとすることができる。
【００３７】
本発明の多層配線基板においては、第２の貫通導体７ｂの底面がこの底面が接続されている配線導体層３ｂに、埋入しかつ、その深さが0.1μｍ以上であるとよい。これにより、第２の貫通導体７ｂと配線導体層３ｂの上面との間に集中した応力を配線導体層３ｂに埋入した第２の貫通導体７ｂの底部の側面方向に分散することができる。その結果、多層配線基板にチップ部品等を実装する際の加熱工程の温度により配線導体層３の上面とその上に複数個が積み重ねられて形成された貫通導体７の底面とが接している界面方向に発生するクラックの進行が抑えられ、配線導体層３と貫通導体７との間の剥離を有効になくすことができる。この埋入深さが0.1μｍより小さい場合は、貫通導体７と配線導体層３と絶縁層８の絶縁性接着剤層５とが接する最大応力点からの距離が短いため、第２の貫通導体７ｂの底部の側面方向への応力分散の効果が十分に発揮されない。
【００３８】
また、第２の貫通導体７ｂの底面を配線導体層３ｂの上面に埋入させる場合に、配線導体層３ｂの上面に第２の貫通導体７ｂの底面が埋入する凹部を形成するには、例えば、配線導体層３ｂの上面に第２の貫通孔６ｂが開口した第２の絶縁層８ｂを形成した後、第２の貫通孔６ｂを窓部としてその底に露出している配線導体層３ｂの上面をエッチングによって凹状に除去することにより、その部分の配線導体層３ｂの上面に、第２の貫通孔６ｂの内面に形成される第２の貫通導体７ｂの底面を埋入させる凹部を形成することができる。このとき、凹部を1.0μｍ以上の深さで形成すると、第２の絶縁層８ｂと配線導体層３ｂとの間に剥離が発生しやすくなるため、凹部の深さすなわち第２の貫通導体７ｂの底面が配線導体層３ｂに埋入する深さは1.0μｍを超えないことが望ましい。
【００３９】
かくして、本発明の多層配線基板によれば、基板１の上面に積層された多層配線部２の上に半導体素子や容量素子，抵抗器等の電子部品を搭載実装し、電子部品の各電極を配線導体層３に電気的に接続することによって半導体装置や混成集積回路装置等となる。
【００４０】
【実施例】
絶縁フィルムとしてユーピレックスＳ（宇部興産株式会社製ポリイミドフィルム、商品名、熱膨張係数12×10^-6／℃）の12.5μｍ厚みのものに絶縁性接着剤としてシロキサン変性ポリアミドイミド（熱膨張係数50×10^-6／℃）を10μｍ厚みに塗布し、絶縁性接着剤層付きの絶縁フィルム層を準備した。次に、配線導体層（第３の配線導体層）を形成したアルミナ基板（100ｍｍ角）に圧力３ＭＰａ，260℃，60分間の加熱加圧条件で先の絶縁フィルム層を絶縁性接着剤層を間にして積層し絶縁層（第２の絶縁層）を形成した。その後、ＵＶレーザにて表１に示すような直径の貫通孔（第２の貫通孔）の加工を行ない、次いで、スパッタリング法にてＣｒとＣｕとの多層膜を形成し、電解めっき用の下地導体層を形成した。次に、配線導体層および貫通導体を形成する以外の部分にフォトレジストをマスキングし、電解硫酸銅めっき(荏原ユージライト製キューブライトＶＦ２)にて配線導体層および貫通孔を充填した貫通導体（第２の貫通導体）を形成した。その後、フォトレジストを剥離し、電解銅めっき用の下地導体層を除去することにより、配線導体層（第２の配線導体層）および貫通導体（第２の貫通導体）を形成した。
【００４１】
次に、上記手順と同様の方法で第１の絶縁層，第１の配線導体層，第２の配線導体層と第１の配線導体層とを接続する第１の貫通導体を形成した。ただし、第１の貫通導体の直径は20μｍまたは30μｍとして第１の貫通導体の底面と第２の貫通導体の底面との面積比（Ｓｂ／Ｓａ）が表１に示すような値になるようにした。また、第１の配線導体層には表層保護膜としてさらにニッケル層と金層を順次形成した。
【００４２】
以上のような方法で900穴組の貫通導体の接続抵抗値を測定できる試験片を製作し、リフロー通炉試験（260℃ピーク），温度サイクル試験（−55℃⇔＋125℃，1000サイクル），高温放置試験（150℃，1000時間）を行ない、貫通導体の接続抵抗値の変化率を評価した。判定は初期値に対して±10％以上の変化を示したものを故障とした。各試験における故障数／サンプル数の結果のまとめを表１に示す。
【００４３】
【表１】

【００４４】
表１に示すように、上下に重なった貫通導体において、第２の貫通導体の底面の面積が第１の貫通導体の底面の面積に対し、Ｓｂ≧｛（Ｔａ＋Ｔｂ）／Ｔａ｝Ｓａ、この例の場合はＳｂ／Ｓａ≧２を満たさない場合は、貫通導体の接続抵抗に大幅な上昇が見られて故障数が大きくなった。この故障箇所の不良解析を行なった結果、第２の貫通導体の底面とこの底面が接続されている配線導体層（第３の配線導体層）の上面との間で剥離が発生していることが判明した。この剥離の原因は、絶縁層と貫通導体との熱膨張差により貫通導体が押し上げられ、その結果、最も高い応力が第２の貫通導体の底面とこの底面が接続されている配線導体層（第３の配線導体層）の上面との間に発生し、第２の貫通導体の底面とその底面が接続されている配線導体層の上面との間の接着強度を超えたためである。
【００４５】
なお、本発明は上記の実施の形態の例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能である。例えば、上述の実施の形態の例においては基板１の上面にのみ絶縁層８と配線導体層３とから成る多層配線部２を設けたが、多層配線部２を基板１の下面側のみに設けても、上下の両面に設けてもよい。また、上述の実施の形態の例においては貫通孔６および貫通導体７の横断面形状は円形であったが、四角形状等の多角形でもよい。
【００４６】
【発明の効果】
以上のように、本発明の多層配線基板によれば、第１の絶縁層に形成された第１の貫通導体がその直下の第２の絶縁層に形成された第２の貫通導体の上に重なるように形成されているとともに、第１の絶縁層および第２の絶縁層の高さをＴａおよびＴｂとし、第１および第２の貫通導体の底面の面積をＳａおよびＳｂとしたとき、Ｓｂ≧｛（Ｔａ＋Ｔｂ）／Ｔａ｝Ｓａを満たすものとしたことにより、第２の貫通導体の底面の面積Ｓｂが、第２の貫通導体の底面とこの底面が接続されている配線導体層の上面との間の接着強度がそこに働く熱応力を超えるような面積となり、第２の貫通導体の底面とこの底面が接続されている配線導体層の上面との間の剥離を防止することができる。その結果として、チップ部品等を実装する際の加熱工程や温度サイクル試験等の耐環境試験において上下に位置する配線導体層間の導通不良の発生がなくなり、電気的接続信頼性の優れた多層配線基板となる。
【００４７】
さらに、本発明の多層配線基板によれば、第２の貫通導体の底面がこの底面が接続されている配線導体層に0.1μｍ以上の深さで埋入しているときには、第２の貫通導体の底面とこの底面が接続されている配線導体層の上面との間に集中した応力を、配線導体層に埋入した貫通導体の底部の側面方向に分散することができるようになる。このことにより、多層配線基板にチップ部品等を実装する際の加熱工程や温度サイクル試験等の耐環境試験において発生する配線導体層の上面と貫通導体の底面との接する界面方向に発生するクラックの進行が抑えられ、配線導体層と貫通導体との剥離を有効になくすことができる。
【００４８】
これにより、上下に位置する配線導体層間の導通不良の発生がなくなり、より一層、電気的接続信頼性の優れた多層配線基板となる。
【図面の簡単な説明】
【図１】本発明の多層配線基板の実施の形態の一例を示す断面図である。
【図２】図１に示す多層配線基板における貫通導体が重ねて形成されている部位の周辺の構成を示す要部拡大断面図である。
【符号の説明】
１・・・・基板
２・・・・多層配線部
３・・・・配線導体層
４・・・・絶縁フィルム層
５・・・・絶縁性接着剤層
６・・・・貫通孔
７・・・・貫通導体
７ａ・・・第１の貫通導体
７ｂ・・・第２の貫通導体
８・・・・絶縁層
８ａ・・・第１の絶縁層
８ｂ・・・第２の絶縁層[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multilayer wiring board, and more particularly to a multilayer wiring board used for a hybrid integrated circuit device, a semiconductor element housing package for housing semiconductor elements, and the like.
[0002]
[Prior art]
Conventionally, as a multilayer wiring board used for a hybrid integrated circuit device, a package for housing a semiconductor element, etc., a multilayer wiring composed of an insulating layer and a wiring conductor layer is formed on the substrate for the purpose of forming wiring conductors at a high density. A multilayer wiring board having a portion formed thereon has been adopted.
[0003]
Such a multilayer wiring board is made of an insulating layer made of a polyimide resin or the like formed by a spin coating method or the like on a top surface of a substrate made of an aluminum oxide sintered body or the like, and a metal such as copper or aluminum, and is plated or vapor-deposited. It has a structure in which wiring conductor layers formed by adopting a thin film forming technique such as a method and a photolithography technique are alternately laminated in multiple layers.
[0004]
However, when an insulating layer made of polyimide resin is formed by a spin coating method, it is necessary to apply a polyimide resin precursor in a number of times to form the insulating layer in a desired thickness. This requires a curing process for polyimidating the precursor of the above, and thus the manufacturing process becomes long.
[0005]
Therefore, a multilayer wiring board in which a plurality of insulating film layers made of polyimide resin or the like are laminated via an insulating adhesive layer made of bismaleimide triazine resin or the like, or multilayer wiring in which a thermoplastic resin such as a liquid crystal polymer is laminated Substrates have been adopted.
[0006]
In order to form an insulating layer in such a multilayer wiring board, first, an insulating film is prepared by applying an insulating adhesive using a doctor blade method and drying, and this insulating film layer is used as a substrate or a lower insulating film layer. It is carried out by stacking the insulating adhesive layers so as to be disposed between the upper surfaces and bonding them by applying heat and pressure using a hot press device.
[0007]
In addition, the electrical connection between the upper and lower wiring conductor layers is achieved by forming through holes in the insulating film layer and the insulating adhesive layer by a method such as laser or dry etching, and then forming a vacuum film on the inner walls of the through holes. Or by forming through conductors by plating.
[0008]
The wiring conductor layer and the through conductor are formed by a manufacturing method including the following steps (1) to (5).
(1) The inside of the through hole opened by the laser is roughened with a roughening solution such as a potassium permanganate solution.
(2) Pd or the like is applied as a plating catalyst to the roughened surface, and then a base conductor film is formed by electroless plating.
(3) Next, by applying a photoresist on the underlying conductor film and exposing / developing it, a window having a predetermined shape is formed in the portion of the underlying conductor layer where the upper main conductor layer is to be formed. To do.
(4) Next, an electrolytic plating film is formed to a thickness of 3 to 10 μm using the underlying conductor layer exposed at the window portion of the photoresist as an electrode. As a result, a plating film is formed on the exposed underlying conductor layer corresponding to the portion of the upper main conductor layer, and no plating film is formed because the other portions are covered with the photoresist, so that the upper wiring conductor layer The main conductor layer is formed only in the portion corresponding to the through conductor.
(5) After the main conductor layer having a predetermined thickness is formed in this way, the photoresist is peeled and removed, and then the main conductor layer is used as an etching resist for the underlying conductor layer previously used as an electrode for electrolytic plating. By etching a part, an upper wiring conductor layer and a through conductor are formed.
[0009]
In recent years, some of the through conductors formed in this way are formed with through conductors filled with conductive metal by plating the through holes to further increase the density of the substrate. In some cases, the vias are formed in a so-called stacked via structure connected in a stacked manner.
[0010]
[Problems to be solved by the invention]
However, in the multilayer wiring board in which the insulating layer composed of the insulating film and the insulating adhesive layer as described above is heated and pressed to adhere, there is a large difference in the thermal expansion coefficient between the through conductor and the insulating layer. Stress is generated by heat in an environmental resistance test such as a heating process or a temperature cycle test when mounting a chip part or the like on the chip. The stress is concentrated between the upper surface of the wiring conductor layer and the bottom surface of the through conductor, and in particular, in the case of a so-called stacked via structure in which a through conductor is formed on the through conductor, the through hole in which the lower through conductor is formed And a maximum stress is applied between the through conductor and the upper surface of the wiring conductor layer to which the bottom surface of the through conductor is connected. The reason is that in the case of the stacked via structure, the distance between the vertically stacked through conductor and the insulating layer in which the through conductor is in contact is increased, and the thermal stress due to the difference in thermal expansion is proportional to the distance. As a result, the stress acting between the lower through hole and the upper surface of the wiring conductor layer to which the bottom surface of the through conductor formed therein is connected increases. That is, when two through conductors overlap each other and the thickness of the upper and lower insulating layers is the same, the distance between the upper and lower overlapping conductors and the upper and lower insulating layers where the through conductors are formed is Since the distance between the upper penetrating conductor and the upper insulating layer on which the penetrating conductor is in contact is approximately twice, the bottom surface of the lower penetrating conductor and the upper surface of the wiring conductor layer to which the bottom surface is connected The thermal stress acting between them is approximately twice the thermal stress acting on the bottom surface of the upper through conductor and the upper surface of the lower through conductor to which the bottom surface is connected. For this reason, a crack is generated between the bottom surface of the through conductor below the stacked via and the top surface of the wiring conductor layer to which the bottom surface is connected, and the wiring conductor layer and the through conductor are separated. There was a problem that electrical continuity between the wiring conductor layers could not be obtained.
[0011]
The present invention has been made in view of the above-described problems in the prior art, and its purpose is to form a wiring conductor layer and a stack generated in an environmental resistance test such as a heating process or a temperature cycle test when mounting a chip component or the like. An object of the present invention is to provide a multilayer wiring board excellent in electrical connection reliability, in which peeling from a through conductor below Tobia is suppressed.
[0012]
[Means for Solving the Problems]
The multilayer wiring board of the present invention has a plurality of insulating layers made of an organic resin and a wiring conductor layer laminated in a multilayer on the board, and the wiring conductor layers positioned above and below are provided in the insulating layer therebetween. A multilayer wiring board in which a through conductor is arranged and electrically connected to a hole, and a part of the through conductor is a second through which is formed immediately below the first through conductor formed in the first insulating layer. The first and second penetrating conductors are formed so as to overlap the second penetrating conductor formed in the insulating layer, and the heights of the first and second insulating layers are Ta and Tb. When the area of the bottom surface of the conductor is Sa and Sb, Sb ≧ {(Ta + Tb) / Ta} Sa is satisfied.
[0013]
In the multilayer wiring board of the present invention, in the above configuration, the bottom surface of the second through conductor is embedded in the wiring conductor layer to which the bottom surface is connected at a depth of 0.1 μm or more. It is a feature.
[0014]
According to the multilayer wiring board of the present invention, the first through conductor formed in the first insulating layer is formed so as to overlap the second through conductor formed in the second insulating layer immediately below the first through conductor. And when the heights of the first and second insulating layers are Ta and Tb, and the areas of the bottom surfaces of the first and second through conductors are Sa and Sb, Sb ≧ {(Ta + Tb) / Ta} Sa so that the area Sb of the bottom surface of the second through conductor is the adhesive strength between the bottom surface of the second through conductor and the top surface of the wiring conductor layer to which the bottom surface is connected. Is larger than the thermal stress acting on the second through conductor, and peeling between the bottom surface of the second through conductor and the upper surface of the wiring conductor layer to which the bottom surface is connected can be prevented. As a result, there is no continuity failure between the upper and lower wiring conductor layers in environmental resistance tests such as heating processes and temperature cycle tests when mounting chip parts, etc., and a multilayer wiring board with excellent electrical connection reliability It becomes.
[0015]
Furthermore, according to the multilayer wiring board of the present invention, when the bottom surface of the second through conductor is buried at a depth of 0.1 μm or more in the wiring conductor layer to which the bottom surface is connected, the second through conductor The stress concentrated between the bottom surface of the wiring conductor layer and the upper surface of the wiring conductor layer to which the bottom surface is connected can be distributed in the side surface direction of the bottom portion of the through conductor embedded in the wiring conductor layer. As a result, cracks generated in the interface direction between the upper surface of the wiring conductor layer and the bottom surface of the through conductor, which are generated in an environmental resistance test such as a heating process or a temperature cycle test when a chip component is mounted on the multilayer wiring board, are prevented. Progress is suppressed and peeling between the wiring conductor layer and the through conductor can be effectively eliminated.
[0016]
As a result, the occurrence of poor conduction between the upper and lower wiring conductor layers is eliminated, and the multilayer wiring board is further improved in electrical connection reliability.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the drawings.
[0018]
FIG. 1 is a cross-sectional view showing an example of an embodiment of a multilayer wiring board according to the present invention, and FIG. 2 is a schematic diagram showing a peripheral configuration of a portion where through conductors are overlapped in the multilayer wiring board shown in FIG. FIG. In these figures, 1 is a substrate, 2 is a multilayer wiring portion, 3 is a wiring conductor layer, 4 is an insulating film layer, 5 is an insulating adhesive layer, 6 is a through hole, 7 is a through conductor, and 8 is an insulating layer. is there.
[0019]
The substrate 1 is provided with a multilayer wiring portion 2 in which an insulating layer 8 having a plurality of insulating film layers 4 laminated with an insulating adhesive layer 5 interposed therebetween and a wiring conductor layer 3 are laminated in multiple layers on the upper surface. It functions as a support member that supports the multilayer wiring portion 2.
[0020]
The substrate 1 is made of an oxide ceramic such as an aluminum oxide sintered body or a mullite sintered body, or a non-oxide type such as an aluminum nitride sintered body or silicon carbide sintered body having an oxide film on the surface. It is formed of an electrically insulating material such as ceramics, a glass epoxy resin obtained by impregnating a glass fiber base material with an epoxy resin, or a glass fiber base material impregnated with a bismaleimide triazine resin.
[0021]
For example, when it is formed of an aluminum oxide sintered body, an appropriate organic solvent or solvent is added to and mixed with raw material powders such as alumina, silica, calcia, and magnesia to form a slurry, and this is conventionally known. A ceramic green sheet (green ceramic sheet) is formed by adopting the doctor blade method or the calender roll method, and then the ceramic green sheet is appropriately punched into a predetermined shape and at a high temperature (about 1600 ° C). Or by adding an appropriate organic solvent and solvent to the raw material powder such as alumina to adjust the raw material powder, and then forming the raw material powder into a predetermined shape by a press molding machine. Manufactured by firing at high temperature (about 1600 ° C). Moreover, when it consists of glass epoxy resins, it manufactures, for example by impregnating the base material which consists of glass fiber with the precursor of an epoxy resin, and thermosetting this epoxy resin precursor at predetermined temperature.
[0022]
The substrate 1 is provided with a multilayer wiring portion 2 in which a plurality of insulating film layers 4 are laminated on the upper surface with an insulating adhesive layer 5 interposed therebetween, and a wiring conductor layer 3 is laminated in multiple layers. It is installed. The insulating film layer 4 constituting the multilayer wiring portion 2 electrically insulates the wiring conductor layer 3 positioned above and below, and the wiring conductor layer 3 functions as a transmission path for transmitting an electrical signal.
[0023]
The insulating layer 8 of the multilayer wiring portion 2 is composed of an insulating film layer 4 and an insulating adhesive layer 5, and the insulating film layer 4 is made of an organic resin such as polyimide resin, polyphenylene sulfide resin, wholly aromatic polyester resin, or fluorine resin. Become. The insulating adhesive layer 5 is made of an organic resin such as a polyamide-imide resin, a polyimide siloxane resin, a bismaleimide triazine resin, or an epoxy resin.
[0024]
First, the insulating layer 8 is prepared by applying an insulating adhesive to an insulating film of about 12.5 to 50 μm using a doctor blade method to a dry thickness of about 5 to 20 μm, and drying the insulating film. In addition, the insulating layer 8 is stacked on the upper surface of the lower insulating layer 8 so that an insulating adhesive is disposed between them, and is heated and pressed using a heating press device to be bonded.
[0025]
In particular, in a combination in which the through conductor 7 is formed of copper or a copper alloy, the insulating film layer 4 is a polyimide resin, and the insulating adhesive layer 5 is a polyimide siloxane resin or a siloxane-modified polyamideimide resin, a polyimide siloxane resin or siloxane is used. Since the modified polyamideimide resin has good adhesion to the insulating film layer 4 and high heat resistance, and the thermal expansion coefficient is relatively close to copper, the thermal expansion difference between the through conductor 7 and the insulating layer 8 is also small. Therefore, it is suitable for the present invention.
[0026]
A through hole 6 is formed in the insulating layer 8 at a predetermined position so as to penetrate the insulating film layer 4 and the insulating adhesive layer 5. A through conductor 7 is formed in the through hole 6 so as to be insulated. A connection path that electrically connects each of the wiring conductor layers 3 positioned above and below the film layer 4 is formed.
[0027]
In addition, with respect to some of the plurality of through holes 6 and the through conductors 7, the first through holes 6a formed in the first insulating layer 8a positioned above are formed in the second insulating layer 8b immediately below the first through holes 6a. The first and second through holes 6a and 6b, which are formed on the formed second through hole 6b and are arranged so as to overlap in the vertical direction, are filled with copper sulfate plating respectively. First and second through conductors 7a and 7b are formed. Accordingly, the first through conductor 7a formed in the first insulating layer 8a is formed so as to overlap the second through conductor 7b formed in the second insulating layer 8b immediately below the first through conductor 7a. .
[0028]
The through-hole 6 is formed by removing a part of the insulating layer 8 composed of the insulating film layer 4 and the insulating adhesive layer 5 using, for example, a laser. In particular, when the opening diameter of the through hole 6 is small, it is desirable to control the angle of the inner wall surface of the through hole 6 and to form an ultraviolet laser that smoothly processes the inner wall surface of the through hole 6.
[0029]
The wiring conductor layer 3 disposed on the upper surface of the insulating film layer 4 of each insulating layer 8 and the through conductor 7 disposed in the through hole 6 are made of a metal material such as copper, gold, aluminum, nickel and alloys thereof. Can be formed by adopting a thin film forming technique such as sputtering, vapor deposition or plating, but it is desirable to form copper with low cost and low electrical resistance by plating.
[0030]
The through conductors 7 may be formed separately from the wiring conductor layer 3, but forming them simultaneously can reduce the number of processes and is excellent in terms of electrical connection reliability between them. When the wiring conductor layer 3 and the through conductor 7 are integrally formed, the wiring conductor layer 3 and the through conductor 7 are formed mainly using an electrolytic plating method so that a plating film having a desired thickness can be adjusted for each. It is good.
[0031]
The wiring conductor layer 3 formed on the uppermost layer of the insulating layer 8 includes a nickel layer on the wiring conductor layer 3 in the case where the wiring conductor layer 3 is made of a copper layer from the viewpoint of the mountability and environmental resistance of the chip component. A metal layer may be formed.
[0032]
In the multilayer wiring board of the present invention, the first through conductor 7a formed in the first insulating layer 8a overlaps the second through conductor 7b formed in the second insulating layer 8b immediately below the first through conductor 7a. The heights of the first insulating layer 8a and the second insulating layer 8b are Ta and Tb, and the areas of the bottom surfaces of the first through conductor 7a and the second through conductor 7b are Sa and Sb. When
Sb ≧ {(Ta + Tb) / Ta} Sa (1)
It is important to meet.
[0033]
The stress acting between the bottom surface of the first through conductor 7a formed in the first through hole 6a and the upper surface of the second through conductor 7b formed in the second through hole 6b immediately below the first through conductor 7a is σA, Assuming that the stress acting between the bottom surface of the second through conductor 7b formed in the second through hole 6b and the upper surface of the wiring conductor layer 3b to which the bottom surface is connected is σB, these are as follows. Using the difference δα in the thermal expansion coefficient between the material and the material of the through conductor 7, the difference δT between the temperature at which the through conductor 7 is formed and the temperature at which the stress is generated, and the Young's modulus E of the insulating layer 8, Can be described as follows.
[0034]
σA∝EδαTaδT (2)
σB∝Eδα (Ta + Tb) δT (3)
When these stresses σA and σB exceed the adhesive strength between the bottom surface of the through conductor 7 and the top surface of the wiring conductor layer 3, it is considered that peeling occurs between the bottom surface of the through conductor 7 and the top surface of the wiring conductor layer 3.
[0035]
When the adhesive force between the bottom surface of the through conductor 7 per unit area and the upper surface of the wiring conductor layer 3 to which the bottom surface is connected is C, the bottom surface of the through conductor and the bottom surface when there is one through conductor are connected. When the area of the bottom surface of the through conductor is S and the stress acting between the bottom surface and the top surface of the wiring conductor layer to which the bottom surface is connected is σ, The condition for not peeling is CS ≧ σ. Therefore, CSb ≧ σB must be satisfied so that the bottom surface of the second through conductor 7b does not peel from the top surface of the wiring conductor layer 3b immediately below the second through conductor 7b. Here, since the adhesive force C is the same when the bottom surface of the through conductor is connected to the top surface of the through conductor immediately below, the bottom surface of the first through conductor 7a and the top surface of the second through conductor 7b If the adhesive strength C of the part is determined as a minimum value satisfying CSa ≧ σA based on the fact that no peeling occurs between the two, and is substituted, σA (Sb / Sa) ≧ σB is obtained. From (2) and (3) to (1). Therefore, the second through conductor 7b is formed so that the area Sb of the bottom surface thereof satisfies Sb ≧ {(Ta + Tb) / Ta} Sa, whereby the bottom surface of the second through conductor 8b and the upper surface of the wiring conductor 3b are formed. Can be prevented. Further, the upper limit of the bottom surface area Sb of the second through conductor 7b is not particularly limited from the viewpoint of connection reliability. However, in order to arrange the through conductors at high density, the upper limit is as small as possible within the range satisfying the above relational expression. It is desirable to form.
[0036]
The relationship between the bottom surface of the second through conductor 7b and the top surface of the wiring conductor 3b to which the bottom surface is connected is as follows. The through conductor 7 has the bottom surface of the second through conductor 7b formed immediately below it. The same applies to the space between the bottom surface of the second through conductor 7b and the top surface of the through conductor to which the bottom surface is connected. Thereby, peeling can be prevented from occurring between the bottom surface of the second through conductor 7b and the top surface of the through conductor 7 to which the bottom surface is connected.
[0037]
In the multilayer wiring board of the present invention, the bottom surface of the second through conductor 7b is preferably embedded in the wiring conductor layer 3b to which the bottom surface is connected and the depth thereof is 0.1 μm or more. Thereby, the stress concentrated between the 2nd penetration conductor 7b and the upper surface of the wiring conductor layer 3b can be disperse | distributed to the side surface direction of the bottom part of the 2nd penetration conductor 7b embedded in the wiring conductor layer 3b. As a result, the interface between the upper surface of the wiring conductor layer 3 and the bottom surface of the through conductor 7 formed by stacking a plurality of the wiring conductor layers 3 on the basis of the temperature of the heating process when mounting the chip parts or the like on the multilayer wiring board. The progress of cracks occurring in the direction is suppressed, and peeling between the wiring conductor layer 3 and the through conductor 7 can be effectively eliminated. When the embedding depth is smaller than 0.1 μm, the distance from the maximum stress point where the through conductor 7, the wiring conductor layer 3, and the insulating adhesive layer 5 of the insulating layer 8 are in contact with each other is short. The effect of stress distribution in the side surface direction of the bottom portion of 7b is not sufficiently exhibited.
[0038]
In order to form a recess in which the bottom surface of the second through conductor 7b is embedded in the top surface of the wiring conductor layer 3b when the bottom surface of the second through conductor 7b is embedded in the top surface of the wiring conductor layer 3b, For example, after the second insulating layer 8b having the second through hole 6b opened is formed on the upper surface of the wiring conductor layer 3b, the wiring conductor layer 3b exposed at the bottom using the second through hole 6b as a window portion. By removing the upper surface of the recess in a concave shape by etching, a recess is formed on the upper surface of the wiring conductor layer 3b at that portion so as to embed the bottom surface of the second through conductor 7b formed on the inner surface of the second through hole 6b. can do. At this time, if the concave portion is formed with a depth of 1.0 μm or more, peeling is likely to occur between the second insulating layer 8b and the wiring conductor layer 3b. Therefore, the depth of the concave portion, that is, the second through conductor 7b It is desirable that the depth at which the bottom surface is embedded in the wiring conductor layer 3b does not exceed 1.0 μm.
[0039]
Thus, according to the multilayer wiring board of the present invention, electronic components such as semiconductor elements, capacitive elements, resistors, and the like are mounted and mounted on the multilayer wiring portion 2 laminated on the upper surface of the substrate 1, and each electrode of the electronic component is mounted. By electrically connecting to the wiring conductor layer 3, a semiconductor device, a hybrid integrated circuit device, or the like is obtained.
[0040]
【Example】
Insulating film Upilex S (polyimide film manufactured by Ube Industries, Ltd., trade name, thermal expansion coefficient 12 × 10 ⁻⁶ / ° C.) having a thickness of 12.5 μm and insulating adhesive with siloxane-modified polyamideimide (thermal expansion coefficient 50 × 10 ⁻⁶ / ° C.) was applied to a thickness of 10 μm to prepare an insulating film layer with an insulating adhesive layer. Next, the insulating adhesive layer is applied to the alumina substrate (100 mm square) on which the wiring conductor layer (third wiring conductor layer) is formed under the conditions of heating and pressing at a pressure of 3 MPa, 260 ° C. for 60 minutes. An insulating layer (second insulating layer) was formed by stacking them in between. Thereafter, through holes (second through holes) having a diameter as shown in Table 1 are processed with a UV laser, and then a multilayer film of Cr and Cu is formed by a sputtering method. A conductor layer was formed. Next, the photoresist is masked on the portions other than the wiring conductor layer and the through conductor, and the through conductor (first through hole) filled with the wiring conductor layer and the through hole by electrolytic copper sulfate plating (Cubelight VF2 manufactured by Sugawara Eugelite) 2 through conductors). Thereafter, the photoresist was peeled off and the base conductor layer for electrolytic copper plating was removed, thereby forming a wiring conductor layer (second wiring conductor layer) and a through conductor (second through conductor).
[0041]
Next, the 1st penetration conductor which connects the 1st insulating layer, the 1st wiring conductor layer, the 2nd wiring conductor layer, and the 1st wiring conductor layer by the method similar to the above-mentioned procedure was formed. However, the diameter of the first through conductor is 20 μm or 30 μm so that the area ratio (Sb / Sa) between the bottom surface of the first through conductor and the bottom surface of the second through conductor becomes a value as shown in Table 1. did. Further, a nickel layer and a gold layer were sequentially formed as a surface protective film on the first wiring conductor layer.
[0042]
Test pieces that can measure the connection resistance value of 900-hole through conductors by the above method are manufactured, reflow furnace test (260 ° C peak), temperature cycle test (-55 ° C ⇔ + 125 ° C, 1000 cycles), A high temperature storage test (150 ° C, 1000 hours) was conducted to evaluate the rate of change in the connection resistance value of the through conductor. Judgment was determined to be a failure indicating a change of ± 10% or more relative to the initial value. A summary of the number of failures / number of samples in each test is shown in Table 1.
[0043]
[Table 1]

[0044]
As shown in Table 1, in the through conductors stacked vertically, the area of the bottom surface of the second through conductor is Sb ≧ {(Ta + Tb) / Ta} Sa with respect to the area of the bottom surface of the first through conductor. In this case, when Sb / Sa ≧ 2 was not satisfied, the connection resistance of the through conductor was significantly increased, and the number of failures increased. As a result of performing failure analysis of this failure location, separation has occurred between the bottom surface of the second through conductor and the top surface of the wiring conductor layer (third wiring conductor layer) to which the bottom surface is connected. There was found. The cause of this peeling is that the through conductor is pushed up by the difference in thermal expansion between the insulating layer and the through conductor, and as a result, the highest stress is applied to the bottom surface of the second through conductor and the wiring conductor layer (first conductor) connected to the bottom surface. This is because the adhesive strength between the bottom surface of the second through conductor and the top surface of the wiring conductor layer to which the bottom surface is connected is exceeded.
[0045]
In addition, this invention is not limited to the example of said embodiment, A various change is possible if it is the range which does not deviate from the summary of this invention. For example, in the example of the above-described embodiment, the multilayer wiring portion 2 including the insulating layer 8 and the wiring conductor layer 3 is provided only on the upper surface of the substrate 1, but the multilayer wiring portion 2 is provided only on the lower surface side of the substrate 1. Alternatively, it may be provided on both upper and lower surfaces. Further, in the example of the above-described embodiment, the cross-sectional shape of the through hole 6 and the through conductor 7 is circular, but may be a polygon such as a quadrangle.
[0046]
【The invention's effect】
As described above, according to the multilayer wiring board of the present invention, the first through conductor formed in the first insulating layer is formed on the second through conductor formed in the second insulating layer immediately below the first through conductor. When the heights of the first insulating layer and the second insulating layer are Ta and Tb and the areas of the bottom surfaces of the first and second through conductors are Sa and Sb, By satisfying ≧ {(Ta + Tb) / Ta} Sa, the area Sb of the bottom surface of the second through conductor is such that the bottom surface of the second through conductor and the top surface of the wiring conductor layer to which the bottom surface is connected. The area between the two through conductors and the upper surface of the wiring conductor layer to which the bottom surface is connected can be prevented. As a result, there is no continuity failure between the upper and lower wiring conductor layers in environmental resistance tests such as heating processes and temperature cycle tests when mounting chip parts, etc., and a multilayer wiring board with excellent electrical connection reliability It becomes.
[0047]
Furthermore, according to the multilayer wiring board of the present invention, when the bottom surface of the second through conductor is buried at a depth of 0.1 μm or more in the wiring conductor layer to which the bottom surface is connected, the second through conductor The stress concentrated between the bottom surface of the wiring conductor layer and the upper surface of the wiring conductor layer to which the bottom surface is connected can be distributed in the side surface direction of the bottom portion of the through conductor embedded in the wiring conductor layer. As a result, cracks generated in the interface direction between the upper surface of the wiring conductor layer and the bottom surface of the through conductor, which are generated in an environmental resistance test such as a heating process or a temperature cycle test when a chip component is mounted on the multilayer wiring board, are prevented. Progress is suppressed and peeling between the wiring conductor layer and the through conductor can be effectively eliminated.
[0048]
As a result, the occurrence of poor conduction between the upper and lower wiring conductor layers is eliminated, and the multilayer wiring board is further improved in electrical connection reliability.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an example of an embodiment of a multilayer wiring board according to the present invention.
FIG. 2 is an enlarged cross-sectional view of a main part showing a configuration around a portion where through conductors are overlaid in the multilayer wiring board shown in FIG. 1;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ...... Board | substrate 2 ... Multi-layer wiring part 3 ... Wiring conductor layer 4 ... Insulating film layer 5 ... Insulating adhesive layer 6 ... Through-hole 7 ... .. Penetration conductor 7a ... 1st penetration conductor 7b ... 2nd penetration conductor 8 ...... Insulating layer 8a ... 1st insulating layer 8b ... 2nd insulating layer

Claims

A plurality of insulating layers made of organic resin and wiring conductor layers are laminated in layers on a substrate, and through conductors are arranged in through holes provided in the insulating layer between the wiring conductor layers positioned above and below. An electrically connected multilayer wiring board, wherein a part of the through conductor is a first through conductor formed in a first insulating layer and formed in a second insulating layer immediately below the first through conductor. And the height of the first and second insulating layers is Ta and Tb, and the area of the bottom surface of the first and second through conductors is Sa and A multilayer wiring board characterized by satisfying Sb ≧ {(Ta + Tb) / Ta} Sa when Sb is satisfied.

The multilayer wiring board according to claim 1, wherein the bottom surface of the second through conductor is embedded in the wiring conductor layer to which the bottom surface is connected at a depth of 0.1 μm or more.