JP3803631B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP3803631B2
JP3803631B2 JP2002323493A JP2002323493A JP3803631B2 JP 3803631 B2 JP3803631 B2 JP 3803631B2 JP 2002323493 A JP2002323493 A JP 2002323493A JP 2002323493 A JP2002323493 A JP 2002323493A JP 3803631 B2 JP3803631 B2 JP 3803631B2
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Japan
Prior art keywords
contact hole
film
silicide layer
impurity diffusion
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2002323493A
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English (en)
Japanese (ja)
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JP2004158663A (ja
JP2004158663A5 (enExample
Inventor
一明 中嶋
恭一 須黒
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Toshiba Corp
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Toshiba Corp
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Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2002323493A priority Critical patent/JP3803631B2/ja
Priority to US10/701,435 priority patent/US7354819B2/en
Publication of JP2004158663A publication Critical patent/JP2004158663A/ja
Publication of JP2004158663A5 publication Critical patent/JP2004158663A5/ja
Application granted granted Critical
Publication of JP3803631B2 publication Critical patent/JP3803631B2/ja
Priority to US12/071,887 priority patent/US7667274B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2002323493A 2002-11-07 2002-11-07 半導体装置及びその製造方法 Expired - Fee Related JP3803631B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2002323493A JP3803631B2 (ja) 2002-11-07 2002-11-07 半導体装置及びその製造方法
US10/701,435 US7354819B2 (en) 2002-11-07 2003-11-06 Method of manufacturing CMOS with silicide contacts
US12/071,887 US7667274B2 (en) 2002-11-07 2008-02-27 Semiconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002323493A JP3803631B2 (ja) 2002-11-07 2002-11-07 半導体装置及びその製造方法

Publications (3)

Publication Number Publication Date
JP2004158663A JP2004158663A (ja) 2004-06-03
JP2004158663A5 JP2004158663A5 (enExample) 2005-03-03
JP3803631B2 true JP3803631B2 (ja) 2006-08-02

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ID=32697454

Family Applications (1)

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JP2002323493A Expired - Fee Related JP3803631B2 (ja) 2002-11-07 2002-11-07 半導体装置及びその製造方法

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US (2) US7354819B2 (enExample)
JP (1) JP3803631B2 (enExample)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7405112B2 (en) * 2000-08-25 2008-07-29 Advanced Micro Devices, Inc. Low contact resistance CMOS circuits and methods for their fabrication
JP4237161B2 (ja) * 2005-05-09 2009-03-11 エルピーダメモリ株式会社 半導体装置の製造方法
US7749877B2 (en) * 2006-03-07 2010-07-06 Siliconix Technology C. V. Process for forming Schottky rectifier with PtNi silicide Schottky barrier
JP4534164B2 (ja) * 2006-07-25 2010-09-01 エルピーダメモリ株式会社 半導体装置の製造方法
DE102006040764B4 (de) * 2006-08-31 2010-11-11 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement mit einem lokal vorgesehenem Metallsilizidgebiet in Kontaktbereichen und Herstellung desselben
US7768074B2 (en) * 2008-12-31 2010-08-03 Intel Corporation Dual salicide integration for salicide through trench contacts and structures formed thereby
DE102010004230A1 (de) 2009-01-23 2010-10-14 Qimonda Ag Integrierter Schaltkreis mit Kontaktstrukturen für P- und N-Dotierte Gebiete und Verfahren zu dessen Herstellung
CN103000675B (zh) * 2011-09-08 2015-11-25 中国科学院微电子研究所 低源漏接触电阻mosfets及其制造方法
DE112011105702T5 (de) * 2011-10-01 2014-07-17 Intel Corporation Source-/Drain-Kontakte für nicht planare Transistoren
JP5981711B2 (ja) * 2011-12-16 2016-08-31 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
JP6113500B2 (ja) * 2012-12-27 2017-04-12 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
KR20140101218A (ko) 2013-02-08 2014-08-19 삼성전자주식회사 반도체 소자 및 그 제조 방법
KR102061265B1 (ko) 2013-07-23 2019-12-31 삼성전자주식회사 반도체 장치 및 그 제조방법
US20150372100A1 (en) * 2014-06-19 2015-12-24 GlobalFoundries, Inc. Integrated circuits having improved contacts and methods for fabricating same
KR102231205B1 (ko) 2014-11-19 2021-03-25 삼성전자주식회사 반도체 장치 및 그 제조 방법
CN105762106B (zh) * 2014-12-18 2021-02-19 联华电子股份有限公司 半导体装置及其制作工艺
US9748281B1 (en) * 2016-09-15 2017-08-29 International Business Machines Corporation Integrated gate driver

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2859288B2 (ja) * 1989-03-20 1999-02-17 株式会社日立製作所 半導体集積回路装置及びその製造方法
JP3246189B2 (ja) * 1994-06-28 2002-01-15 株式会社日立製作所 半導体表示装置
JPH11214650A (ja) 1998-01-23 1999-08-06 Toshiba Corp 半導体装置及びその製造方法
JP2000286411A (ja) 1999-03-29 2000-10-13 Toshiba Corp 半導体装置とその製造方法
JP2001250792A (ja) 2000-03-06 2001-09-14 Hitachi Ltd 半導体集積回路装置の製造方法
US6465887B1 (en) * 2000-05-03 2002-10-15 The United States Of America As Represented By The Secretary Of The Navy Electronic devices with diffusion barrier and process for making same
JP3833903B2 (ja) 2000-07-11 2006-10-18 株式会社東芝 半導体装置の製造方法
US7405112B2 (en) * 2000-08-25 2008-07-29 Advanced Micro Devices, Inc. Low contact resistance CMOS circuits and methods for their fabrication
JP2002198325A (ja) 2000-12-26 2002-07-12 Toshiba Corp 半導体装置およびその製造方法
DE10208904B4 (de) * 2002-02-28 2007-03-01 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung unterschiedlicher Silicidbereiche auf verschiedenen Silicium enthaltenden Gebieten in einem Halbleiterelement
US7112483B2 (en) * 2003-08-29 2006-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming a device having multiple silicide types

Also Published As

Publication number Publication date
US20080157214A1 (en) 2008-07-03
JP2004158663A (ja) 2004-06-03
US7354819B2 (en) 2008-04-08
US7667274B2 (en) 2010-02-23
US20040142567A1 (en) 2004-07-22

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