JP3690723B2 - 回路基板、回路基板の中間体およびそれらの製造方法 - Google Patents

回路基板、回路基板の中間体およびそれらの製造方法 Download PDF

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Publication number
JP3690723B2
JP3690723B2 JP2000025957A JP2000025957A JP3690723B2 JP 3690723 B2 JP3690723 B2 JP 3690723B2 JP 2000025957 A JP2000025957 A JP 2000025957A JP 2000025957 A JP2000025957 A JP 2000025957A JP 3690723 B2 JP3690723 B2 JP 3690723B2
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Japan
Prior art keywords
hole
circuit board
conductor
adhesive layer
base material
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Expired - Lifetime
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JP2000025957A
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Japanese (ja)
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JP2001217547A5 (enExample
JP2001217547A (ja
Inventor
秀樹 東谷
俊夫 須川
禎志 中村
大蔵 安藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
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Priority to JP2000025957A priority Critical patent/JP3690723B2/ja
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Publication of JP2001217547A5 publication Critical patent/JP2001217547A5/ja
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Expired - Lifetime legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
JP2000025957A 2000-02-03 2000-02-03 回路基板、回路基板の中間体およびそれらの製造方法 Expired - Lifetime JP3690723B2 (ja)

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JP2000025957A JP3690723B2 (ja) 2000-02-03 2000-02-03 回路基板、回路基板の中間体およびそれらの製造方法

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JP2000025957A JP3690723B2 (ja) 2000-02-03 2000-02-03 回路基板、回路基板の中間体およびそれらの製造方法

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JP2001217547A JP2001217547A (ja) 2001-08-10
JP2001217547A5 JP2001217547A5 (enExample) 2005-07-28
JP3690723B2 true JP3690723B2 (ja) 2005-08-31

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101829316B1 (ko) * 2016-12-22 2018-02-14 제이앤케이티(주) 솔더링 방식을 이용한 인쇄회로기판 제조 방법

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5083906B2 (ja) * 2008-10-30 2012-11-28 京セラＳｌｃテクノロジー株式会社 配線基板の製造方法
CN115379669B (zh) * 2021-05-20 2025-11-14 鹏鼎控股(深圳)股份有限公司 多层线路板及其制造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101829316B1 (ko) * 2016-12-22 2018-02-14 제이앤케이티(주) 솔더링 방식을 이용한 인쇄회로기판 제조 방법

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JP2001217547A (ja) 2001-08-10

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