JP3663343B2 - Package for storing semiconductor elements - Google Patents

Package for storing semiconductor elements Download PDF

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Publication number
JP3663343B2
JP3663343B2 JP2000215007A JP2000215007A JP3663343B2 JP 3663343 B2 JP3663343 B2 JP 3663343B2 JP 2000215007 A JP2000215007 A JP 2000215007A JP 2000215007 A JP2000215007 A JP 2000215007A JP 3663343 B2 JP3663343 B2 JP 3663343B2
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Japan
Prior art keywords
lid
frame
package
main surface
semiconductor element
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JP2000215007A
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JP2002033408A (en
Inventor
義明 植田
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Kyocera Corp
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Kyocera Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

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  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
  • Casings For Electric Apparatus (AREA)

Description

【0001】
【発明の属する技術分野】
本発明は半導体素子収納用パッケージに関し、特に半導体素子収納用パッケージ内に半導体素子を封止するために溶接される金属製の蓋体の取着構造の改良に関するものである。
【0002】
【従来の技術】
従来、電界効果型トランジスターやパワートランジスターあるいはMMIC(Monolithic Microwave IC)などの高周波で作動する半導体素子等を収容する半導体素子収納用パッケージ(以下、半導体パッケージとする)には、図6に示すように、酸化アルミニウム質焼結体などの電気絶縁材料からなる基体1と、基体1の上面に半導体素子4の載置部を囲むようにしてロウ材を介して取着され、鉄(Fe)−ニッケル(Ni)−コバルト(Co)合金や、鉄(Fe)−ニッケル(Ni)合金等の合金からなるとともに、メタライズ配線層7が形成されたセラミック入出力端子6を予め側部に設けられた切り欠きまたは貫通孔に嵌着させた金属製の枠体2と、この枠体2の上面に接合されるFe−Ni−Co合金等からなる金属製の蓋体3とから成る半導体パッケージが提案されている(特開平11−126837号公報参照)。
【0003】
上記半導体パッケージの内部に半導体素子4を収容するとともに、半導体素子4の各電極をボンディングワイヤ11を介して入出力端子6のメタライズ配線層7に接続し、しかる後、枠体2の上面に金属製の蓋体3をシーム溶接法により溶接し、基体1と枠体2と蓋体3とからなる容器内に半導体素子4を収容し気密に封止することによって、最終製品としての電子装置となる。このような図6のものと同様の構成の光半導体モジュールとして、金属製の枠体上面に金属製の気密キャップがシーム溶接により接合されているものも知られている(特開平8−94888号公報参照)。
【0004】
上記のシーム溶接法は、図5に示すように、円錐台状のローラー電極10の斜面部を蓋体3の上面の周縁に当接させながら転がし、ローラー電極10を介して電流を蓋体3から枠体2へと流し、この時ローラー電極10直下の蓋体3と枠体2との当接部に発生するジュール熱によって、その当接部に予め形成されているNiメッキ層等を溶融させ、再び固化させて接合層となすことにより、蓋体3を枠体2に溶接する方法である。このシーム溶接法では、蓋体3の全周を溶接する際に発生する熱はローラー電極10の接触部近辺に限られ、またその熱は枠体2を介して基体1側へと速やかに伝達される。その結果、半導体パッケージ内に載置している半導体素子4に熱破壊等を発生させることがないので、近年多用されている蓋体3の接合方法である。
【0005】
また金属製の蓋体3は、その両主面がロール圧延等の成形方法により比較的平滑な表面性状とされている。また、特開平8−94888号公報に示されているように、枠体2の上面に接合される側の蓋体3の主面の周縁部はエッチングによって薄肉部9を形成している。
【0006】
そして、蓋体3の周縁部に薄肉部9を形成するのは、図5に示すように、蓋体3の周縁部の面方向(X方向)から見た断面の断面積を減少させることにより、蓋体3の周縁部の面方向の電気抵抗を大きくしてローラー電極10から蓋体3の主面の中心側に流れる電流を少なくするとともに、蓋体3の周縁部のX方向に垂直な方向Y(主面に垂直な方向)から見た断面の断面積を、X方向における断面積の数倍以上とし得ることから電気抵抗を小さくすることができ、よってローラー電極10から電気抵抗が小さい枠体2の方向(下方)に流れる電流を大きくできる為である。これにより、蓋体3と枠体2との当接部に大きなジュール熱を発生させ得る。また蓋体3の周縁部に薄肉部が形成されたことで、段差が形成され、蓋体3の枠体2への位置合わせにも役立つといったものも提案されている(特開平8−274208号公報参照)。
【0007】
【発明が解決しようとする課題】
しかしながら、前述のように蓋体3を枠体2に効率よく溶接するために蓋体3の周縁部に薄肉部9を形成しているのであるが、シーム溶接時に一旦溶融し固化した接合層8中にボイドが発生して、かかるボイドにより蓋体3の接合強度が低下する、また半導体パッケージの気密性が劣化するなどの不具合が発生していた。これは、エッチングにより薄肉化された蓋体3の周縁部の表面の凹凸が大きいため、溶融したNiの流れが阻害され、蓋体3と枠体2との当接部に均一かつ密に行きわたらず、その結果接合層8にボイドが発生することによると考えられる。
【0008】
従って、本発明は上記の問題点に鑑みて完成されたものであり、その目的は、蓋体3を枠体2の上面に接合する際に、接合層8におけるボイドの発生を抑え、またその接合強度を向上させることにより、長期間に亘って正常に作動する半導体パッケージを提供することである。
【0009】
【課題を解決するための手段】
本発明の半導体素子収納用パッケージは、上面に半導体素子を載置する載置部を有する基体と、前記載置部を囲繞するように前記上面に接合された枠体と、該枠体の上面に一方主面の周縁部が接合される金属製の蓋体とを具備した半導体素子収納用パッケージにおいて、前記蓋体は、他方主面の周縁部をエッチングにより薄肉化して算術平均粗さRaを3.0乃至6.3μmとするとともに、前記一方主面の周縁部の算術平均粗さRa3.0μm未満としてあり、前記一方主面の周縁部を前記枠体の上面にシーム溶接により接合せしめたことを特徴とする。
【0010】
本発明は、上記の構成により、蓋体を枠体にシーム溶接法で接合する際に、蓋体と枠体との接合部で溶融したNiメッキ層等の接合材の流れが阻害されることがなく、蓋体と枠体との接合部に均一かつ密に行きわたるので、ボイドの発生を大幅に抑制し得るという作用効果を有する。
【0011】
【発明の実施の形態】
本発明の半導体パッケージを添付図面に基づき以下に詳細に説明する。図1及び図2は本発明の半導体パッケージの一実施形態を示し、1は基体、2は金属,セラミックス等から成る枠体、3は金属製の蓋体、5は半導体素子4の載置部、6は入出力端子である。かかる基体1と、枠体2と、蓋体3とによって半導体素子4を収納するための容器が構成される。なお、図1、図2において、従来例を示す図6と同じ部分には同じ符号を付した。
【0012】
基体1は、銅(Cu)やFe−Ni−Co合金、Cu−W合金等の金属材料からなり、例えば、銅からなる場合には銅のインゴット(塊)に圧延加工法、プレス成型法、打ち抜き加工法等の従来周知の金属加工法を採用することによって所定の形状に形成される。
【0013】
また、枠体2は、例えばFe−Ni−Co合金、Fe−Ni合金等からなり、このような金属材料の粉末を混合して加熱溶解させたものをシート状部材となし、これをロール圧延法にて所定の厚さに圧延し、得られたシート状部材を従来周知の絞り加工法にてパイプ状部材とする。このようにして得られたパイプ状部材を、従来周知の引き抜き加工法により段階的に加工して所望の矩形状の断面形状を有するパイプを得る。このパイプを適宜の長さに切断することによって、所望の大きさ及び形状の枠体2が作製される。
【0014】
この枠体2は、基体1の上面に半導体素子4の載置部5を囲繞するようにして銀ロウなどのロウ材を介して接合される。このとき、入出力端子6は、従来周知のセラミックグリーンシート積層法によって別途作製され、上面に枠体2の内外を導出するメタライズ配線層7が形成された平板部上に立壁部を積層させた構成である。そして、この入出力端子6は枠体2に設けた切り欠きまたは貫通孔に銀ロウなどのロウ材を介して嵌着される。その後、基体1と枠体2の全面及び入出力端子6の表面に形成されたメタライズ配線層7の表面にNiメッキが施される。
【0015】
また、金属製の枠体2に代えてセラミックス製のものを用いても良く、その場合、例えば酸化アルミニウム(Al23)の粉末と、焼結助材としてのシリカ(SiO2)、カルシア(CaO)、マグネシア(MgO)などの粉末と、適当なバインダー及び溶剤とを混合してこれをスラリー状となし、次いで従来周知のドクターブレード法などのテープ成形法によって所定厚みのセラミックグリーンシートに成形し、このセラミックグリーンシートを複数枚準備する。ついで、セラミックグリーンシートに打ち抜き加工を施すとともに、枠体2及び基体1と接合される所定の部位にメタライズ層を、入出力端子部にメタライズ配線層を、また図には示していないがシーム溶接時に導電路となるメタライズ配線層を形成し、この後セラミックスグリーンシートを積層し、1600℃程度の温度で焼成してセラミック枠体2が得られる。
【0016】
そして、図4に示すように、この枠体2の上面にFe−Ni−Co合金、Fe−Ni合金等からな蓋体3の周縁部をシーム溶接するが、この周縁部を薄くすることにより以下のような作用が生じる。即ち、蓋体3の周縁部の面方向(X方向)から見た断面の断面積を減少させることにより、蓋体3の周縁部の面方向の電気抵抗を大きくしてローラー電極10から蓋体3の主面の中心側に流れる電流を少なくする。また、蓋体3の周縁部のX方向に垂直な方向Y(主面に垂直な方向)から見た断面の断面積を、X方向における断面積の数倍以上とし得ることから、電気抵抗を小さくすることができる。よって、ローラー電極10から電気抵抗が小さい枠体2の方向(下方)に流れる電流を大きくし、蓋体3と枠体2との当接部に大きなジュール熱を発生させ得る。
【0017】
本発明において、金属製の蓋体3は、一方主面Aの周縁部9の算術平均粗さRaが3.0μm未満であるが、3.0μm以上になると、枠体2の上面に接合される一方主面Aの周縁部と枠体2の上面との接触面積が小さくなって電気抵抗が大きくなり、流れる電流が小さくなり、シーム溶接時に蓋体3と枠体2との接合部の加熱が不十分となり接合が困難となる。
【0018】
また、金属製の蓋体3の両主面は、当初例えばロール圧延法によって成型されており、圧延ロール表面のRaは最も平滑なもので0.3μm程度である。この圧延ロールの表面が蓋体3の主面にほぼそのまま転写されるので、一方主面Aの周縁部のRaは実際上約0.3μm以上3.0μm未満となる。したがって、一方主面Aの周縁部のRaは0.3μm以上3.0μm未満が好ましい。また、このことから、他方主面(上面)Bの周縁部を除く両主面のRaは0.3μm以上3.0μm未満が好適である。
【0019】
この蓋体3の一方主面(下面)Aはエッチングなどの表面処理が施されず、一方、他方主面(上面)Bの周縁部はX方向から見た断面の断面積を減少させるためにエッチングされて薄肉化される。この薄肉部では、蓋体3の面方向の電流の流れが抑制される。エッチングされて得られた他方主面Bの周縁部9は3.0〜6.3μm程度の算術平均粗さRaを有しているので、枠体2の上面への接合に際してはこの他方主面Bを上側にし、一方主面Aを接合面側として枠体2の上面にシーム溶接する。
【0020】
また薄肉部9の厚みは0.05〜0.15mmがよく、0.05mm以下では、薄肉部9の一部がシーム溶接時に溶融して消失したり、欠けが生じ易くなる。また薄肉部9の厚みが0.15mm以上になると、蓋体3の面方向(X方向)での電気抵抗が小さくなって大きな電流がこの方向に流れ、蓋体3全体がジュール熱によって加熱され、薄肉部9の加熱が不足する傾向にある。
【0021】
この蓋体3の厚さは0.1〜0.3mm程度であり、よって薄肉部9は蓋体3の厚さの17〜50%程度の厚さがよい。17%未満では、薄肉部9の一部がシーム溶接時に溶融して消失したり、欠けが生じ易くなるという点で不適である。50%を超えると、蓋体3の面方向(X方向)での電気抵抗が小さくなって大きな電流がこの方向に流れ、蓋体3全体がジュール熱によって加熱され、薄肉部9の加熱が不足する傾向にある。
【0022】
また薄肉部9の幅は0.1〜1.5mmがよく、0.1mm以下では蓋体3の面方向の電気抵抗が小さくなり、よって面方向に大きな電流が流れ易くなる。また、薄肉部9の幅が1.5mm以上になると、蓋体3の強度が薄肉部9で低下し、半導体パッケージの気密性をテストするHeリークテストの際に薄肉部9が変形するという問題が発生し易い。
【0023】
かくして、基体1と枠体2とで構成された容器内に半導体素子4を収容し、しかる後半導体素子4上の各電極と入出力端子6上のメタライズ配線層7とをボンディングワイヤ11によって電気的に接続し、最後に蓋体3によって半導体素子4が気密に封止されて半導体装置となる。
【0024】
ところで、従来例では、エッチングにより形成された薄肉部9の段差がシーム溶接の際の蓋体3の位置合わせにも役立つとされているが、エッチングの位置ずれなども生じやすいため、シーム溶接において段差による位置合わせを行うことは実用性に乏しい。したがって、段差が設けられていない一方主面Aを接合面とすることに不具合はほとんどない。
【0025】
なお、本発明は上記実施形態に限定されるものではなく、本発明の要旨を逸脱しない範囲において種々の変更を行うことは何ら差し支えない。例えば、図3に示すように、入出力端子6をセラミックスから成る平板状のものとし、セラミックスから成る枠体2の下面の切り欠きに嵌着させる構成としてもよく、この場合入出力端子6に立壁部がない分半導体パッケージが薄型化される。
【0026】
【発明の効果】
本発明の半導体素子収納用パッケージによれば、上面に半導体素子を載置する載置部を有する基体と、載置部を囲繞するように上面に接合された枠体と、枠体の上面に一方主面の周縁部が接合される金属製の蓋体とを具備しており、蓋体は、他方主面の周縁部をエッチングにより薄肉化して算術平均粗さRaを3.0乃至6.3μmとするとともに、一方主面の周縁部の算術平均粗さRa3.0μm未満としてあり、一方主面の周縁部を枠体の上面にシーム溶接により接合せしめたことにより、シーム溶接の際の接合部におけるNiメッキ等の接合材の流れが阻害されることがなく、蓋体と枠体との当接部に均一かつ密に行きわたるので、接合部に発生するボイドを大幅に抑制することが出来る。その結果、蓋体の接合強度が低下することがなく、また半導体パッケージ内部の気密性が劣化することがない。さらに、シーム溶接時の電流を大部分蓋体の周縁部から下方の枠体へと効率よく流すことができるため、電流の大きさを小さく出来るとともに、蓋体の全周における均一な溶接を可能とし、また溶接時間の短縮が可能となり、半導体パッケージを低コストに製造することが出来る。
【図面の簡単な説明】
【図1】本発明の半導体素子収納用パッケージの一実施形態の断面図である。
【図2】図1の半導体素子収納用パッケージの要部の部分断面図である。
【図3】本発明の半導体素子収納用パッケージの他の実施形態の断面図である。
【図4】本発明の半導体素子収納用パッケージにおける枠体と蓋体のシーム溶接を説明するものであり、ローラー電極と半導体素子収納用パッケージの溶接部を示す部分断面図である。
【図5】従来の半導体素子収納用パッケージにおける枠体と蓋体のシーム溶接を説明するものであり、ローラー電極と半導体素子収納用パッケージの溶接部を示す部分断面図である。
【図6】従来の半導体素子収納用パッケージの断面図である。
【符号の説明】
1・・・基体
2・・・枠体
3・・・金属製の蓋体
4・・・半導体素子
5・・・載置部
6・・・入出力端子
7・・・メタライズ配線層
8・・・接合層
9・・・薄肉部
10・・・ローラー電極
11・・・ボンディングワイヤ
A・・・一方主面
B・・・他方主面
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a package for housing semiconductor elements, and more particularly to an improvement in the attachment structure of a metal lid welded to seal a semiconductor element in the package for housing semiconductor elements.
[0002]
[Prior art]
Conventionally, a semiconductor element storage package (hereinafter referred to as a semiconductor package) that contains a semiconductor element that operates at a high frequency such as a field effect transistor, a power transistor, or an MMIC (Monolithic Microwave IC), as shown in FIG. The base 1 made of an electrically insulating material such as an aluminum oxide sintered body, and the upper surface of the base 1 is attached via a brazing material so as to surround the mounting portion of the semiconductor element 4, and iron (Fe) -nickel (Ni ) -Cobalt (Co) alloy, iron (Fe) -nickel (Ni) alloy, and the like, and the ceramic input / output terminal 6 on which the metallized wiring layer 7 is formed is notched or provided in advance on the side. A metal frame 2 fitted in the through hole and a metal lid 3 made of Fe-Ni-Co alloy or the like joined to the upper surface of the frame 2 are formed. The semiconductor package has been proposed (see Japanese Patent Laid-Open No. 11-126837).
[0003]
The semiconductor element 4 is accommodated in the semiconductor package, and each electrode of the semiconductor element 4 is connected to the metallized wiring layer 7 of the input / output terminal 6 through the bonding wires 11. An electronic device as a final product is obtained by welding a manufactured lid 3 by a seam welding method, housing a semiconductor element 4 in a container composed of a base body 1, a frame body 2 and a lid body 3 and sealing hermetically. Become. As an optical semiconductor module having the same configuration as that shown in FIG. 6, there is also known an optical semiconductor module in which a metal hermetic cap is joined to the upper surface of a metal frame by seam welding (Japanese Patent Laid-Open No. 8-94888). See the official gazette).
[0004]
As shown in FIG. 5, the above seam welding method rolls the truncated cone-shaped roller electrode 10 while abutting the inclined surface of the frustoconical roller electrode 10 against the peripheral edge of the upper surface of the lid 3, and current is passed through the roller electrode 10 to the lid 3. The Ni plating layer or the like formed in advance on the contact portion is melted by Joule heat generated at the contact portion between the lid 3 and the frame body 2 immediately below the roller electrode 10 at this time. In this method, the lid 3 is welded to the frame 2 by solidifying again to form a bonding layer. In this seam welding method, the heat generated when welding the entire circumference of the lid 3 is limited to the vicinity of the contact portion of the roller electrode 10, and the heat is quickly transferred to the base 1 side through the frame 2. Is done. As a result, the semiconductor element 4 placed in the semiconductor package does not cause thermal destruction or the like, and this is a method of joining the lid 3 that has been widely used in recent years.
[0005]
Further, the metal lid 3 has a relatively smooth surface property on both main surfaces by a forming method such as roll rolling. Further, as disclosed in Japanese Patent Laid-Open No. 8-94888, the peripheral portion of the main surface of the lid 3 on the side joined to the upper surface of the frame 2 forms a thin portion 9 by etching.
[0006]
And the thin part 9 is formed in the peripheral part of the cover 3 by reducing the cross-sectional area of the cross section seen from the surface direction (X direction) of the peripheral part of the cover 3, as shown in FIG. The electrical resistance in the surface direction of the peripheral portion of the lid body 3 is increased to reduce the current flowing from the roller electrode 10 to the center side of the main surface of the lid body 3, and perpendicular to the X direction of the peripheral edge portion of the lid body 3. Since the cross-sectional area of the cross section viewed from the direction Y (perpendicular to the main surface) can be several times the cross-sectional area in the X direction, the electric resistance can be reduced, and thus the electric resistance from the roller electrode 10 is small. This is because the current flowing in the direction of the frame 2 (downward) can be increased. Thereby, a large Joule heat can be generated at the contact portion between the lid 3 and the frame 2. In addition, there has also been proposed a thin-walled portion formed on the peripheral portion of the lid 3 so that a step is formed and is useful for alignment of the lid 3 with the frame 2 (Japanese Patent Laid-Open No. 8-274208). See the official gazette).
[0007]
[Problems to be solved by the invention]
However, as described above, in order to efficiently weld the lid 3 to the frame 2, the thin-walled portion 9 is formed on the peripheral edge of the lid 3, but the bonding layer 8 is once melted and solidified during seam welding. A void has occurred in the inside, and such a void has caused problems such as a decrease in the bonding strength of the lid 3 and a deterioration in the airtightness of the semiconductor package. This is because the unevenness of the surface of the peripheral portion of the lid 3 thinned by etching is large, so that the flow of molten Ni is hindered and goes to the contact portion between the lid 3 and the frame 2 uniformly and densely. It is considered that voids are generated in the bonding layer 8 as a result.
[0008]
Accordingly, the present invention has been completed in view of the above-described problems, and its purpose is to suppress the generation of voids in the bonding layer 8 when the lid body 3 is bonded to the upper surface of the frame body 2. It is an object of the present invention to provide a semiconductor package that operates normally over a long period of time by improving the bonding strength.
[0009]
[Means for Solving the Problems]
A package for housing a semiconductor element according to the present invention includes a base body having a mounting portion for mounting a semiconductor element on an upper surface, a frame body joined to the upper surface so as to surround the mounting portion, and an upper surface of the frame body the semiconductor device package for housing the peripheral portion is provided with a metal lid to be bonded of the hand main surface, wherein the lid has an arithmetic mean roughness Ra of the peripheral portion of the other main surface by thinning by etching 3.0 to with a 6.3 [mu] m, the one Ri arithmetic mean roughness Ra of the peripheral portion of the main surface is less than 3.0μm Thea, seam welding the peripheral portion of the one main surface to the upper surface of the frame It is characterized by having been joined by.
[0010]
According to the present invention, when the lid is joined to the frame by the seam welding method, the flow of the bonding material such as the Ni plating layer melted at the joint between the lid and the frame is inhibited. There is no problem, and the joints between the lid and the frame are uniformly and densely distributed, so that it is possible to greatly suppress the generation of voids.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
The semiconductor package of the present invention will be described in detail below with reference to the accompanying drawings. 1 and 2 show an embodiment of a semiconductor package of the present invention, wherein 1 is a base, 2 is a frame made of metal, ceramics, etc., 3 is a metal lid, and 5 is a mounting portion for the semiconductor element 4. , 6 are input / output terminals. The base body 1, the frame body 2, and the lid body 3 constitute a container for housing the semiconductor element 4. 1 and 2, the same reference numerals are given to the same portions as FIG. 6 showing the conventional example.
[0012]
The substrate 1 is made of a metal material such as copper (Cu), an Fe—Ni—Co alloy, or a Cu—W alloy. For example, in the case of copper, a rolling process, a press molding method, It is formed in a predetermined shape by employing a conventionally known metal processing method such as a punching method.
[0013]
The frame 2 is made of, for example, an Fe—Ni—Co alloy, an Fe—Ni alloy, or the like, and is a sheet-like member obtained by mixing and melting such a metal material powder. The sheet-like member obtained by rolling to a predetermined thickness is formed into a pipe-like member by a conventionally known drawing method. The pipe-shaped member thus obtained is processed stepwise by a conventionally known drawing method to obtain a pipe having a desired rectangular cross-sectional shape. The frame 2 having a desired size and shape is produced by cutting the pipe into an appropriate length.
[0014]
The frame 2 is joined to the upper surface of the base 1 via a brazing material such as silver brazing so as to surround the mounting portion 5 of the semiconductor element 4. At this time, the input / output terminal 6 is separately manufactured by a conventionally known ceramic green sheet laminating method, and the standing wall portion is laminated on the flat plate portion on which the metallized wiring layer 7 leading out the inside and outside of the frame body 2 is formed on the upper surface. It is a configuration. The input / output terminal 6 is fitted into a notch or a through hole provided in the frame 2 via a brazing material such as silver brazing. Thereafter, Ni plating is applied to the entire surface of the substrate 1 and the frame 2 and the surface of the metallized wiring layer 7 formed on the surface of the input / output terminal 6.
[0015]
Further, instead of the metal frame 2, a ceramic one may be used. In this case, for example, aluminum oxide (Al 2 O 3 ) powder, silica (SiO 2 ) as a sintering aid, calcia. (CaO), magnesia (MgO), etc., and a suitable binder and solvent are mixed to form a slurry, which is then formed into a ceramic green sheet of a predetermined thickness by a tape forming method such as a conventionally known doctor blade method. A plurality of ceramic green sheets are prepared. Next, the ceramic green sheet is punched, a metallized layer is formed at a predetermined portion to be joined to the frame 2 and the base 1, a metallized wiring layer is formed at the input / output terminal portion, and seam welding is not shown in the figure. A metallized wiring layer that sometimes becomes a conductive path is formed, and then a ceramic green sheet is laminated and fired at a temperature of about 1600 ° C. to obtain the ceramic frame 2.
[0016]
Then, as shown in FIG. 4, the peripheral portion of the lid 3 made of Fe-Ni-Co alloy, Fe-Ni alloy, or the like is seam welded to the upper surface of the frame 2, and the peripheral portion is thinned. The following effects occur. That is, by reducing the cross-sectional area of the cross section viewed from the surface direction (X direction) of the peripheral portion of the lid 3, the electrical resistance in the surface direction of the peripheral portion of the lid 3 is increased, and the lid from the roller electrode 10. 3 to reduce the current flowing to the center side of the main surface. In addition, since the cross-sectional area of the cross section viewed from the direction Y (perpendicular to the main surface) perpendicular to the X direction of the peripheral portion of the lid body 3 can be several times the cross-sectional area in the X direction, the electrical resistance can be reduced. Can be small. Therefore, the current flowing from the roller electrode 10 in the direction (downward) of the frame 2 having a small electric resistance can be increased, and a large Joule heat can be generated at the contact portion between the lid 3 and the frame 2.
[0017]
In the present invention, the metal lid 3 is joined to the upper surface of the frame 2 when the arithmetic average roughness Ra of the peripheral edge 9 of the main surface A is less than 3.0 μm. On the other hand, the contact area between the peripheral edge portion of the main surface A and the upper surface of the frame body 2 is reduced, the electrical resistance is increased, the flowing current is reduced, and the joined portion between the lid 3 and the frame body 2 is heated during seam welding. Becomes insufficient and joining becomes difficult.
[0018]
Further, both main surfaces of the metallic lid 3 are initially formed by, for example, a roll rolling method, and the Ra of the rolling roll surface is the smoothest and is about 0.3 μm. Since the surface of the rolling roll is transferred almost as it is to the main surface of the lid 3, the Ra at the peripheral portion of the main surface A is actually about 0.3 μm or more and less than 3.0 μm. Therefore, Ra of the peripheral part of one main surface A is preferably 0.3 μm or more and less than 3.0 μm. From this, Ra of both main surfaces excluding the peripheral portion of the other main surface (upper surface) B is preferably 0.3 μm or more and less than 3.0 μm.
[0019]
One main surface (lower surface) A of the lid 3 is not subjected to surface treatment such as etching, while the peripheral portion of the other main surface (upper surface) B is to reduce the cross-sectional area of the cross section viewed from the X direction. It is etched and thinned. In this thin portion, the flow of current in the surface direction of the lid 3 is suppressed. Since the peripheral edge portion 9 of the other main surface B obtained by etching has an arithmetic average roughness Ra of about 3.0 to 6.3 μm, the other main surface is used for bonding to the upper surface of the frame 2. Seam welding is performed on the upper surface of the frame body 2 with B on the upper side and the main surface A on the joining surface side.
[0020]
Further, the thickness of the thin portion 9 is preferably 0.05 to 0.15 mm. When the thickness is 0.05 mm or less, a part of the thin portion 9 is melted and disappears during seam welding, or chipping is likely to occur. When the thickness of the thin wall portion 9 is 0.15 mm or more, the electrical resistance in the surface direction (X direction) of the lid body 3 is reduced and a large current flows in this direction, and the entire lid body 3 is heated by Joule heat. The heating of the thin portion 9 tends to be insufficient.
[0021]
The thickness of the lid 3 is about 0.1 to 0.3 mm. Therefore, the thin portion 9 is preferably about 17 to 50% of the thickness of the lid 3. If it is less than 17%, a part of the thin-walled portion 9 is unsuitable in that it melts and disappears during seam welding, or chipping easily occurs. If it exceeds 50%, the electrical resistance in the surface direction (X direction) of the lid 3 is reduced, a large current flows in this direction, the entire lid 3 is heated by Joule heat, and heating of the thin portion 9 is insufficient. Tend to.
[0022]
Further, the width of the thin portion 9 is preferably 0.1 to 1.5 mm, and if it is 0.1 mm or less, the electrical resistance in the surface direction of the lid 3 is reduced, and thus a large current is likely to flow in the surface direction. Further, when the width of the thin portion 9 is 1.5 mm or more, the strength of the lid 3 is reduced at the thin portion 9 and the thin portion 9 is deformed during the He leak test for testing the airtightness of the semiconductor package. Is likely to occur.
[0023]
Thus, the semiconductor element 4 is accommodated in a container constituted by the base 1 and the frame 2, and then each electrode on the semiconductor element 4 and the metallized wiring layer 7 on the input / output terminal 6 are electrically connected by the bonding wires 11. Finally, the semiconductor element 4 is hermetically sealed by the lid 3 to form a semiconductor device.
[0024]
By the way, in the conventional example, the step of the thin portion 9 formed by etching is said to be useful for alignment of the lid 3 at the time of seam welding. It is not practical to perform alignment by steps. Therefore, there is almost no problem in using the main surface A on which the step is not provided as the joining surface.
[0025]
The present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the present invention. For example, as shown in FIG. 3, the input / output terminal 6 may be a flat plate made of ceramics, and may be fitted into a notch on the lower surface of the frame 2 made of ceramics. The semiconductor package is made thinner by the absence of the standing wall.
[0026]
【The invention's effect】
According to the semiconductor device housing package of the present invention, a substrate having a mounting portion for mounting a semiconductor element on an upper surface, a frame body which is joined to the upper surface so as to surround the mounting portion, the upper surface of the frame has and a metallic lid periphery of hand main surface is joined, the cover is 3.0 to the arithmetic mean roughness Ra of the peripheral portion of the other main surface by thinning by etching 6 with the .3Myuemu, whereas the arithmetic average roughness Ra of the peripheral portion of the main surface Ri Thea is less than 3.0 [mu] m, whereas the periphery of the main surface on the upper surface of the frame by was allowed joined by seam welding, seam welding The flow of the joining material such as Ni plating at the joining portion is not obstructed and the contact portion between the lid body and the frame body is spread uniformly and densely. Can be suppressed. As a result, the bonding strength of the lid does not decrease, and the airtightness inside the semiconductor package does not deteriorate. In addition, most of the current during seam welding can be efficiently flowed from the peripheral edge of the lid to the lower frame, so that the current can be reduced and uniform welding is possible on the entire circumference of the lid. In addition, the welding time can be shortened, and the semiconductor package can be manufactured at low cost.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of an embodiment of a package for housing a semiconductor element of the present invention.
2 is a partial cross-sectional view of a main part of the semiconductor element storage package of FIG. 1;
FIG. 3 is a cross-sectional view of another embodiment of a package for housing a semiconductor element of the present invention.
FIG. 4 is a partial cross-sectional view for explaining seam welding between a frame body and a lid body in a semiconductor element housing package according to the present invention and showing a welded portion between a roller electrode and a semiconductor element housing package.
FIG. 5 is a partial cross-sectional view for explaining seam welding between a frame body and a lid body in a conventional semiconductor element housing package, and showing a welded portion between a roller electrode and a semiconductor element housing package.
FIG. 6 is a cross-sectional view of a conventional package for housing semiconductor elements.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Base | substrate 2 ... Frame 3 ... Metal-made cover body 4 ... Semiconductor element 5 ... Mounting part 6 ... Input / output terminal 7 ... Metallized wiring layer 8 ... -Bonding layer 9 ... thin portion 10 ... roller electrode 11 ... bonding wire A ... one main surface B ... other main surface

Claims (1)

上面に半導体素子を載置する載置部を有する基体と、前記載置部を囲繞するように前記上面に接合された枠体と、該枠体の上面に一方主面の周縁部が接合される金属製の蓋体とを具備した半導体素子収納用パッケージにおいて、前記蓋体は、他方主面の周縁部をエッチングにより薄肉化して算術平均粗さRaを3.0乃至6.3μmとするとともに、前記一方主面の周縁部の算術平均粗さRa3.0μm未満としてあり、前記一方主面の周縁部を前記枠体の上面にシーム溶接により接合せしめたことを特徴とする半導体素子収納用パッケージ。A substrate having a mounting portion for mounting a semiconductor element on an upper surface, a frame body joined to the upper surface so as to surround the placing section, the periphery of the hand main surface on the upper surface of the frame body joined In the package for housing a semiconductor device, the lid body is thinned by etching the peripheral portion of the other main surface so that the arithmetic average roughness Ra is 3.0 to 6.3 μm. together with the semiconductor, characterized in that the one Ri arithmetic mean roughness Ra of the peripheral portion of the main surface is less than 3.0μm tare, and the peripheral portion of the one main surface brought bonded by seam welding the upper surface of the frame Package for element storage.
JP2000215007A 2000-07-14 2000-07-14 Package for storing semiconductor elements Expired - Lifetime JP3663343B2 (en)

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JP4618790B2 (en) * 2005-04-07 2011-01-26 田中貴金属工業株式会社 Hermetic seal cover and method for manufacturing the same
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