JP2002033408A - Package for semiconductor element - Google Patents

Package for semiconductor element

Info

Publication number
JP2002033408A
JP2002033408A JP2000215007A JP2000215007A JP2002033408A JP 2002033408 A JP2002033408 A JP 2002033408A JP 2000215007 A JP2000215007 A JP 2000215007A JP 2000215007 A JP2000215007 A JP 2000215007A JP 2002033408 A JP2002033408 A JP 2002033408A
Authority
JP
Japan
Prior art keywords
lid
frame
semiconductor element
main surface
peripheral portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000215007A
Other languages
Japanese (ja)
Other versions
JP3663343B2 (en
Inventor
Yoshiaki Ueda
義明 植田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2000215007A priority Critical patent/JP3663343B2/en
Publication of JP2002033408A publication Critical patent/JP2002033408A/en
Application granted granted Critical
Publication of JP3663343B2 publication Critical patent/JP3663343B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Landscapes

  • Casings For Electric Apparatus (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent a void from being formed at a joint to lower the joining strength or disable airtight sealing when the peripheral edge of a lid is joined with the top surface of a frame by seam welding. SOLUTION: The mathematical mean roughness Ra of the peripheral edge of one main surface A of the lid 3 is <=3.0 μm, and the peripheral edge of the other main surface B is made thin by etching.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体素子収納用パ
ッケージに関し、特に半導体素子収納用パッケージ内に
半導体素子を封止するために溶接される金属製の蓋体の
取着構造の改良に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package for accommodating a semiconductor element, and more particularly to an improvement in a mounting structure of a metal lid welded to seal a semiconductor element in the package for a semiconductor element. is there.

【0002】[0002]

【従来の技術】従来、電界効果型トランジスターやパワ
ートランジスターあるいはMMIC(Monolithic Micr
owave IC)などの高周波で作動する半導体素子等を
収容する半導体素子収納用パッケージ(以下、半導体パ
ッケージとする)には、図6に示すように、酸化アルミ
ニウム質焼結体などの電気絶縁材料からなる基体1と、
基体1の上面に半導体素子4の載置部を囲むようにして
ロウ材を介して取着され、鉄(Fe)−ニッケル(N
i)−コバルト(Co)合金や、鉄(Fe)−ニッケル
(Ni)合金等の合金からなるとともに、メタライズ配
線層7が形成されたセラミック入出力端子6を予め側部
に設けられた切り欠きまたは貫通孔に嵌着させた金属製
の枠体2と、この枠体2の上面に接合されるFe−Ni
−Co合金等からなる金属製の蓋体3とから成る半導体
パッケージが提案されている(特開平11−12683
7号公報参照)。
2. Description of the Related Art Conventionally, a field-effect transistor, a power transistor or an MMIC (Monolithic Micr) has been used.
As shown in FIG. 6, a semiconductor element housing package (hereinafter, referred to as a semiconductor package) for housing a semiconductor element operating at a high frequency such as an Owave IC) is made of an electrically insulating material such as an aluminum oxide sintered body. A substrate 1 comprising
It is attached to the upper surface of the base 1 through a brazing material so as to surround the mounting portion of the semiconductor element 4 and is made of iron (Fe) -nickel (N
i) Notch made of an alloy such as -cobalt (Co) alloy or iron (Fe) -nickel (Ni) alloy and having a ceramic input / output terminal 6 on which a metallized wiring layer 7 is formed, provided in advance on a side portion Alternatively, a metal frame 2 fitted in the through hole, and Fe-Ni bonded to the upper surface of the frame 2
A semiconductor package comprising a metal lid 3 made of a -Co alloy or the like has been proposed (JP-A-11-12683).
No. 7).

【0003】上記半導体パッケージの内部に半導体素子
4を収容するとともに、半導体素子4の各電極をボンデ
ィングワイヤ11を介して入出力端子6のメタライズ配
線層7に接続し、しかる後、枠体2の上面に金属製の蓋
体3をシーム溶接法により溶接し、基体1と枠体2と蓋
体3とからなる容器内に半導体素子4を収容し気密に封
止することによって、最終製品としての電子装置とな
る。このような図6のものと同様の構成の光半導体モジ
ュールとして、金属製の枠体上面に金属製の気密キャッ
プがシーム溶接により接合されているものも知られてい
る(特開平8−94888号公報参照)。
The semiconductor element 4 is accommodated in the semiconductor package, and each electrode of the semiconductor element 4 is connected to the metallized wiring layer 7 of the input / output terminal 6 via the bonding wire 11. A metal lid 3 is welded to the upper surface by a seam welding method, and the semiconductor element 4 is accommodated in a container formed of the base 1, the frame 2, and the lid 3 and hermetically sealed, so that a final product is obtained. Become an electronic device. As such an optical semiconductor module having the same configuration as that of FIG. 6, there is known an optical semiconductor module in which a metal airtight cap is joined to the upper surface of a metal frame by seam welding (Japanese Patent Application Laid-Open No. 8-94888). Gazette).

【0004】上記のシーム溶接法は、図5に示すよう
に、円錐台状のローラー電極10の斜面部を蓋体3の上
面の周縁に当接させながら転がし、ローラー電極10を
介して電流を蓋体3から枠体2へと流し、この時ローラ
ー電極10直下の蓋体3と枠体2との当接部に発生する
ジュール熱によって、その当接部に予め形成されている
Niメッキ層等を溶融させ、再び固化させて接合層とな
すことにより、蓋体3を枠体2に溶接する方法である。
このシーム溶接法では、蓋体3の全周を溶接する際に発
生する熱はローラー電極10の接触部近辺に限られ、ま
たその熱は枠体2を介して基体1側へと速やかに伝達さ
れる。その結果、半導体パッケージ内に載置している半
導体素子4に熱破壊等を発生させることがないので、近
年多用されている蓋体3の接合方法である。
In the above-described seam welding method, as shown in FIG. 5, the roller electrode 10 having a truncated cone shape is rolled while being brought into contact with the peripheral edge of the upper surface of the lid 3, and current is applied through the roller electrode 10. It flows from the lid 3 to the frame 2, and at this time, a Ni plating layer previously formed on the contact between the lid 3 and the frame 2 just below the roller electrode 10 is generated by Joule heat generated at the contact. This is a method in which the lid 3 is welded to the frame 2 by melting and the like to form a bonding layer again.
In this seam welding method, heat generated when welding the entire circumference of the lid 3 is limited to the vicinity of the contact portion of the roller electrode 10, and the heat is quickly transmitted to the base 1 via the frame 2. Is done. As a result, the semiconductor element 4 mounted in the semiconductor package does not suffer from thermal destruction or the like, so that the joining method of the lid 3 has been frequently used in recent years.

【0005】また金属製の蓋体3は、その両主面がロー
ル圧延等の成形方法により比較的平滑な表面性状とされ
ている。また、特開平8−94888号公報に示されて
いるように、枠体2の上面に接合される側の蓋体3の主
面の周縁部はエッチングによって薄肉部9を形成してい
る。
[0005] The metal lid 3 has relatively smooth surface properties on both main surfaces by a forming method such as roll rolling. Further, as shown in Japanese Patent Application Laid-Open No. 8-94888, the peripheral portion of the main surface of the lid 3 on the side joined to the upper surface of the frame 2 forms a thin portion 9 by etching.

【0006】そして、蓋体3の周縁部に薄肉部9を形成
するのは、図5に示すように、蓋体3の周縁部の面方向
(X方向)から見た断面の断面積を減少させることによ
り、蓋体3の周縁部の面方向の電気抵抗を大きくしてロ
ーラー電極10から蓋体3の主面の中心側に流れる電流
を少なくするとともに、蓋体3の周縁部のX方向に垂直
な方向Y(主面に垂直な方向)から見た断面の断面積
を、X方向における断面積の数倍以上とし得ることから
電気抵抗を小さくすることができ、よってローラー電極
10から電気抵抗が小さい枠体2の方向(下方)に流れ
る電流を大きくできる為である。これにより、蓋体3と
枠体2との当接部に大きなジュール熱を発生させ得る。
また蓋体3の周縁部に薄肉部が形成されたことで、段差
が形成され、蓋体3の枠体2への位置合わせにも役立つ
といったものも提案されている(特開平8−27420
8号公報参照)。
The reason why the thin portion 9 is formed on the peripheral portion of the lid 3 is to reduce the cross-sectional area of the cross section of the peripheral portion of the lid 3 viewed from the plane direction (X direction), as shown in FIG. By doing so, the electric resistance in the surface direction of the peripheral portion of the cover 3 is increased to reduce the current flowing from the roller electrode 10 to the center side of the main surface of the cover 3, and the X direction of the peripheral portion of the cover 3 Can be several times or more the cross-sectional area in the X direction when viewed from a direction Y (a direction perpendicular to the main surface), which can reduce the electric resistance. This is because the current flowing in the direction (downward) of the frame 2 having a small resistance can be increased. Thereby, a large Joule heat can be generated at the contact portion between the lid 3 and the frame 2.
Further, there has been proposed a configuration in which a step is formed by forming a thin portion on a peripheral portion of the lid 3, which is also useful for positioning the lid 3 with the frame 2 (Japanese Patent Laid-Open No. 8-27420).
No. 8).

【0007】[0007]

【発明が解決しようとする課題】しかしながら、前述の
ように蓋体3を枠体2に効率よく溶接するために蓋体3
の周縁部に薄肉部9を形成しているのであるが、シーム
溶接時に一旦溶融し固化した接合層8中にボイドが発生
して、かかるボイドにより蓋体3の接合強度が低下す
る、また半導体パッケージの気密性が劣化するなどの不
具合が発生していた。これは、エッチングにより薄肉化
された蓋体3の周縁部の表面の凹凸が大きいため、溶融
したNiの流れが阻害され、蓋体3と枠体2との当接部
に均一かつ密に行きわたらず、その結果接合層8にボイ
ドが発生することによると考えられる。
However, in order to efficiently weld the cover 3 to the frame 2 as described above, the cover 3
A thin portion 9 is formed in the peripheral portion of the bonding layer. However, voids are generated in the bonding layer 8 once melted and solidified at the time of seam welding, and the bonding strength of the lid 3 is reduced due to the voids. Problems such as deterioration of the airtightness of the package have occurred. This is because the unevenness of the surface of the peripheral portion of the lid 3 thinned by etching is large, so that the flow of the molten Ni is hindered, and the contact between the lid 3 and the frame 2 is uniformly and densely distributed. This is considered to be due to the occurrence of voids in the bonding layer 8 as a result.

【0008】従って、本発明は上記の問題点に鑑みて完
成されたものであり、その目的は、蓋体3を枠体2の上
面に接合する際に、接合層8におけるボイドの発生を抑
え、またその接合強度を向上させることにより、長期間
に亘って正常に作動する半導体パッケージを提供するこ
とである。
Accordingly, the present invention has been completed in view of the above problems, and an object thereof is to suppress the generation of voids in the bonding layer 8 when the lid 3 is bonded to the upper surface of the frame 2. Another object of the present invention is to provide a semiconductor package which operates normally for a long period of time by improving its bonding strength.

【0009】[0009]

【課題を解決するための手段】本発明の半導体素子収納
用パッケージは、上面に半導体素子を載置する載置部を
有する基体と、前記載置部を囲繞するように前記上面に
接合された枠体と、該枠体の上面にシーム溶接により一
方主面の周縁部が接合される金属製の蓋体とを具備した
半導体素子収納用パッケージにおいて、前記蓋体は、前
記一方主面の周縁部の算術平均粗さRaが3.0μm未
満であり、他方主面の周縁部がエッチングされて薄肉化
されていることを特徴とする。
According to a first aspect of the present invention, there is provided a package for housing a semiconductor element, the base having a mounting portion for mounting a semiconductor element on the upper surface, and the semiconductor device package being joined to the upper surface so as to surround the mounting portion. In a semiconductor element housing package comprising a frame and a metal lid to which a peripheral portion of one main surface is joined to an upper surface of the frame by seam welding, the lid is a peripheral portion of the one main surface. The arithmetic mean roughness Ra of the portion is less than 3.0 μm, and the peripheral portion of the main surface is etched and thinned.

【0010】本発明は、上記の構成により、蓋体を枠体
にシーム溶接法で接合する際に、蓋体と枠体との接合部
で溶融したNiメッキ層等の接合材の流れが阻害される
ことがなく、蓋体と枠体との接合部に均一かつ密に行き
わたるので、ボイドの発生を大幅に抑制し得るという作
用効果を有する。
According to the present invention, when the lid is joined to the frame by the seam welding method, the flow of the joining material such as the Ni plating layer melted at the joint between the lid and the frame is obstructed. Since it does not occur and spreads evenly and densely at the joint between the lid and the frame, there is an operational effect that the generation of voids can be greatly suppressed.

【0011】[0011]

【発明の実施の形態】本発明の半導体パッケージを添付
図面に基づき以下に詳細に説明する。図1及び図2は本
発明の半導体パッケージの一実施形態を示し、1は基
体、2は金属,セラミックス等から成る枠体、3は金属
製の蓋体、5は半導体素子4の載置部、6は入出力端子
である。かかる基体1と、枠体2と、蓋体3とによって
半導体素子4を収納するための容器が構成される。な
お、図1、図2において、従来例を示す図6と同じ部分
には同じ符号を付した。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor package according to the present invention will be described below in detail with reference to the accompanying drawings. 1 and 2 show an embodiment of a semiconductor package according to the present invention, wherein 1 is a base, 2 is a frame made of metal, ceramics or the like, 3 is a metal lid, and 5 is a mounting portion of the semiconductor element 4. , 6 are input / output terminals. The base 1, the frame 2, and the lid 3 constitute a container for housing the semiconductor element 4. 1 and 2, the same parts as those in FIG. 6 showing the conventional example are denoted by the same reference numerals.

【0012】基体1は、銅(Cu)やFe−Ni−Co
合金、Cu−W合金等の金属材料からなり、例えば、銅
からなる場合には銅のインゴット(塊)に圧延加工法、
プレス成型法、打ち抜き加工法等の従来周知の金属加工
法を採用することによって所定の形状に形成される。
The base 1 is made of copper (Cu) or Fe—Ni—Co
Alloy, a metal material such as a Cu-W alloy, for example, when it is made of copper, it is rolled into a copper ingot (lump),
It is formed into a predetermined shape by employing a conventionally known metal working method such as a press molding method or a punching method.

【0013】また、枠体2は、例えばFe−Ni−Co
合金、Fe−Ni合金等からなり、このような金属材料
の粉末を混合して加熱溶解させたものをシート状部材と
なし、これをロール圧延法にて所定の厚さに圧延し、得
られたシート状部材を従来周知の絞り加工法にてパイプ
状部材とする。このようにして得られたパイプ状部材
を、従来周知の引き抜き加工法により段階的に加工して
所望の矩形状の断面形状を有するパイプを得る。このパ
イプを適宜の長さに切断することによって、所望の大き
さ及び形状の枠体2が作製される。
The frame 2 is made of, for example, Fe--Ni--Co.
An alloy, a Fe-Ni alloy, etc., which is obtained by mixing and heating and melting powder of such a metal material to form a sheet-shaped member, which is rolled to a predetermined thickness by a roll rolling method, is obtained. The sheet-like member is formed into a pipe-like member by a conventionally known drawing method. The pipe-like member thus obtained is processed stepwise by a conventionally known drawing method to obtain a pipe having a desired rectangular cross-sectional shape. By cutting this pipe into an appropriate length, a frame 2 having a desired size and shape is manufactured.

【0014】この枠体2は、基体1の上面に半導体素子
4の載置部5を囲繞するようにして銀ロウなどのロウ材
を介して接合される。このとき、入出力端子6は、従来
周知のセラミックグリーンシート積層法によって別途作
製され、上面に枠体2の内外を導出するメタライズ配線
層7が形成された平板部上に立壁部を積層させた構成で
ある。そして、この入出力端子6は枠体2に設けた切り
欠きまたは貫通孔に銀ロウなどのロウ材を介して嵌着さ
れる。その後、基体1と枠体2の全面及び入出力端子6
の表面に形成されたメタライズ配線層7の表面にNiメ
ッキが施される。
The frame 2 is joined to the upper surface of the base 1 with a brazing material such as silver brazing surrounding the mounting portion 5 of the semiconductor element 4. At this time, the input / output terminals 6 were separately manufactured by a conventionally well-known ceramic green sheet laminating method, and a standing wall portion was laminated on a flat plate portion on which a metallized wiring layer 7 for leading the inside and outside of the frame 2 was formed on the upper surface. Configuration. The input / output terminal 6 is fitted into a notch or a through hole provided in the frame 2 via a brazing material such as silver brazing. Thereafter, the entire surface of the base 1 and the frame 2 and the input / output terminals 6
Is plated with Ni on the surface of the metallized wiring layer 7 formed on the surface of the substrate.

【0015】また、金属製の枠体2に代えてセラミック
ス製のものを用いても良く、その場合、例えば酸化アル
ミニウム(Al23)の粉末と、焼結助材としてのシリ
カ(SiO2)、カルシア(CaO)、マグネシア(M
gO)などの粉末と、適当なバインダー及び溶剤とを混
合してこれをスラリー状となし、次いで従来周知のドク
ターブレード法などのテープ成形法によって所定厚みの
セラミックグリーンシートに成形し、このセラミックグ
リーンシートを複数枚準備する。ついで、セラミックグ
リーンシートに打ち抜き加工を施すとともに、枠体2及
び基体1と接合される所定の部位にメタライズ層を、入
出力端子部にメタライズ配線層を、また図には示してい
ないがシーム溶接時に導電路となるメタライズ配線層を
形成し、この後セラミックスグリーンシートを積層し、
1600℃程度の温度で焼成してセラミック枠体2が得
られる。
In place of the metal frame 2, ceramics may be used. In this case, for example, aluminum oxide (Al 2 O 3 ) powder and silica (SiO 2 ), Calcia (CaO), magnesia (M
gO) and a suitable binder and solvent to form a slurry, which is then formed into a ceramic green sheet having a predetermined thickness by a conventional tape forming method such as a doctor blade method. Prepare multiple sheets. Next, the ceramic green sheet is punched, a metallized layer is formed on a predetermined portion to be joined to the frame 2 and the base 1, a metallized wiring layer is formed on the input / output terminal portion, and seam welding is performed. Sometimes a metallized wiring layer that becomes a conductive path is formed, and then a ceramic green sheet is laminated,
The ceramic frame 2 is obtained by firing at a temperature of about 1600 ° C.

【0016】そして、図4に示すように、この枠体2の
上面にFe−Ni−Co合金、Fe−Ni合金等からな
蓋体3の周縁部をシーム溶接するが、この周縁部を薄く
することにより以下のような作用が生じる。即ち、蓋体
3の周縁部の面方向(X方向)から見た断面の断面積を
減少させることにより、蓋体3の周縁部の面方向の電気
抵抗を大きくしてローラー電極10から蓋体3の主面の
中心側に流れる電流を少なくする。また、蓋体3の周縁
部のX方向に垂直な方向Y(主面に垂直な方向)から見
た断面の断面積を、X方向における断面積の数倍以上と
し得ることから、電気抵抗を小さくすることができる。
よって、ローラー電極10から電気抵抗が小さい枠体2
の方向(下方)に流れる電流を大きくし、蓋体3と枠体
2との当接部に大きなジュール熱を発生させ得る。
Then, as shown in FIG. 4, the periphery of the lid 3 made of an Fe--Ni--Co alloy, Fe--Ni alloy, or the like is seam-welded to the upper surface of the frame 2, and this periphery is thinned. By doing so, the following operation occurs. That is, by reducing the cross-sectional area of the cross section viewed from the surface direction (X direction) of the peripheral portion of the lid 3, the electric resistance in the surface direction of the peripheral portion of the lid 3 is increased, and The current flowing to the center side of the main surface of No. 3 is reduced. In addition, since the cross-sectional area of the peripheral portion of the lid 3 viewed from the direction Y (perpendicular to the main surface) perpendicular to the X direction can be several times or more the cross-sectional area in the X direction, the electric resistance is reduced. Can be smaller.
Therefore, the frame 2 having a small electric resistance from the roller electrode 10
The current flowing in the direction (downward) is increased, and a large Joule heat can be generated in the contact portion between the lid 3 and the frame 2.

【0017】本発明において、金属製の蓋体3は、一方
主面Aの周縁部9の算術平均粗さRaが3.0μm未満
であるが、3.0μm以上になると、枠体2の上面に接
合される一方主面Aの周縁部と枠体2の上面との接触面
積が小さくなって電気抵抗が大きくなり、流れる電流が
小さくなり、シーム溶接時に蓋体3と枠体2との接合部
の加熱が不十分となり接合が困難となる。
In the present invention, the metal lid 3 has an arithmetic mean roughness Ra of the peripheral portion 9 of the one main surface A of less than 3.0 μm. The contact area between the peripheral portion of the main surface A and the upper surface of the frame 2 is reduced, the electrical resistance is increased, the flowing current is reduced, and the joint between the lid 3 and the frame 2 during seam welding. The heating of the portion becomes insufficient and the joining becomes difficult.

【0018】また、金属製の蓋体3の両主面は、当初例
えばロール圧延法によって成型されており、圧延ロール
表面のRaは最も平滑なもので0.3μm程度である。
この圧延ロールの表面が蓋体3の主面にほぼそのまま転
写されるので、一方主面Aの周縁部のRaは実際上約
0.3μm以上3.0μm未満となる。したがって、一
方主面Aの周縁部のRaは0.3μm以上3.0μm未
満が好ましい。また、このことから、他方主面(上面)
Bの周縁部を除く両主面のRaは0.3μm以上3.0
μm未満が好適である。
The two main surfaces of the metal lid 3 are initially formed by, for example, a roll rolling method, and the surface of the roll has a smoothest Ra of about 0.3 μm.
Since the surface of the rolling roll is almost directly transferred to the main surface of the lid 3, the Ra of the peripheral portion of the main surface A is actually about 0.3 μm or more and less than 3.0 μm. Therefore, Ra at the peripheral portion of main surface A is preferably 0.3 μm or more and less than 3.0 μm. Also, from this, the other main surface (upper surface)
Ra of both main surfaces except the peripheral portion of B is 0.3 μm or more and 3.0.
Preferably less than μm.

【0019】この蓋体3の一方主面(下面)Aはエッチ
ングなどの表面処理が施されず、一方、他方主面(上
面)Bの周縁部はX方向から見た断面の断面積を減少さ
せるためにエッチングされて薄肉化される。この薄肉部
では、蓋体3の面方向の電流の流れが抑制される。エッ
チングされて得られた他方主面Bの周縁部9は3.0〜
6.3μm程度の算術平均粗さRaを有しているので、
枠体2の上面への接合に際してはこの他方主面Bを上側
にし、一方主面Aを接合面側として枠体2の上面にシー
ム溶接する。
One principal surface (lower surface) A of the lid 3 is not subjected to a surface treatment such as etching, while the peripheral portion of the other principal surface (upper surface) B has a reduced cross-sectional area as viewed in the X direction. It is etched to make it thinner. In this thin portion, the flow of current in the surface direction of the lid 3 is suppressed. The peripheral portion 9 of the other main surface B obtained by etching is 3.0 to 3.0.
Since it has an arithmetic average roughness Ra of about 6.3 μm,
When joining to the upper surface of the frame 2, the other main surface B is set to the upper side, and one main surface A is seam-welded to the upper surface of the frame 2 with the main surface A as the joining surface.

【0020】また薄肉部9の厚みは0.05〜0.15
mmがよく、0.05mm以下では、薄肉部9の一部が
シーム溶接時に溶融して消失したり、欠けが生じ易くな
る。また薄肉部9の厚みが0.15mm以上になると、
蓋体3の面方向(X方向)での電気抵抗が小さくなって
大きな電流がこの方向に流れ、蓋体3全体がジュール熱
によって加熱され、薄肉部9の加熱が不足する傾向にあ
る。
The thickness of the thin portion 9 is 0.05 to 0.15.
If the thickness is less than 0.05 mm, a part of the thin portion 9 is likely to be melted and lost or chipped during seam welding. When the thickness of the thin portion 9 is 0.15 mm or more,
The electric resistance in the surface direction (X direction) of the lid 3 is reduced, and a large current flows in this direction. The entire lid 3 is heated by Joule heat, and the heating of the thin portion 9 tends to be insufficient.

【0021】この蓋体3の厚さは0.1〜0.3mm程
度であり、よって薄肉部9は蓋体3の厚さの17〜50
%程度の厚さがよい。17%未満では、薄肉部9の一部
がシーム溶接時に溶融して消失したり、欠けが生じ易く
なるという点で不適である。50%を超えると、蓋体3
の面方向(X方向)での電気抵抗が小さくなって大きな
電流がこの方向に流れ、蓋体3全体がジュール熱によっ
て加熱され、薄肉部9の加熱が不足する傾向にある。
The thickness of the lid 3 is about 0.1 to 0.3 mm, so that the thin portion 9 has a thickness of 17 to 50 mm of the lid 3.
% Thickness is good. If it is less than 17%, a part of the thin portion 9 is unsuitable in that it melts and disappears during seam welding, or chipping easily occurs. If it exceeds 50%, the lid 3
The electrical resistance in the surface direction (X direction) becomes small, a large current flows in this direction, the entire lid 3 is heated by Joule heat, and the heating of the thin portion 9 tends to be insufficient.

【0022】また薄肉部9の幅は0.1〜1.5mmが
よく、0.1mm以下では蓋体3の面方向の電気抵抗が
小さくなり、よって面方向に大きな電流が流れ易くな
る。また、薄肉部9の幅が1.5mm以上になると、蓋
体3の強度が薄肉部9で低下し、半導体パッケージの気
密性をテストするHeリークテストの際に薄肉部9が変
形するという問題が発生し易い。
The width of the thin portion 9 is preferably 0.1 to 1.5 mm. If the width is 0.1 mm or less, the electric resistance in the surface direction of the lid 3 becomes small, and a large current easily flows in the surface direction. Further, when the width of the thin portion 9 is 1.5 mm or more, the strength of the lid 3 is reduced at the thin portion 9, and the thin portion 9 is deformed during a He leak test for testing the airtightness of the semiconductor package. Is easy to occur.

【0023】かくして、基体1と枠体2とで構成された
容器内に半導体素子4を収容し、しかる後半導体素子4
上の各電極と入出力端子6上のメタライズ配線層7とを
ボンディングワイヤ11によって電気的に接続し、最後
に蓋体3によって半導体素子4が気密に封止されて半導
体装置となる。
Thus, the semiconductor element 4 is accommodated in the container constituted by the base 1 and the frame 2, and thereafter, the semiconductor element 4
The upper electrodes and the metallized wiring layer 7 on the input / output terminals 6 are electrically connected by bonding wires 11, and finally, the semiconductor element 4 is hermetically sealed by the lid 3, thereby forming a semiconductor device.

【0024】ところで、従来例では、エッチングにより
形成された薄肉部9の段差がシーム溶接の際の蓋体3の
位置合わせにも役立つとされているが、エッチングの位
置ずれなども生じやすいため、シーム溶接において段差
による位置合わせを行うことは実用性に乏しい。したが
って、段差が設けられていない一方主面Aを接合面とす
ることに不具合はほとんどない。
In the conventional example, the step of the thin portion 9 formed by etching is said to be useful for positioning the lid 3 at the time of seam welding. It is not practical to perform alignment by steps in seam welding. Accordingly, there is almost no problem in using the main surface A as the joining surface while the step is not provided.

【0025】なお、本発明は上記実施形態に限定される
ものではなく、本発明の要旨を逸脱しない範囲において
種々の変更を行うことは何ら差し支えない。例えば、図
3に示すように、入出力端子6をセラミックスから成る
平板状のものとし、セラミックスから成る枠体2の下面
の切り欠きに嵌着させる構成としてもよく、この場合入
出力端子6に立壁部がない分半導体パッケージが薄型化
される。
It should be noted that the present invention is not limited to the above embodiment, and that various changes can be made without departing from the spirit of the present invention. For example, as shown in FIG. 3, the input / output terminal 6 may be a flat plate made of ceramics and may be fitted into a notch on the lower surface of the frame 2 made of ceramics. The semiconductor package is reduced in thickness because there is no standing wall.

【0026】[0026]

【発明の効果】本発明の半導体素子収納用パッケージに
よれば、上面に半導体素子を載置する載置部を有する基
体と、載置部を囲繞するように上面に接合された枠体
と、枠体の上面にシーム溶接により一方主面の周縁部が
接合される金属製の蓋体とを具備しており、蓋体は、一
方主面の周縁部の算術平均粗さRaが3.0μm未満で
あり、他方主面の周縁部がエッチングにより薄肉化され
ていることにより、シーム溶接の際の接合部におけるN
iメッキ等の接合材の流れが阻害されることがなく、蓋
体と枠体との当接部に均一かつ密に行きわたるので、接
合部に発生するボイドを大幅に抑制することが出来る。
その結果、蓋体の接合強度が低下することがなく、また
半導体パッケージ内部の気密性が劣化することがない。
さらに、シーム溶接時の電流を大部分蓋体の周縁部から
下方の枠体へと効率よく流すことができるため、電流の
大きさを小さく出来るとともに、蓋体の全周における均
一な溶接を可能とし、また溶接時間の短縮が可能とな
り、半導体パッケージを低コストに製造することが出来
る。
According to the semiconductor device housing package of the present invention, a base having a mounting portion for mounting a semiconductor element on the upper surface, a frame joined to the upper surface so as to surround the mounting portion, A metal lid to which the peripheral portion of the one main surface is joined by seam welding on the upper surface of the frame, wherein the lid has an arithmetic average roughness Ra of 3.0 μm on the peripheral portion of the one main surface. And the peripheral portion of the other main surface is thinned by etching, so that the N at the joint at the time of seam welding is reduced.
Since the flow of the bonding material such as i-plating is not hindered and uniformly and densely reaches the contact portion between the lid and the frame, voids generated at the bonding portion can be significantly suppressed.
As a result, the joining strength of the lid does not decrease, and the airtightness inside the semiconductor package does not deteriorate.
Furthermore, the current during seam welding can be efficiently flowed from the periphery of the lid to the lower frame, so that the current can be reduced and uniform welding can be achieved over the entire circumference of the lid. In addition, the welding time can be reduced, and the semiconductor package can be manufactured at low cost.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体素子収納用パッケージの一実施
形態の断面図である。
FIG. 1 is a cross-sectional view of one embodiment of a semiconductor device housing package of the present invention.

【図2】図1の半導体素子収納用パッケージの要部の部
分断面図である。
FIG. 2 is a partial cross-sectional view of a main part of the semiconductor device housing package of FIG. 1;

【図3】本発明の半導体素子収納用パッケージの他の実
施形態の断面図である。
FIG. 3 is a cross-sectional view of another embodiment of the semiconductor device housing package of the present invention.

【図4】本発明の半導体素子収納用パッケージにおける
枠体と蓋体のシーム溶接を説明するものであり、ローラ
ー電極と半導体素子収納用パッケージの溶接部を示す部
分断面図である。
FIG. 4 is a partial cross-sectional view for explaining seam welding between the frame and the lid in the semiconductor element housing package of the present invention, and showing a welded portion between the roller electrode and the semiconductor element housing package.

【図5】従来の半導体素子収納用パッケージにおける枠
体と蓋体のシーム溶接を説明するものであり、ローラー
電極と半導体素子収納用パッケージの溶接部を示す部分
断面図である。
FIG. 5 is a partial cross-sectional view for explaining seam welding of a frame and a lid in a conventional semiconductor element housing package, and showing a welded portion between a roller electrode and the semiconductor element housing package.

【図6】従来の半導体素子収納用パッケージの断面図で
ある。
FIG. 6 is a cross-sectional view of a conventional semiconductor element storage package.

【符号の説明】[Explanation of symbols]

1・・・基体 2・・・枠体 3・・・金属製の蓋体 4・・・半導体素子 5・・・載置部 6・・・入出力端子 7・・・メタライズ配線層 8・・・接合層 9・・・薄肉部 10・・・ローラー電極 11・・・ボンディングワイヤ A・・・一方主面 B・・・他方主面 DESCRIPTION OF SYMBOLS 1 ... Base body 2 ... Frame body 3 ... Metal lid 4 ... Semiconductor element 5 ... Placement part 6 ... Input / output terminal 7 ... Metallized wiring layer 8 ... -Bonding layer 9-Thin portion 10-Roller electrode 11-Bonding wire A-One main surface B-Other main surface

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】上面に半導体素子を載置する載置部を有す
る基体と、前記載置部を囲繞するように前記上面に接合
された枠体と、該枠体の上面にシーム溶接により一方主
面の周縁部が接合される金属製の蓋体とを具備した半導
体素子収納用パッケージにおいて、前記蓋体は、前記一
方主面の周縁部の算術平均粗さRaが3.0μm未満で
あり、他方主面の周縁部がエッチングにより薄肉化され
ていることを特徴とする半導体素子収納用パッケージ。
A base having a mounting portion for mounting a semiconductor element on an upper surface, a frame joined to the upper surface so as to surround the mounting portion, and one of the frames being seam-welded to the upper surface of the frame. In the semiconductor device housing package provided with a metal lid to which a peripheral portion of the main surface is joined, the lid has an arithmetic average roughness Ra of the peripheral portion of the one main surface less than 3.0 μm. A semiconductor element housing package, wherein a peripheral portion of the other main surface is thinned by etching.
JP2000215007A 2000-07-14 2000-07-14 Package for storing semiconductor elements Expired - Lifetime JP3663343B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000215007A JP3663343B2 (en) 2000-07-14 2000-07-14 Package for storing semiconductor elements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000215007A JP3663343B2 (en) 2000-07-14 2000-07-14 Package for storing semiconductor elements

Publications (2)

Publication Number Publication Date
JP2002033408A true JP2002033408A (en) 2002-01-31
JP3663343B2 JP3663343B2 (en) 2005-06-22

Family

ID=18710498

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000215007A Expired - Lifetime JP3663343B2 (en) 2000-07-14 2000-07-14 Package for storing semiconductor elements

Country Status (1)

Country Link
JP (1) JP3663343B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006112105A1 (en) * 2005-04-07 2006-10-26 Tanaka Kikinzoku Kogyo K.K. Hermetic seal cover and method for manufacture thereof
JPWO2012017888A1 (en) * 2010-08-04 2013-10-03 株式会社村田製作所 Electronic component manufacturing method and electronic component

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006112105A1 (en) * 2005-04-07 2006-10-26 Tanaka Kikinzoku Kogyo K.K. Hermetic seal cover and method for manufacture thereof
EP1863084A1 (en) * 2005-04-07 2007-12-05 Tanaka Kikinzoku Kogyo Kabushiki Kaisha Hermetic seal cover and method for manufacture thereof
EP1863084A4 (en) * 2005-04-07 2010-03-24 Tanaka Precious Metal Ind Hermetic seal cover and method for manufacture thereof
JPWO2012017888A1 (en) * 2010-08-04 2013-10-03 株式会社村田製作所 Electronic component manufacturing method and electronic component

Also Published As

Publication number Publication date
JP3663343B2 (en) 2005-06-22

Similar Documents

Publication Publication Date Title
JP6602480B2 (en) Semiconductor device
CN103222045B (en) Electro part carrying packaging body and make use of the electronic installation of this packaging body
US20210407954A1 (en) Semiconductor device
JP2000183222A (en) Semiconductor device and manufacture thereof
JP2008235531A (en) Package for hermetic sealing, and connection structure
JP2005039168A (en) Ceramic package and tantalum electrolytic capacitor using the same
US20160358832A1 (en) Ceramic package and manufacturing method therefor
JP2002033408A (en) Package for semiconductor element
JP3573955B2 (en) Power semiconductor device and method of manufacturing the same
JP4511214B2 (en) Electronic component storage package and electronic device
JPH08141745A (en) Hermetic sealing method of ic
JP2004356391A (en) Package for encasing semiconductor element and semiconductor device
JPH05315467A (en) Hybrid integrated circuit device
JP3694670B2 (en) Semiconductor element storage package and semiconductor device
JP3800998B2 (en) Electronic component package, and electronic package component and electronic device using the same
JP3323171B2 (en) Package for storing semiconductor elements
JPH09293799A (en) Semiconductor integrated circuit package and manufacture thereof
JP3078534B1 (en) Electronic equipment
JP2004327562A (en) Electronic part housing package and electronic device
JP2004296577A (en) Input/output terminal and package for housing semiconductor element, and semiconductor device
JP4295641B2 (en) Manufacturing method of electronic component storage package
JP2849865B2 (en) Heat radiator manufacturing method
JP2002170895A (en) Package for housing electronic component and method for sealing the same
JP2740602B2 (en) Package for storing semiconductor elements
JP4854644B2 (en) Package and electronic equipment

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20040913

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20040921

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20041118

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20050322

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20050328

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080401

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090401

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090401

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100401

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110401

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110401

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120401

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120401

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130401

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130401

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140401

Year of fee payment: 9