JPH09293799A - Semiconductor integrated circuit package and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To protect a semiconductor integrated circuit package against cracking caused by seam welding in a lid sealing process by a method wherein a multilayer ceramic board is set more in number of layers than a conventional one at least by one so as to disperse stress imposed on the ceramic board in a sealing process. SOLUTION: A package is increased in temperature by heat released at welding, whereby stress is induced between a lid and a multilayer ceramic board. The stress concentrates usually at an interface between the layers of the multilayer ceramic board. At this point, when the multilayer ceramic board is composed of layers which comprise a semiconductor integrated circuit chip mounting surface 6, a stitching surface 7, and a seal ring surface 8, the number of layers is set more than 2. Therefore, stress imposed on an interface between layers can be more dispersed. Therefore, a multilayer ceramic board can be protected against cracking caused by stress.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a semiconductor integrated circuit package, and more particularly to a hermetically sealed semiconductor integrated circuit package made of ceramic and a method of manufacturing the same.

[0002]

2. Description of the Related Art As a prior art of this kind of semiconductor integrated circuit package, for example, Japanese Patent Application Laid-Open No. Sho 60-123044 discloses that when a lid is sealed by seam welding, a ceramic, a seal ring and a lid constituting the package are sealed. Stress is generated due to the difference in the coefficient of linear expansion from the constituent metal material, and the stress is concentrated at the junction boundary of the stepped portion of the multilayer ceramic substrate, cracks are generated and the airtightness of the package is reduced. For the purpose of providing a semiconductor device capable of preventing the problem, there has been proposed a configuration in which a rounded or inclined portion is provided at a boundary portion of a ceramic layer in a cavity forming a step portion.

FIG. 8A is a sectional view showing an example of a conventional semiconductor integrated circuit package proposed in the above publication. In FIG. 8A, 4 is a lead frame, 5 is a hollow portion, 6 is a chip mounting surface, 7 is a metallized pattern layer, 8 is a seal ring surface, 10 is a lid, 11 is an opening, 12 is a chip, 13 Denotes a ceramic substrate, 14 denotes bonding wires, and 26 denotes a round portion provided in a corner region between ceramic layers. As described above, the rounded portion 26 is formed at the junction boundary of the stepped portion of the multilayer ceramic substrate.
Is added, thereby dispersing the stress at the time of seam welding and preventing a decrease in airtightness due to generation of cracks. FIG. 8B is also a cross-sectional view showing an example of the semiconductor integrated circuit package proposed in the above-mentioned publication, and an inclined portion 27 is provided in a corner region between ceramic layers.

[0004]

However, in the prior art described above, in order to prevent cracks from occurring during the sealing step by seam welding of the hermetically sealed ceramic semiconductor integrated circuit package, the boundary of the multilayer ceramic substrate is prevented. In order to provide a rounded portion or an inclined portion in the portion, it is necessary to introduce a special process different from the usual process in the manufacturing process of the multilayer ceramic substrate, which has a problem that it causes a cost increase. I have.

[0005] The reason for this is that a multi-layer ceramic substrate is formed by punching a green sheet (a sheet obtained by connecting a ceramic powder before sintering with a binder into a sheet) as a general manufacturing process. In order to form a rounded or sloping portion such as a semiconductor integrated circuit package into a green sheet, the green sheet is punched and formed, and then the rounded or sloping portion is laminated with the green sheet and then an alumina paste is applied. A coating step is required.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above problems, and has as its object to reduce the occurrence of cracks during a lid sealing step by seam welding of a hermetically sealed ceramic semiconductor integrated circuit package. It is an object of the present invention to provide a semiconductor integrated circuit package and a method of manufacturing the same, which can prevent such a problem.

Another object of the present invention is to provide a semiconductor integrated circuit package capable of manufacturing a hermetically sealed ceramic semiconductor integrated circuit package by using a conventional manufacturing process. To provide.

[0008]

In order to achieve the above object, the semiconductor integrated circuit package of the present invention is a multilayer ceramic substrate having a step required in a manufacturing process such as a surface for attaching a wire connection and a seal ring, It is characterized in that a step is further provided between at least one of the surfaces having the step so that the stress applied during the sealing step is dispersed.

Further, in the semiconductor integrated circuit package of the present invention, preferably, in the semiconductor integrated circuit package including a multilayer ceramic substrate, a seal ring, and a lead frame, the chip mounting surface of the multilayer ceramic substrate and wire connection are provided. A step formed by changing the shape of the ceramic substrate between the stitching surface and the seal ring surface so that the opening dimension becomes narrower and the remaining ceramic substrate width becomes wider toward the lower layer. Is provided.

The outline of the present invention will be described below. In the present invention, a multi-layer ceramic substrate having a step such as a mounting surface of a semiconductor integrated circuit chip, a stitching surface for wire bonding, a surface for attaching a seal ring, and the like, wherein steps are further divided between the respective surfaces. It is.
As described above, by increasing the level difference of the multilayer ceramic substrate of the semiconductor integrated circuit package, the places where stress is applied when sealing the lid of the semiconductor integrated circuit package by seam welding are increased, and the boundary of the joining of one ceramic substrate is increased. , The occurrence of cracks can be prevented and the problem of reduced airtightness can be avoided, thereby greatly improving yield and reliability.

Further, since the ceramic semiconductor integrated circuit package having this configuration can be manufactured by laminating green sheets formed by punching, it can be manufactured by using the conventional manufacturing process of a multilayer ceramic substrate as it is. It has the advantage of being able to do so, while suppressing an increase in manufacturing costs.

[0012]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIGS. 1A and 1B are a plan view and a sectional view showing a first embodiment of the present invention.

Referring to FIG. 1, in a first embodiment of the present invention, a multilayer ceramic substrate is used, each layer of the ceramic substrate is provided with a hollow portion 5, and the outer shape is processed. However, the hollow portion is not provided in the ceramic substrate of the layer to be the semiconductor integrated circuit chip mounting surface 6.

A stitch surface 7 on which a stitch connected to an electrode on a semiconductor integrated circuit chip 12 by a wire 14 is formed.
Is provided on the ceramic substrate in the middle layer (third layer in FIG. 1).

A seal ring 3 is welded to the lid 10 to seal the package hermetically to the uppermost surface (seal ring surface) 8 of the multilayer ceramic substrate. A lead frame 4 is joined to the outside of the multilayer ceramic substrate.

The characteristic portions of the first embodiment of the present invention will be described in detail. The dimensions of the opening and the outer shape of the ceramic substrate between the respective surfaces of the semiconductor integrated circuit chip mounting surface 6, the stitch surface 7, and the seal ring surface 8 of the multilayer ceramic substrate are increased from the upper layer to the lower layer. By changing the dimensions of the ceramic substrate to be small and the remaining ceramic substrate to be wide, many steps for stress dispersion are formed.

The greater the number of stages, the more the effect of dispersing the stress is. However, in practice, there are restrictions such as the thickness of the semiconductor integrated circuit chip to be mounted, the assembly conditions, and the thickness of the green sheet. Is about 1 to 4 steps.

FIG. 2A, FIG. 2B and FIG. 2C
1 shows a plan view and a side view illustrating the seam welding operation of the first embodiment of the present invention shown in FIG. 1, respectively.

Referring to FIG. 2, in the seam welding operation, the lid 10 is mounted on the seal ring 3 and a pair of copper rotating electrodes 15 having a tapered portion are passed through the lid 10 between the electrodes while passing a current. Move it. Joule heat is generated by the electric current at the contact points of the electrodes, whereby welding is performed and the entire circumference of the lid 10 is moved (FIG. 2).
The sealing is completed when the arrow (A) indicates the moving direction).

The temperature of the package rises due to the heat generated at the time of welding. However, depending on conditions such as the thermal conductivity inherent to each material of the lid 10 and the multilayer ceramic substrate, the package structure, and the speed at which the rotating electrode 15 is moved, etc. The temperature of the package may not be uniform and a temperature distribution may occur.

When the lid 10 and the multilayer ceramic substrate are cooled from the state having such a temperature distribution to room temperature, a displacement amount occurs due to a temperature change amount of each part of the lid 10 and the multilayer ceramic substrate and a linear expansion coefficient specific to the material. A mismatch is generated between the lid and the multilayer ceramic substrate due to the mismatch between the displacements.

FIG. 2C schematically shows how stress is generated by shrinkage of the lid 10. That is, as shown in FIG. 2C, stress is applied in the direction of arrow 17 and stress is applied to the portion indicated by 18 on the ceramic substrate.

This stress concentrates on the boundary between the steps of the multilayer ceramic substrate. In the semiconductor integrated circuit package according to the first embodiment of the present invention, the steps of the multilayer ceramic substrate are mounted on the semiconductor integrated circuit chip. When the surface 6, the stitching surface 7, and the seal ring surface 8 are formed, the stress applied to the boundary between the steps is dispersed by increasing the number of the portions more than the two conventionally formed, and the boundary is formed at one location. Since the amount of the stress is reduced, it is possible to prevent the multilayer ceramic substrate from cracking due to the stress.

The manufacturing process of the package according to the first embodiment of the present invention will be described with reference to FIG. FIG.
FIG. 2 is a diagram illustrating a manufacturing process of the semiconductor integrated circuit package according to the first embodiment of the present invention illustrated in FIG. 1 in a process order.

As shown in FIG. 3, the green sheet 19
The hollow part and the outer part of the package are cut out from the mold 2
0 (see FIGS. 3A and 3B).

The formed green sheet 21 (FIG. 3C)
(See FIG. 3 (D)), and a ceramic is sintered by pressing and firing. Metal fittings such as the seal ring 3 and the lead frame 4 are brazed to the multilayer ceramic substrate 2 (see FIG. 3E), and the surface of the conductor and the metal fitting is treated to complete the process.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to explain the above-mentioned first embodiment of the present invention in more detail, an embodiment of the present invention will be described below with reference to FIG.

Referring to FIG. 4, the embodiment of the present invention uses alumina for the multilayer ceramic substrate and Kovar for the seal ring and the lid, respectively.

On the multi-layer alumina substrate, a distance from the semiconductor integrated circuit chip mounting surface 6 to the stitch surface 7 for wire connection is 2
There are two steps from the step and the stitch surface 7 to the uppermost surface to which the seal ring 23 is joined.

Table 1 shows examples of parameters indicating the physical properties of alumina and Kovar.

[0032]

[Table 1]

Next, the operation of the embodiment of the present invention will be described in detail with reference to FIG.

When seam welding the lid 25, the lid 2
5 is placed on a seal ring, and a pair of rotating electrodes 15 made of copper having a tapered portion are moved while flowing an electric current between the electrodes through a lid 25, so that welding is performed by Joule heat due to the electric current at a contact portion of the electrodes Then, the entire circumference of the lid 25 is moved to complete the sealing. 80 welds
The temperature becomes higher than 0 ° C.

This welding operation is performed at room temperature. The temperature distribution of the package after welding has a temperature gradient of 300 ° C. at the center of the lid and 100 ° C. at the bottom of the package.

Stress is caused by the difference between the respective temperatures when cooling from this state to room temperature and the difference in the displacement amount determined by the linear expansion coefficient.

If the stress at this time reaches a certain amount, the alumina is damaged and the airtightness of the package is impaired. However, in the package of this embodiment, one step is formed by increasing the steps of the multilayer alumina substrate. Therefore, the airtightness of the package is not affected without damaging the alumina.

The manufacturing process of the semiconductor integrated circuit package according to this embodiment is also manufactured by the manufacturing process shown in FIG.

Next, a second embodiment of the present invention will be described in detail with reference to FIG.

Referring to FIG. 6, in the second embodiment of the present invention, a multi-layer ceramic substrate is provided with a semiconductor integrated circuit chip mounting surface 6 to a stitch surface 7 for connecting a wire 14 to one.
There are two steps from the step and the stitch surface 7 to the uppermost surface 8 to which the seal ring 3 is joined.

In the second embodiment of the present invention, the division between the chip mounting surface 6 and the stitch surface 7 is omitted, but the effect of the application division can be obtained by dividing the stitch surface 7 and the seal ring surface 8. Can be As described above, the number of steps between the respective surfaces is not limited to two. Also, the number of steps between the surfaces need not be the same.

The mounting position of the lead frame 4 does not need to be the same as the stitch surface 7, and the same effect can be obtained in the structure shown in FIGS. 7A and 7B.

In the example shown in FIG.
Is attached to the back surface of the lowermost substrate, in the example shown in FIG. 7B, to the side surface of the lowermost substrate.

[0044]

As described above, according to the present invention,
It has the following effects.

A first effect of the present invention is that cracks can be prevented from occurring during a sealing step by seam welding of a hermetically sealed ceramic semiconductor integrated circuit package. Therefore, the present invention achieves a remarkable improvement in the reliability of the semiconductor integrated circuit package.

The reason for this is that, in the present invention, by increasing the steps of the multilayer ceramic substrate of the semiconductor integrated circuit package, the locations where stress is applied when the lid of the semiconductor integrated circuit package is sealed by seam welding are increased. This is because the occurrence of cracks can be prevented by reducing the amount of stress applied to the boundaries of the joining of the ceramic substrates, and the problem of reduced airtightness can be avoided.

The second effect of the present invention is that a special technique of applying an alumina paste to provide a rounded portion or an inclined portion at a boundary portion of a multilayer ceramic substrate, which is disclosed in Japanese Patent Application Laid-Open No. 60-123444 as a prior art. It is possible to manufacture without going through a complicated process.
Therefore, according to the present invention, it is possible to realize a highly reliable semiconductor integrated circuit package while suppressing an increase in cost.

The reason for this is that, in the present invention, the ceramic semiconductor integrated circuit package having this structure can be formed by stacking green sheets punched and formed, so that a normal manufacturing process for a multilayer ceramic substrate is performed. It can be manufactured by using.

[Brief description of drawings]

FIG. 1 is a plan view and a cross-sectional view showing a first embodiment of the present invention.

FIG. 2 is a plan view and a side view illustrating a seam welding operation in the first embodiment of the present invention in FIG. 1;

FIG. 3 is a diagram illustrating a package manufacturing process according to the first embodiment of the present invention.

FIG. 4 is a plan view and a cross-sectional view showing an embodiment of the present invention.

FIG. 5 is a plan view and a side view illustrating a seam welding operation according to the embodiment of the present invention.

FIG. 6 is a cross-sectional view showing another embodiment of the present invention.

FIG. 7 is a sectional view showing still another embodiment of the present invention.

FIG. 8 is a sectional view showing a conventional semiconductor integrated circuit package.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Package 2 Multilayer ceramic substrate 3 Seal ring 4 Lead frame 5 Hollow part 6 Chip mounting surface 7 Stitch surface 8 Seal ring surface 9 Stress dispersion step 10 Lid 11 Opening 12 Chip 13 Ceramic substrate 14 Wire 15 Rotary electrode 16 Electrode movement Direction 17 Stressed direction 18 Stressed location 19 Green sheet 20 Die 21 Molded green sheet 22 Multilayer alumina substrate 23 Seal ring (Kovar) 24 Lead frame (Kovar) 25 Lid (Kovar) 26 Rounded portion 27 Slope

Claims (5)

[Claims] 1. A multilayer ceramic substrate having a step required in a manufacturing process such as a surface for attaching a wire connection and a seal ring, and further a step is provided between at least one of the steps. The semiconductor integrated circuit package is characterized in that it is configured to disperse the stress applied during the sealing step. 2. A multilayer ceramic substrate, a seal ring,
In a semiconductor integrated circuit package including a lead frame, a ceramic substrate shape is a lower layer between the chip mounting surface of the multilayer ceramic substrate, the stitch surface for wire connection, and the seal ring surface. Accordingly, the semiconductor integrated circuit package is provided with a step formed by changing the opening dimension to be narrower and the remaining ceramic substrate width to be wider. 3. A semiconductor integrated circuit package having a multi-layer ceramic substrate structure having steps such as a stitch surface for wire connection and a seal ring surface for attaching a seal ring, wherein the seal ring surface and the stitch surface are further divided to form a lower layer. At least one step is provided between the seal ring surface and the stitch surface by making the ceramic substrate wider than the upper layer, and a stress is applied when sealing the package lid by seam welding. A semiconductor integrated circuit package, wherein the semiconductor integrated circuit package is configured to be distributed. 4. The semiconductor integrated circuit package according to claim 2, wherein at least one step is provided between the semiconductor integrated circuit chip mounting surface and the stitch surface. 5. A multilayer ceramic substrate, a seal ring,
A method of manufacturing a semiconductor integrated circuit package including: a lead frame; a chip mounting surface of the multilayer ceramic substrate, a stitch surface for wire connection, and a seal ring surface, each having a ceramic substrate shape below. Providing a step by reducing the size of the opening as the layer is formed and changing the size of the remaining ceramic substrate so as to increase the width of the remaining ceramic substrate, thereby providing a step.