JP3647448B2 - 半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置及び半導体装置の製造方法 Download PDFInfo
- Publication number
- JP3647448B2 JP3647448B2 JP2004168845A JP2004168845A JP3647448B2 JP 3647448 B2 JP3647448 B2 JP 3647448B2 JP 2004168845 A JP2004168845 A JP 2004168845A JP 2004168845 A JP2004168845 A JP 2004168845A JP 3647448 B2 JP3647448 B2 JP 3647448B2
- Authority
- JP
- Japan
- Prior art keywords
- die pad
- semiconductor element
- semiconductor device
- resin
- view
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004168845A JP3647448B2 (ja) | 2004-06-07 | 2004-06-07 | 半導体装置及び半導体装置の製造方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004168845A JP3647448B2 (ja) | 2004-06-07 | 2004-06-07 | 半導体装置及び半導体装置の製造方法 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP35644699A Division JP3602997B2 (ja) | 1999-12-15 | 1999-12-15 | 半導体装置及び半導体装置の製造方法 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005004182A Division JP4418373B2 (ja) | 2005-01-11 | 2005-01-11 | 半導体装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2004260216A JP2004260216A (ja) | 2004-09-16 |
| JP3647448B2 true JP3647448B2 (ja) | 2005-05-11 |
| JP2004260216A5 JP2004260216A5 (https=) | 2005-06-02 |
Family
ID=33128737
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004168845A Expired - Fee Related JP3647448B2 (ja) | 2004-06-07 | 2004-06-07 | 半導体装置及び半導体装置の製造方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3647448B2 (https=) |
-
2004
- 2004-06-07 JP JP2004168845A patent/JP3647448B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2004260216A (ja) | 2004-09-16 |
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