JP4418373B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4418373B2 JP4418373B2 JP2005004182A JP2005004182A JP4418373B2 JP 4418373 B2 JP4418373 B2 JP 4418373B2 JP 2005004182 A JP2005004182 A JP 2005004182A JP 2005004182 A JP2005004182 A JP 2005004182A JP 4418373 B2 JP4418373 B2 JP 4418373B2
- Authority
- JP
- Japan
- Prior art keywords
- die pad
- semiconductor device
- resin
- semiconductor element
- view
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
参考実施形態1の半導体装置を図面を用いて説明する。
本参考実施形態2の半導体装置を図面を用いて説明する。
参考実施形態3の半導体装置を図面を用いて説明する。
本発明の実施の形態1の半導体装置を図面を用いて説明する。
参考実施形態4の半導体装置を図面を用いて説明する。
本発明の実施の形態2の半導体装置の製造方法を図面を用いて説明する。
印方向から見た断面図である。なお、91は封止樹脂の注入方向を示す。
参考実施形態5の半導体装置の製造方法を図面を用いて説明する。
81 上金型
82 下金型
84 溝
85 吸引孔
90 封止樹脂
91 樹脂注入方向
100 フレーム
101 ダイパッド
101a ダイパッド上面(素子載置面)
101b ダイパッド下面
103 ボンディングリード
105 ワイヤ
110 サポートリード
111 開口
112 突出部
113 開口
114 突出部
121 開口
122 第2の突出部
131 窪み部
131a、131b、131c 空間
132 突出部
133 窪み部
133a 空間
900 フレーム
901 ダイパッド
903 ボンディングリード
905 ワイヤ
910 サポートリード
950 半導体素子
981 上金型
982 下金型
990 封止樹脂
991 注入方向
Claims (2)
- 半導体素子と、
前記半導体素子を一方の面に載置したダイパッドと、
前記ダイパッドを両側で支持し、前記ダイパッドと一体に形成されたサポートリードとを備えた半導体装置であって、
前記半導体素子、前記ダイパッド及び前記サポートリードが樹脂で封止され、
前記半導体素子が載置された面と反対側の面が前記半導体装置の樹脂表面近傍に配置され、
前記ダイパッドの、前記半導体素子が載置された面と反対側の面の外周部に窪み部が連続して形成されており、
前記窪み部は前記ダイパッドと前記サポートリードとの接続部分においても形成され、前記樹脂で前記窪み部が充填され、
前記窪み部と対向する部位には、前記半導体素子が載置されておらず、
前記半導体素子が載置されている面に対向する面は前記樹脂から露出していることを特徴とする半導体装置。 - 前記窪み部は階段状であることを特徴とする請求項1に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005004182A JP4418373B2 (ja) | 2005-01-11 | 2005-01-11 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005004182A JP4418373B2 (ja) | 2005-01-11 | 2005-01-11 | 半導体装置 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004168845A Division JP3647448B2 (ja) | 2004-06-07 | 2004-06-07 | 半導体装置及び半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005101670A JP2005101670A (ja) | 2005-04-14 |
JP4418373B2 true JP4418373B2 (ja) | 2010-02-17 |
Family
ID=34464653
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005004182A Expired - Fee Related JP4418373B2 (ja) | 2005-01-11 | 2005-01-11 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4418373B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5072911B2 (ja) * | 2009-07-02 | 2012-11-14 | 三菱電機株式会社 | 半導体装置 |
US8937374B2 (en) | 2011-12-22 | 2015-01-20 | Panasonic Corporation | Semiconductor package, method and mold for producing same, input and output terminals of semiconductor package |
-
2005
- 2005-01-11 JP JP2005004182A patent/JP4418373B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2005101670A (ja) | 2005-04-14 |
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