JP3531475B2 - Flip chip type optical semiconductor device - Google Patents
Flip chip type optical semiconductor deviceInfo
- Publication number
- JP3531475B2 JP3531475B2 JP14187398A JP14187398A JP3531475B2 JP 3531475 B2 JP3531475 B2 JP 3531475B2 JP 14187398 A JP14187398 A JP 14187398A JP 14187398 A JP14187398 A JP 14187398A JP 3531475 B2 JP3531475 B2 JP 3531475B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- optical semiconductor
- flip
- chip type
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 128
- 230000003287 optical effect Effects 0.000 title claims description 44
- 150000004767 nitrides Chemical class 0.000 claims description 56
- 229910052751 metal Inorganic materials 0.000 claims description 43
- 239000002184 metal Substances 0.000 claims description 43
- 239000000758 substrate Substances 0.000 claims description 38
- 230000001681 protective effect Effects 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 16
- 229920001721 polyimide Polymers 0.000 claims description 9
- 239000011248 coating agent Substances 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 8
- 239000004642 Polyimide Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 4
- 229910000484 niobium oxide Inorganic materials 0.000 claims description 4
- URLJKFSTXLNXLG-UHFFFAOYSA-N niobium(5+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Nb+5].[Nb+5] URLJKFSTXLNXLG-UHFFFAOYSA-N 0.000 claims description 4
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 4
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 4
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 4
- 239000010410 layer Substances 0.000 claims 15
- 239000011241 protective layer Substances 0.000 claims 1
- 239000010408 film Substances 0.000 description 55
- 239000007789 gas Substances 0.000 description 17
- 229910052594 sapphire Inorganic materials 0.000 description 17
- 239000010980 sapphire Substances 0.000 description 17
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 16
- 239000000853 adhesive Substances 0.000 description 8
- 230000001070 adhesive effect Effects 0.000 description 8
- 239000002019 doping agent Substances 0.000 description 8
- 229910052697 platinum Inorganic materials 0.000 description 8
- 238000005530 etching Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 238000004544 sputter deposition Methods 0.000 description 6
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 6
- 229910002601 GaN Inorganic materials 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 229910001873 dinitrogen Inorganic materials 0.000 description 4
- 239000002994 raw material Substances 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000005253 cladding Methods 0.000 description 3
- 125000005842 heteroatom Chemical group 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052749 magnesium Inorganic materials 0.000 description 2
- 239000011777 magnesium Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- 229910020068 MgAl Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910052790 beryllium Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052791 calcium Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 229910052711 selenium Inorganic materials 0.000 description 1
- 229910052596 spinel Inorganic materials 0.000 description 1
- 239000011029 spinel Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 229910052712 strontium Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Device Packages (AREA)
- Led Devices (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は各種インジケータや
光プリンタのプリンタヘッド用など種々の発光素子や太
陽電池などの受光素子として利用可能なフリップチップ
型光半導体素子に係わり、特に、駆動基板上への配置に
おいても位置精度に関わりなく短絡が極めて少ない高輝
度フリップチップ型光半導体素子に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-chip type optical semiconductor device that can be used as various light-emitting devices such as various indicators and printer heads of optical printers and light-receiving devices such as solar cells, and more particularly to a drive substrate. The present invention also relates to a high-brightness flip-chip type optical semiconductor element in which short circuits are extremely small regardless of the positional accuracy.
【０００２】[0002]
【従来技術】駆動基板の電極上にＬＥＤチップの電極を
直接、Ａｇペーストや半田などにより導通固定させるフ
リップチップ型光半導体素子がある。このようなＬＥＤ
チップは、導通を取るためにワイヤを用いる必要がな
く、比較的簡単な工程で比較的小型なＬＥＤチップを搭
載することができる。2. Description of the Related Art There is a flip-chip type optical semiconductor device in which an electrode of an LED chip is directly fixed on an electrode of a driving substrate by Ag paste or solder. LED like this
The chip does not need to use a wire for electrical conduction, and a relatively small LED chip can be mounted by a relatively simple process.
【０００３】このようなフリップチップ型光半導体素子
の模式的断面図を図４に示す。図４にはサファイア基板
４０４上にバッファ層４０５を介してｎ型窒化物半導
体、ｐ型窒化物半導体が形成されたＬＥＤチップが示さ
れている。半導体表面側から導通を取る為に半導体の一
部を除去してｐ型及びｎ型窒化物半導体の表面をそれぞ
れ露出させてある。ｐ型及びｎ型窒化物半導体の表面に
はそれぞれ各ｐ型電極４１１及びｎ型電極４１２を形成
してある。したがって、ｐ型電極４１１及びｎ型電極４
１２はそれぞれ同一平面側に形成されている。A schematic sectional view of such a flip-chip type optical semiconductor device is shown in FIG. FIG. 4 shows an LED chip in which an n-type nitride semiconductor and a p-type nitride semiconductor are formed on a sapphire substrate 404 via a buffer layer 405. In order to establish conduction from the semiconductor surface side, part of the semiconductor is removed to expose the surfaces of the p-type and n-type nitride semiconductors. The p-type electrode 411 and the n-type electrode 412 are formed on the surfaces of the p-type and n-type nitride semiconductors, respectively. Therefore, the p-type electrode 411 and the n-type electrode 4
12 are formed on the same plane side.
【０００４】ＬＥＤチップは予め駆動基板の電極パター
ン上にＡｇペーストなどを塗布した後、電極面を下にし
た状態でＬＥＤチップを配置させる。Ａｇペーストを硬
化させることで、ＬＥＤチップを固定すると共に駆動基
板の電極とＬＥＤチップの各電極との導通を取ることが
できる。For the LED chip, Ag paste or the like is applied on the electrode pattern of the driving substrate in advance, and then the LED chip is arranged with the electrode surface facing down. By curing the Ag paste, the LED chip can be fixed and the electrodes of the drive substrate and the electrodes of the LED chip can be electrically connected.
【０００５】ＬＥＤチップは一片が３５０μｍ以下でＬ
ＥＤチップ上の電極は一辺が約１００μｍ程度と極めて
小さな場合がある。この場合、ＬＥＤチップをダイボン
ド機器を用いて精度良く配置させることが難しい。ま
た、上述のフリップチップ型光半導体素子は同一面側に
異なる極性を持った半導体接合が露出形成される場合が
ある。そのため、Ａｇペーストなどを介してＬＥＤチッ
プの電極と駆動基板の電極パターンとを接続する場合、
ＬＥＤチップの配置ずれによりＡｇペーストが半導体接
合間をショートしてしまう場合がある。また、Ａｇペー
ストの粘度、ＬＥＤチップ表面との表面張力によりＡｇ
ペーストが半導体接合箇所まで這い上がり、同様に半導
体接合間を短絡してしまう場合がある。短絡は発光輝度
の低下のみならず発光素子の破壊を生ずる。このよう
な、短絡は電極表面を除いて酸化珪素などの保護膜４０
１を形成させることによりある程度制御することができ
る。One piece of the LED chip is 350 μm or less and L
The electrodes on the ED chip may be extremely small with a side of about 100 μm. In this case, it is difficult to accurately arrange the LED chips using a die bond device. Further, in the above flip-chip type optical semiconductor device, semiconductor junctions having different polarities may be exposed and formed on the same surface side. Therefore, when the electrodes of the LED chip and the electrode pattern of the drive substrate are connected via Ag paste or the like,
The Ag paste may short-circuit between the semiconductor junctions due to the displacement of the LED chips. In addition, Ag viscosity depends on the viscosity of the paste and the surface tension with the LED chip surface.
The paste may crawl up to the semiconductor junctions and similarly short-circuit between the semiconductor junctions. The short circuit not only lowers the light emission brightness but also damages the light emitting element. Such a short circuit is caused by a protective film 40 such as silicon oxide except for the electrode surface.
By forming 1, it is possible to control to some extent.
【０００６】しかしながら、より小型化かつ歩留まりの
高い光半導体素子が求められる現在においては十分では
なく、更なる改良が求められている。特に、絶縁性被膜
を成膜させると短絡を生ずる数が減るものの、いまだ十
分な歩留まりがあるフリップチップ型光半導体素子とす
ることができなかった。したがって、本発明はより短絡
の少ない高輝度発光可能なフリップチップ型光半導体素
子を提供することを目的とする。However, it is not sufficient at present when there is a demand for a more compact and high-yield optical semiconductor element, and further improvement is required. In particular, when the insulating film is formed, the number of short circuits is reduced, but a flip chip type optical semiconductor device having a sufficient yield has not yet been obtained. Therefore, an object of the present invention is to provide a flip-chip type optical semiconductor device capable of emitting high-luminance light with less short circuit.
【０００７】[0007]
【課題を解決するための手段】本発明は透光性絶縁基板
に形成された窒化物半導体の同一平面側に正と負の電極
が設けられ、該電極表面の露出部を除いて窒化物半導体
層表面を被覆した保護膜を有するフリップチップ型光半
導体素子である。特に、保護膜は絶縁性被膜からなる第
１層と、第１層上の金属層と、金属層上に絶縁性被膜か
らなる第２層の少なくとも３層構造からなる。According to the present invention, positive and negative electrodes are provided on the same plane side of a nitride semiconductor formed on a translucent insulating substrate, and the nitride semiconductor is formed except for an exposed portion of the electrode surface. It is a flip-chip type optical semiconductor device having a protective film covering the layer surface. In particular, the protective film has at least a three-layer structure of a first layer made of an insulating film, a metal layer on the first layer, and a second layer made of an insulating film on the metal layer.
【０００８】これにより、制御性よく絶縁被膜を半導体
接合部等に形成することができると共にフリップチップ
型光半導体素子の電気的接続時においても極めて短絡の
少ないものとし得る。即ち、金属層（合金を含む）を形
成させることにより、導電性ペーストを構成する導電性
部材が絶縁性被膜を介して進入することを防ぎ短絡を防
止することができる。また、発光素子で放出された発光
波長を効率よく外部に放出させることができる、或いは
外部からの光を半導体に効率よく吸収できる受光素子と
することができる。As a result, the insulating coating can be formed on the semiconductor junction portion and the like with good controllability, and at the time of electrical connection of the flip-chip type optical semiconductor element, the number of short circuits can be extremely reduced. That is, by forming the metal layer (including the alloy), it is possible to prevent the conductive member forming the conductive paste from entering through the insulating film and prevent a short circuit. Further, it is possible to provide a light receiving element capable of efficiently emitting the emission wavelength emitted by the light emitting element to the outside, or capable of efficiently absorbing light from the outside into the semiconductor.
【０００９】本発明の請求項２に記載の構成は、第１層
及び／又は第２層が酸化珪素、酸化チタン、酸化ニオ
ブ、酸化ハフニウム、酸化アルミニウム、酸化ジルコニ
ウム、窒化珪素及びポリイミドから選択される少なくと
も一種である。これにより、より信頼性の高いフリップ
チップ型光半導体素子とすることができる。According to a second aspect of the present invention, the first layer and / or the second layer is selected from silicon oxide, titanium oxide, niobium oxide, hafnium oxide, aluminum oxide, zirconium oxide, silicon nitride and polyimide. At least one. Thereby, a more reliable flip-chip type optical semiconductor element can be obtained.
【００１０】本発明の請求項１に記載に追加の構成は、
金属層が電極の一部を構成するものである。これによ
り、比較的簡単な構成で保護膜の工程を簡略化しつつ信
頼性の高いフリップチップ型光半導体素子とすることが
できる。An additional configuration according to claim 1 of the present invention is as follows.
The metal layer constitutes a part of the electrode. This makes it possible to provide a highly reliable flip-chip type optical semiconductor device with a relatively simple structure while simplifying the process of forming the protective film.
【００１１】[0011]
【発明の実施の形態】本発明者は種々の実験の結果、窒
化物半導体素子上を被覆する被膜を特定構造とすること
により、信頼性の高いフリップチップ型光半導体素子と
しうることを見出し本発明を成すに至った。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As a result of various experiments, the present inventor has found that a highly reliable flip-chip type optical semiconductor device can be obtained by forming a film covering the nitride semiconductor device with a specific structure. Invented the invention.
【００１２】即ち、無機絶縁膜は緻密で欠陥のない薄膜
を形成することが難しいこと、及びフリップチップ型光
半導体素子の電気的接続に使用される導電性接着剤によ
り短絡すると考えられる。より具体的には導電性接着剤
を構成するＡｇなどの導電性部材は、周辺環境の水分等
によりイオン化される。イオン化された金属は、窒化物
半導体との通電に伴い無機絶縁膜内をマイグレーション
して短絡を生ずる場合がある。短絡に伴い半導体の機能
低下ばかりでなく、半導体素子が破壊される場合もあ
る。特に、半導体接合部での短絡は、窒化物半導体素子
に特に大きな影響を与えると考えられる。本発明は絶縁
膜間に金属膜を挟み込む保護膜の構成とすることによ
り、絶縁部材を通して半導体接合部などに形成される短
絡を防止し得るものである。なお、このような問題は発
光素子のみならず受光素子においても同様な問題であ
る。That is, it is considered that it is difficult to form a dense, defect-free thin film for an inorganic insulating film, and a short circuit occurs due to a conductive adhesive used for electrical connection of flip-chip type optical semiconductor elements. More specifically, a conductive member such as Ag that constitutes the conductive adhesive is ionized by moisture in the surrounding environment. The ionized metal may migrate in the inorganic insulating film due to the energization with the nitride semiconductor to cause a short circuit. Due to the short circuit, not only the function of the semiconductor is deteriorated but also the semiconductor element may be destroyed. In particular, it is considered that the short circuit at the semiconductor junction has a particularly large influence on the nitride semiconductor device. The present invention can prevent a short circuit formed at a semiconductor junction or the like through an insulating member by forming a protective film in which a metal film is sandwiched between insulating films. It should be noted that such a problem applies not only to the light emitting element but also to the light receiving element.
【００１３】以下、本発明の具体的実施態様例について
図１を用いて説明する。図１には、サファイア基板１０
４上にｎ型窒化物半導体、ｐ型窒化物半導体をそれぞれ
成膜させた後、ｐ型窒化物半導体を部分的にエッチング
させｎ型窒化物半導体層の表面まで露出させる。ｐ型及
びｎ型窒化物半導体上に電極１１０、１１１、１１２を
形成させた後、プラズマＣＶＤ法により酸化珪素を全面
に成膜する。酸化珪素をマスクを利用したエッチングに
より、電極表面の一部を露出させ第１層１０１としての
絶縁膜を形成させた。次に、白金をスパッタリング法に
より成膜させ、第１層上に金属層１０２を形成させる。
さらに、第１層１０１と同様にして、酸化珪素をプラズ
マＣＶＤ法により絶縁性の第２層１０３として成膜させ
三層構成の保護膜を形成させた。形成させたフリップチ
ップ型光半導体素子の電極と、駆動回路基板の電極パタ
ーンとをＣｕ含有のエポキシ樹脂を用いて電気的に接続
させた。駆動回路から電流を供給するとＬＥＤチップが
発光する。ＬＥＤチップからの光はサファイアを直接透
過して外部に取り出させるものの他、保護膜を形成する
金属層により反射されサファイア取り出されるものがあ
る。そのため、ＬＥＤチップからの発光波長を高効率で
放出することができる。以下、本発明の各構成について
詳述する。A specific embodiment of the present invention will be described below with reference to FIG. FIG. 1 shows a sapphire substrate 10
After the n-type nitride semiconductor and the p-type nitride semiconductor are formed on 4 respectively, the p-type nitride semiconductor is partially etched to expose the surface of the n-type nitride semiconductor layer. After forming the electrodes 110, 111 and 112 on the p-type and n-type nitride semiconductors, a silicon oxide film is formed on the entire surface by a plasma CVD method. By etching using silicon oxide as a mask, a part of the electrode surface was exposed to form an insulating film as the first layer 101. Next, platinum is deposited by a sputtering method to form the metal layer 102 on the first layer.
Further, as in the case of the first layer 101, silicon oxide was deposited as the insulating second layer 103 by a plasma CVD method to form a protective film having a three-layer structure. The electrodes of the formed flip-chip type optical semiconductor element and the electrode patterns of the drive circuit board were electrically connected using a Cu-containing epoxy resin. When current is supplied from the drive circuit, the LED chip emits light. Light emitted from the LED chip may be directly transmitted through sapphire and extracted outside, or may be extracted by sapphire reflected by a metal layer forming a protective film. Therefore, the emission wavelength from the LED chip can be emitted with high efficiency. Hereinafter, each configuration of the present invention will be described in detail.
【００１４】（保護膜）本発明の保護膜は、少なくとも
絶縁性被膜からなる第１層１０１、金属層１０２、絶縁
性被膜１０３からなる第２層で構成されている。特に、
保護膜は少なくとも光半導体素子の半導体接合部をフリ
ップチップ型光半導体素子の導通時に利用される導電性
ペーストや半田などの接触から防止するものである。し
たがって、各層は以下の如き特性を持っていることが好
ましい。(Protective Film) The protective film of the present invention comprises at least a first layer 101 made of an insulating coating, a metal layer 102, and a second layer made of an insulating coating 103. In particular,
The protective film prevents at least the semiconductor junction of the optical semiconductor element from coming into contact with a conductive paste or solder used when the flip-chip type optical semiconductor element is conducted. Therefore, each layer preferably has the following characteristics.
【００１５】（第１層１０１、２０１、３０１）第１層
としては窒化物半導体と接して形成することができるた
め、窒化物半導体との密着性が良いものが好ましい。ま
た、第１層１０１上に金属層１０２を形成するために絶
縁性の高い絶縁膜が好ましい。第１層１０１は発光素子
が発光する波長を効率よく反射する或いは、受光素子が
受光する波長に対して効率よく反射することで光利用効
率を高めることができる。具体的には、第１層１０１の
膜厚を発光素子の発光波長や受光素子の受光波長に対し
１／４倍の厚さとすることで反射率を向上させることが
できる。また、発光素子から放出された発光波長を金属
層１０２で反射させる場合は、第１層１０１が少なくと
も発光素子から放出される発光波長や受光素子で受光さ
れる受光波長に対して透光性の高い層とすることが好ま
しい。(First Layer 101, 201, 301) Since the first layer can be formed in contact with the nitride semiconductor, it is preferable that the first layer has good adhesion to the nitride semiconductor. In addition, an insulating film having a high insulating property is preferable because the metal layer 102 is formed on the first layer 101. The first layer 101 can efficiently reflect the wavelength of light emitted by the light emitting element or efficiently reflect the wavelength of light received by the light receiving element, thereby improving the light utilization efficiency. Specifically, the reflectance can be improved by setting the film thickness of the first layer 101 to 1/4 times the light emitting wavelength of the light emitting element or the light receiving wavelength of the light receiving element. When the light emission wavelength emitted from the light emitting element is reflected by the metal layer 102, the first layer 101 is transparent to at least the light emission wavelength emitted from the light emitting element and the light receiving wavelength received by the light receiving element. Higher layers are preferred.
【００１６】このような第１層１０１に用いられる材料
としては、酸化珪素、酸化チタン、酸化ニオブ、酸化ハ
フニウム、酸化アルミニウム、酸化ジルコニウム及び窒
化珪素などの金属酸化物や金属窒化物、さらにはポリイ
ミドなどの樹脂が好適に挙げられる。第１層１０１が無
機絶縁膜の場合はスパッタリング法や各種ＣＶＤ法など
を利用することにより、小型な光半導体素子においても
制御性よく形成することができる。特に、緻密な無機絶
縁膜を成膜させるためはプラズマＣＶＤ法を利用するこ
とが好ましい。Materials used for the first layer 101 include metal oxides and metal nitrides such as silicon oxide, titanium oxide, niobium oxide, hafnium oxide, aluminum oxide, zirconium oxide and silicon nitride, and further polyimide. Resins such as When the first layer 101 is an inorganic insulating film, it can be formed with good controllability even in a small optical semiconductor element by utilizing a sputtering method or various CVD methods. In particular, it is preferable to use the plasma CVD method for forming a dense inorganic insulating film.
【００１７】（金属層１０２、２０２、３０２）金属層
１０２は導電時に保護膜を構成する第２層１０３を介し
て進入する外部などからの金属イオンなどを実質的に防
止する働きをするものである。金属層１０２は、スパッ
タリング法や真空蒸着法などにより薄膜、かつ制御性良
く形成することができる他、欠陥の少ない膜として形成
しやすい。また、第１層１０１を透過した波長を効率よ
く反射する金属（合金や積層物を含む）を選択すること
により、集光性等を高め光取りだし効率を高めることが
できる。(Metal layers 102, 202, 302) The metal layer 102 has a function of substantially preventing metal ions or the like from the outside that enter through the second layer 103 constituting the protective film during conduction. is there. The metal layer 102 can be formed as a thin film with good controllability by a sputtering method, a vacuum evaporation method, or the like, and can be easily formed as a film with few defects. In addition, by selecting a metal (including an alloy or a laminate) that efficiently reflects the wavelength that has passed through the first layer 101, it is possible to improve the light-collecting property and the light extraction efficiency.
【００１８】このような金属層１０２は外部からのイオ
ンの進入を止める。或いは、導電性ペースト、導電性ペ
ーストを構成するフィラや半田の進入を防止しうるもの
であれば種々の金属でも選択することができる。金属層
の具体的材料としては、ニッケル、白金、金、アルミニ
ウム、タングステン、モリブデンやこれらの合金や積層
物が好適に挙げられる。Such a metal layer 102 blocks the entry of ions from the outside. Alternatively, various metals can be selected as long as they can prevent the conductive paste, the filler forming the conductive paste, and the solder from entering. Preferable examples of specific materials for the metal layer include nickel, platinum, gold, aluminum, tungsten, molybdenum, and alloys and laminates thereof.
【００１９】金属層はイオンマイグレーションを好適に
防止しうるものであるため、金属層自体がイオン化し難
いものが好ましい。特に、銀は、導電性が高く、窒化物
半導体のバンドギャップに対応する光に対して反射性は
よい。しかし、イオンマイグレーションを起こしやすい
銀を除いた金属元素で構成することが好ましい。また、
金属層１０２の厚みは発光素子からの発光波長を反射及
び小型化などを考慮すると百Åから数ミクロン程度の厚
みで形成することが好ましい。金属層１０２は短絡しな
い限り、窒化物半導体の全周を被覆するように形成して
も良いし、複数に分割した形状で形成することもでき
る。Since the metal layer can prevent ion migration, it is preferable that the metal layer itself is difficult to ionize. In particular, silver has high conductivity and good reflectivity for light corresponding to the band gap of a nitride semiconductor. However, it is preferable to be composed of a metal element excluding silver, which easily causes ion migration. Also,
The thickness of the metal layer 102 is preferably about 100 to several microns in consideration of reflection of the wavelength of light emitted from the light emitting element and miniaturization. The metal layer 102 may be formed so as to cover the entire circumference of the nitride semiconductor as long as it does not short circuit, or may be formed in a shape divided into a plurality of parts.
【００２０】複数に分割された場合、ｐ型或いはｎ型の
電極の一部を構成することもできる。これにより、電極
形成と同時に金属層３０２を形成することができる。そ
のため複数のマスクとエッチング工程を簡略して、工程
数を低減することができる。このような金属層３０２と
して具体的にはｐ型窒化物半導体の電極として機能させ
る場合は、オーミック接触等を考慮して、ニッケル、コ
バルト、金や白金などの金属元素で構成されていること
が好ましい。同様に、ｎ型窒化物半導体の電極としても
機能させる場合は、タングステン、アルミニウムやチタ
ンなどの金属元素で構成されていることが好ましい。さ
らに、窒化物半導体を活性層を介してダブルへテロ構造
としたＬＥＤに利用した場合、活性層の端面から放出さ
れる光が特に多いことから活性層を絶縁層を介した金属
層で被覆することにより、発光効率をより向上させるこ
とができる。When divided into a plurality of parts, a part of the p-type or n-type electrode can be formed. Thereby, the metal layer 302 can be formed at the same time when the electrodes are formed. Therefore, the plurality of masks and the etching process can be simplified and the number of processes can be reduced. When specifically functioning as such a metal layer 302 as an electrode of a p-type nitride semiconductor, it may be composed of a metal element such as nickel, cobalt, gold or platinum in consideration of ohmic contact. preferable. Similarly, when functioning as an electrode of an n-type nitride semiconductor, it is preferably composed of a metal element such as tungsten, aluminum or titanium. Furthermore, when a nitride semiconductor is used for an LED having a double hetero structure with an active layer interposed, the active layer is covered with a metal layer via an insulating layer because the light emitted from the end face of the active layer is particularly large. As a result, the luminous efficiency can be further improved.
【００２１】（第２層１０３）第２層１０３は金属層１
０２を被覆する絶縁被膜であり外部と窒化物半導体とを
電気的に絶縁するために設けられるものである。したが
って、金属層１０２上に直接形成される場合は金属層１
０２と密着性がよく絶縁性が高いことが求められる。第
２層１０３に用いられる材料としては、第１層１０１と
同様、種々の金属酸化物、金属窒化物などの無機物質の
他、有機樹脂を種々選択することができる。より具体的
には、酸化珪素、酸化チタン、酸化ニオブ、酸化ハフニ
ウム、酸化アルミニウム、酸化ジルコニウム、窒化珪素
及びポリイミド樹脂などを好適に挙げることができる。
第２層１０３が無機絶縁膜の場合は緻密に形成させるほ
ど短絡の傾向が減少するが、緻密に形成させるためには
成膜時間がかかる傾向にある。(Second Layer 103) The second layer 103 is the metal layer 1
It is an insulating film for covering 02 and is provided to electrically insulate the outside from the nitride semiconductor. Therefore, when directly formed on the metal layer 102, the metal layer 1
No. 02 is required to have good adhesion and high insulation. As the material used for the second layer 103, as with the first layer 101, various organic materials can be selected in addition to inorganic materials such as various metal oxides and metal nitrides. More specifically, suitable examples include silicon oxide, titanium oxide, niobium oxide, hafnium oxide, aluminum oxide, zirconium oxide, silicon nitride, and polyimide resin.
If the second layer 103 is an inorganic insulating film, the tendency of short-circuiting decreases as it is densely formed, but it tends to take a long time to form it densely.
【００２２】一方、第２層１０３はフリップチップ型光
半導体素子の最外郭に配置される場合がある。このよう
な、第２層１０３の場合は実装時における保護膜の損傷
を防止するため、ポリイミドなどの絶縁性有機物質を使
用することもできる。これにより、信頼性を更に向上さ
せることもできる。具体的には、窒化物半導体は、サフ
ァイア基板などの上に形成させた後、粘着シート上でス
クライブなどにより個々の窒化物半導体素子に分割され
る。分割された窒化物半導体素子が取り上げ可能なよう
に粘着シートをのばし、粘着シート下部から突き上げピ
ンによって個々の半導体素子を突き上げ、コレットに吸
着する。他方、搭載させる駆動基板側の電極にＡｇペー
ストなどの導電性ペーストを塗布する。コレットによっ
て吸着した窒化物半導体素子を導電性ペースト上に乗
せ、導電性接着剤を硬化させる。これによって、所望の
駆動基板上などに窒化物半導体素子を配置固定すること
ができる。On the other hand, the second layer 103 may be arranged at the outermost part of the flip-chip type optical semiconductor device. In the case of the second layer 103, an insulating organic material such as polyimide may be used in order to prevent damage to the protective film during mounting. Thereby, the reliability can be further improved. Specifically, a nitride semiconductor is formed on a sapphire substrate or the like and then divided into individual nitride semiconductor elements by scribe or the like on an adhesive sheet. An adhesive sheet is extended so that the divided nitride semiconductor elements can be picked up, and individual semiconductor elements are pushed up from the bottom of the adhesive sheet by push-up pins and adsorbed to the collet. On the other hand, a conductive paste such as Ag paste is applied to the electrodes on the side of the drive substrate to be mounted. The nitride semiconductor element adsorbed by the collet is placed on the conductive paste, and the conductive adhesive is cured. As a result, the nitride semiconductor device can be arranged and fixed on a desired driving substrate or the like.
【００２３】窒化物半導体素子の場合、比較的硬いサフ
ァイア基板などの上に窒化物半導体が形成される。その
ため、基板側においては比較的強度が高いものの、コレ
ットで吸着させる際、突き上げピンは絶縁被膜を形成さ
せた電極面側を突き上げる。そして半導体面（サファイ
ア基板に対して窒化物半導体側）を配線基板の導電部に
導電性接着剤を介してフリップチップボンディングさせ
る。In the case of a nitride semiconductor device, the nitride semiconductor is formed on a relatively hard sapphire substrate or the like. Therefore, although the substrate has relatively high strength, the push-up pin pushes up the electrode surface side on which the insulating coating is formed when adsorbing with the collet. Then, the semiconductor surface (nitride semiconductor side with respect to the sapphire substrate) is flip-chip bonded to the conductive portion of the wiring substrate via a conductive adhesive.
【００２４】この場合、短絡不良を防止するために窒化
物半導体面、窒化物半導体端面及び露出している基板面
等に絶縁膜を形成しているにも関わらず、短絡不良の発
生率がかなり高くなる傾向がある。この原因として、発
光面が基板面の時は基板が硬いために突き上げピンによ
って傷や割れが発生し難い。特に、窒化物半導体面側を
突き上げピンによって突き上げる場合は、保護膜に傷や
割れ等が発生し易くなるために短絡の発生率が高いもの
と考えられる。In this case, although the insulating film is formed on the nitride semiconductor surface, the nitride semiconductor end surface, the exposed substrate surface, etc. in order to prevent the short circuit failure, the occurrence rate of the short circuit failure is considerably high. Tends to be high. As a cause of this, when the light emitting surface is the surface of the substrate, the substrate is hard, so that the push-up pin is unlikely to cause scratches or cracks. In particular, when the nitride semiconductor surface side is pushed up by the push-up pin, it is considered that the occurrence rate of short circuit is high because the protective film is likely to be damaged or cracked.
【００２５】そこで、有機樹脂による絶縁被膜を特に第
２層１０３として形成させた場合はフリップチップボン
ディング形式の窒化物半導体素子において、突き上げピ
ンによる窒化物半導体面の傷及び絶縁膜の割れを防止
し、短絡不良がなく信頼性の高い窒化物半導体素子とす
ることができる。Therefore, when an insulating film made of an organic resin is formed as the second layer 103 in particular, in a nitride semiconductor element of the flip chip bonding type, scratches on the nitride semiconductor surface due to push-up pins and cracks in the insulating film are prevented. It is possible to obtain a highly reliable nitride semiconductor element without a short circuit defect.
【００２６】即ち、第２層１０３を有機絶縁膜とするこ
とにより、配線基板への実装時における粘着シート下部
からの突き上げピンの物理的衝撃を緩和し、短絡の原因
となる絶縁膜の割れ等を効果的に防止できるものであ
る。このような、第２層１０３にポリイミド系薄膜を利
用した場合における具体的な膜厚は、突き上げピンで突
き上げた時に受ける物理的力の緩和、及び絶縁膜の耐圧
の点で１〜１０μｍとすることが好ましい。また、ポリ
イミド系薄膜の発光主波長における透過率が６０％以下
であると、窒化物半導体素子端面からの漏光を抑制、光
学特性のばらつきの軽減される。そのため、配光特性の
安定性が得られるためより好ましい。That is, by using the organic insulating film as the second layer 103, the physical impact of the push-up pin from the lower part of the adhesive sheet at the time of mounting on the wiring board is mitigated, and the insulating film causing a short circuit or the like. Can be effectively prevented. When a polyimide-based thin film is used for the second layer 103, the specific film thickness is set to 1 to 10 μm in terms of the relaxation of the physical force received by the push-up pin and the breakdown voltage of the insulating film. It is preferable. When the transmittance of the polyimide-based thin film at the dominant wavelength of light emission is 60% or less, light leakage from the end surface of the nitride semiconductor element is suppressed and variations in optical characteristics are reduced. Therefore, the stability of the light distribution characteristics can be obtained, which is more preferable.
【００２７】（光半導体素子）本発明の光半導体素子
は、窒化物半導体からなる受光素子や発光素子である。
透光性絶縁基板上に形成され少なくとも半導体接合を有
する窒化物半導体により構成することができる。具体的
には、透光性絶縁基板上にＭＯＣＶＤ法やＨＶＰＥ法を
用いて窒化物半導体を形成させることができる。このよ
うな透光性絶縁基板としては、窒化ガリウム、サファイ
ア（Ａｌ2Ｏ3）やスピネル（ＭｇＡｌ2Ｏ4）などが挙げ
られる。半導体接合としては、ＭＩＳ接合、ＰＩＮ接合
の他、ｐｎ接合が挙げられる。また、光半導体素子の特
性により、ホモやダブルへテロ構造とすることができ
る。さらに、単一量子井戸構造や多重量子井戸構造とす
ることもできる。(Optical Semiconductor Element) The optical semiconductor element of the present invention is a light receiving element or a light emitting element made of a nitride semiconductor.
A nitride semiconductor formed on a translucent insulating substrate and having at least a semiconductor junction can be used. Specifically, a nitride semiconductor can be formed over a light-transmitting insulating substrate by an MOCVD method or an HVPE method. Examples of such a translucent insulating substrate include gallium nitride, sapphire (Al 2 O 3 ) and spinel (MgAl 2 O 4 ). Examples of the semiconductor junction include a pn junction as well as a MIS junction and a PIN junction. Further, depending on the characteristics of the optical semiconductor element, a homo or double hetero structure can be obtained. Further, a single quantum well structure or a multiple quantum well structure can be used.
【００２８】ｐｉｎ接合やｐｎ接合が短絡することで、
半導体特性に大きな損傷が加わる。そのため、本発明が
有効に働くことになる。半導体の材料やその混晶度によ
って光半導体素子の発光波長及び受光波長を紫外光から
赤色領域まで種々選択することができる。By short-circuiting the pin junction and the pn junction,
Greatly damages semiconductor characteristics. Therefore, the present invention works effectively. The emission wavelength and the reception wavelength of the optical semiconductor element can be variously selected from the ultraviolet light to the red region depending on the material of the semiconductor and the mixed crystallinity thereof.
【００２９】なお結晶性の良い窒化物半導体を形成させ
るためにはサファイヤ基板を用いることが好ましい。こ
のサファイヤ基板上に格子不整合緩和のためにＧａＮ、
ＡｌＮ等のバッファー層を形成しその上にｐｎ接合など
を有する窒化物半導体を形成させることにより半導体特
性の優れた発光素子や受光素子を構成させることができ
る。サファイアで基板を形成させると硬度が高く、基板
自体が透光性を持つと共に外部からの水分等の進入を防
ぐことができるため特に好ましい。A sapphire substrate is preferably used to form a nitride semiconductor having good crystallinity. GaN on the sapphire substrate for relaxing the lattice mismatch,
By forming a buffer layer of AlN or the like and forming a nitride semiconductor having a pn junction or the like on the buffer layer, a light emitting element or a light receiving element having excellent semiconductor characteristics can be formed. It is particularly preferable to form the substrate with sapphire because the hardness is high, the substrate itself has a light-transmitting property, and moisture or the like can be prevented from entering from the outside.
【００３０】窒化物半導体は、不純物をドープしない状
態でｎ型導電性を示すが、ｎ型ドーパントとしてＳｉ、
Ｇｅ、Ｓｅ、Ｔｅ、Ｓｎ等を適宜導入することが好まし
い。また、ｎ型ドーパントと微量のｐ型ドーパントとを
ドーピングしたダブルドーピングすることもできる。こ
れらのドーパントの種類とドーピング量を変えることに
よってキヤリア密度を制御し電気抵抗を下げることがで
きる。一方、ｐ型窒化物半導体を形成させる場合は、ｐ
型ドーパントであるＺｎ、Ｍｇ、Ｂｅ、Ｃａ、Ｓｒ、Ｂ
ａ等をドープさせる。窒化ガリウム半導体は、ｐ型ドー
パントをドープしただけでは低抵抗化しにくいためｐ型
ドーパント導入後に、低速電子線照射、プラズマ照射や
熱処理等させることで低抵抗化処理することができる。The nitride semiconductor shows n-type conductivity in a state where impurities are not doped, but Si as an n-type dopant is used.
It is preferable to appropriately introduce Ge, Se, Te, Sn and the like. Further, double doping in which an n-type dopant and a small amount of p-type dopant are doped can be performed. By changing the kind and doping amount of these dopants, the carrier density can be controlled and the electric resistance can be lowered. On the other hand, when forming a p-type nitride semiconductor, p
Type dopants Zn, Mg, Be, Ca, Sr, B
Dope a etc. Since it is difficult to reduce the resistance of a gallium nitride semiconductor simply by doping it with a p-type dopant, it is possible to reduce the resistance by performing low-speed electron beam irradiation, plasma irradiation, heat treatment, or the like after the introduction of the p-type dopant.
【００３１】半導体露出面側に一対の電極を形成するた
めには各半導体を所望の形状にエッチングしてあること
が好ましい。エッチングとしては、ドライエッチング
や、ウエットエッチングがある。ドライエッチングとし
ては例えば反応性イオンエッチング、イオンミリング、
集束ビームエッチング、ＥＣＲエッチング等が挙げられ
る。又、ウエットエッチングとしては、硝酸と燐酸の混
酸を用いることができる。ただし、エッチングを行う前
に所望の形状に窒化珪素や酸化珪素等の材料を用いてマ
スクを形成することは言うまでもない。以下、本発明の
実施例について詳述するがこれのみに限定されるもので
ないことはいうまでもない。In order to form a pair of electrodes on the semiconductor exposed surface side, each semiconductor is preferably etched into a desired shape. Examples of etching include dry etching and wet etching. Examples of dry etching include reactive ion etching, ion milling,
Focused beam etching, ECR etching, etc. are mentioned. For wet etching, a mixed acid of nitric acid and phosphoric acid can be used. However, it goes without saying that a mask is formed into a desired shape using a material such as silicon nitride or silicon oxide before etching. Hereinafter, examples of the present invention will be described in detail, but it goes without saying that the present invention is not limited thereto.
【００３２】[0032]
【実施例】（実施例１）洗浄されたサファイアのＣ面を
成膜表面としてＭＯＣＶＤ法を用いて窒化物半導体を成
膜した。成膜装置内にサファイア基板１０４を配置し６
５０℃に加熱すると共に、ＴＭＧ（トリメチルガリウ
ム）ガス、窒素ガスを原料ガス、水素ガスをキャリアガ
スとして流しバッファ層１０５を形成させた。一旦、原
料ガスの導入を止めた後、成膜温度を１１５０℃に上げ
ＴＭＧガス、窒素ガス、水素ガスにｎ型ドーパントガス
としてシランを加えて厚さ５μｍのｎ型窒化ガリウム層
１０６を成膜した。次に、ＴＭＧガスの供給を停止し、
成膜温度を８００℃に低下させた後、ＴＭＧガス、ＴＭ
Ａ（トリメチルアルミニウム）ガス、窒素ガス及び水素
ガスを供給させて厚さ３ｎｍの窒化インジウムガリウム
を発光層１０７として成膜させた。EXAMPLES Example 1 A nitride semiconductor was deposited by MOCVD using the cleaned C surface of sapphire as the deposition surface. The sapphire substrate 104 is placed in the film forming apparatus, and
While being heated to 50 ° C., TMG (trimethylgallium) gas and nitrogen gas were used as raw material gases and hydrogen gas as a carrier gas to form the buffer layer 105. After stopping the introduction of the raw material gas, the film formation temperature is raised to 1150 ° C. and silane is added as an n-type dopant gas to TMG gas, nitrogen gas and hydrogen gas to form an n-type gallium nitride layer 106 having a thickness of 5 μm. did. Next, stop the supply of TMG gas,
After lowering the film forming temperature to 800 ° C., TMG gas, TM
A (trimethylaluminum) gas, nitrogen gas, and hydrogen gas were supplied to deposit indium gallium nitride with a thickness of 3 nm as a light-emitting layer 107.
【００３３】次に、原料ガスの供給を停止して成膜温度
を１０５０℃に上げた後、再び原料ガスとしてＴＭＧガ
ス、ＴＭＡガス、窒素ガス、キャリアガスとして水素ガ
ス、不純物ガスとしてシクロペンタジエチルマグネシウ
ムを加えて厚さ３００Åのｐ型クラッド層１０８を成膜
させる。Next, after stopping the supply of the raw material gas and raising the film forming temperature to 1050 ° C., TMG gas, TMA gas, nitrogen gas as the raw material gas, hydrogen gas as the carrier gas, and cyclopentadiethyl as the impurity gas. Magnesium is added to form a p-type clad layer 108 having a thickness of 300Å.
【００３４】ｐ型クラッド層１０８上にＴＭＡガスの供
給を停止した以外はｐ型クラッド層の形成と同様にして
厚さ１５００Åのｐ型コンタクト層１０９を成膜させ
る。（なお、ｐ型窒化物半導体となる半導体層は成膜後
４００℃以上で熱処理してある。）こうして活性層を介
してダブルへテロ構造である窒化物半導体を成膜した。
半導体ウエハの同一面側に電極を形成させるため、マス
クを利用して、活性層、ｐ型クラッド層、ｐ型コンタク
ト層を一部残しつつｎ型コンタクト層まで、部分的にエ
ッチングさせてある。同様に各ＬＥＤチップとして分離
できる大きさでサファイア基板上までそれぞれエッチン
グしてある。エッチング後、サファイア基板上には島状
の窒化物半導体層が形成されることとなる。A p-type contact layer 109 having a thickness of 1500 Å is formed on the p-type clad layer 108 in the same manner as the p-type clad layer except that the supply of TMA gas is stopped. (Note that the semiconductor layer to be a p-type nitride semiconductor is heat-treated at 400 ° C. or higher after film formation.) Thus, a nitride semiconductor having a double hetero structure is formed through the active layer.
In order to form electrodes on the same side of the semiconductor wafer, a mask is used to partially etch the n-type contact layer while leaving the active layer, the p-type cladding layer, and the p-type contact layer. Similarly, each LED chip is etched to a size such that it can be separated to the sapphire substrate. After etching, an island-shaped nitride semiconductor layer will be formed on the sapphire substrate.
【００３５】ｐ型コンタクト層１０９と接触し全面を被
覆する電極１１０として白金を５００Åでスパッタリン
グ法を用いて成膜した。この電極１１０上には、１００
μｍ角のｐ型電極１１１として白金を０．７μｍで成膜
した。ｎ型コンタクト層１０６上には直径１００μｍの
ｎ型電極１１２としてタングステン／アルミニウムを２
００Å／０．７μｍとして成膜した。これによって、島
状の窒化物半導体上には同一平面側に正負一対の電極１
１１、１１２が形成されたことになる。A platinum film was formed as an electrode 110 in contact with the p-type contact layer 109 so as to cover the entire surface with 500 Å by a sputtering method. On this electrode 110, 100
A 0.7 μm platinum film was formed as a p-type electrode 111 having a square shape. On the n-type contact layer 106, tungsten / aluminum is used as the n-type electrode 112 having a diameter of 100 μm.
The film was formed with a thickness of 00Å / 0.7 μm. As a result, a pair of positive and negative electrodes 1 are formed on the same plane side on the island-shaped nitride semiconductor.
11, 112 have been formed.
【００３６】各窒化物半導体が形成されたｐ型及びｎ型
の各電極上に第１層１０１を形成すべく、半導体ウエハ
をプラズマＣＶＤ装置内に配置させた。シランガス及び
酸化窒素ガスを原料ガスとして酸化珪素膜を半導体ウエ
ハの全面に形成させた。酸化珪素膜を形成後、プラズマ
ＣＶＤ装置から取り出し、レジストマスクを利用してド
ライエッチングさせることによりｐ型電極１１１及びｎ
型電極１１２の表面を露出させた。レジストマスクを除
去して半導体ウエハ上に第１層１０１となる酸化珪素膜
が形成させた。A semiconductor wafer was placed in a plasma CVD apparatus in order to form the first layer 101 on the p-type and n-type electrodes on which the respective nitride semiconductors were formed. A silicon oxide film was formed on the entire surface of the semiconductor wafer using silane gas and nitric oxide gas as source gases. After the silicon oxide film is formed, it is taken out from the plasma CVD apparatus and dry-etched using a resist mask to form the p-type electrodes 111 and n.
The surface of the mold electrode 112 was exposed. The resist mask was removed, and a silicon oxide film to be the first layer 101 was formed on the semiconductor wafer.
【００３７】続いて、半導体ウエハをスパッタリング装
置内に配置させ、ターゲットをプラチナとしスパッタリ
ングすることにより、金属層１０２となる厚さ５００Å
のプラチナを成膜させた。リフトオフによりｐ型電極１
１１及びｎ型電極１１２の表面を露出させた。さらに、
第１層１０１と同様の条件で再び第２層１０２の酸化珪
素を形成させる。その後、ｐ型電極１１１及びｎ型電極
１１２に形成されたマスクを除去する。これにより、各
ｐ型電極１１１、ｎ型電極１１２の表面及びサファイア
基板１０４以外は窒化物半導体の表面には、酸化珪素１
０１、プラチナ１０２、酸化珪素１０３の三層構成とな
る保護膜が形成される。半導体ウエハを分離することに
より、各々フリップチップ型ＬＥＤを得ることができ
る。Subsequently, the semiconductor wafer is placed in a sputtering apparatus, and platinum is used as a target to perform sputtering, thereby forming a metal layer 102 having a thickness of 500Å.
Of platinum. P-type electrode 1 by lift-off
11 and the surface of the n-type electrode 112 were exposed. further,
Silicon oxide for the second layer 102 is formed again under the same conditions as for the first layer 101. After that, the masks formed on the p-type electrode 111 and the n-type electrode 112 are removed. As a result, silicon oxide 1 is formed on the surface of each p-type electrode 111 and the n-type electrode 112 and on the surface of the nitride semiconductor except the sapphire substrate 104.
A protective film having a three-layer structure of 01, platinum 102, and silicon oxide 103 is formed. By separating the semiconductor wafer, each flip-chip type LED can be obtained.
【００３８】得られたＬＥＤチップの内、１４００個を
電極の間隔が約１００μである一対の電極が形成された
駆動回路上にＡｇペーストを用いてダイボンディングさ
せた。各ＬＥＤに電流を流したところサファイア基板１
０４を介して発光しており全て発光可能であった。Of the obtained LED chips, 1400 pieces were die-bonded using Ag paste on a drive circuit in which a pair of electrodes having an electrode interval of about 100 μ was formed. Sapphire substrate 1 when current is applied to each LED
Light was emitted through 04 and all were capable of emitting light.
【００３９】（比較例１）金属層、第２層を設けるかわ
りに第１層の厚みを実施例１の保護膜の厚みと同じ膜厚
とした以外は同様にして図４の如き、フリップチップ型
ＬＥＤを形成させた。実施例１と同様に駆動回路上にＡ
ｇペーストを用いて１４００個のＬＥＤをダイボンディ
ングさせた。各ＬＥＤに電流を流したところ不灯となっ
たものが５個あった。また、発光輝度が極端に暗くなっ
たものが８個あった。不灯となったものを集束イオンビ
ーム加工装置を用いて調べたところ、保護膜を介してＡ
ｇが貫通しているためにリークしていた。また、発光輝
度が極端に暗くなったものを除いた平均輝度を１００と
した場合、実施例１の平均輝度は１２１であった。(Comparative Example 1) A flip chip as shown in FIG. 4 was prepared in the same manner except that the thickness of the first layer was made the same as the thickness of the protective film of Example 1 instead of providing the metal layer and the second layer. Molded LEDs were formed. As in the first embodiment, A on the drive circuit
1400 LEDs were die bonded using g paste. When a current was applied to each LED, there were 5 lights that were not illuminated. Further, there were eight in which the emission brightness was extremely dark. When the non-lighted one was examined using a focused ion beam processing device, A
It leaked because g penetrated. Further, when the average luminance excluding the one in which the emission luminance was extremely dark was set to 100, the average luminance of Example 1 was 121.
【００４０】（実施例２）実施例２は図２に示したＬＥ
Ｄの如く、第２層２０３を酸化珪素で形成させるかわり
にポリイミド被膜とした。ポリイミド被膜を塗布硬化し
て第２層２０３を形成させた以外は、実施例１と同様に
してフリップチップ型ＬＥＤを構成させた。得られたＬ
ＥＤを実施例１、比較例１と同様にして測定したところ
実施例１とほぼ同様の結果が得られた。なお、実施例２
は実施例１に対して経時劣化が少なくなる傾向にある。(Embodiment 2) Embodiment 2 is the LE shown in FIG.
As in D, instead of forming the second layer 203 with silicon oxide, a polyimide coating was used. A flip-chip type LED was constructed in the same manner as in Example 1 except that the second layer 203 was formed by coating and curing the polyimide film. Obtained L
When the ED was measured in the same manner as in Example 1 and Comparative Example 1, almost the same results as in Example 1 were obtained. In addition, Example 2
Is less likely to deteriorate over time as compared with Example 1.
【００４１】（実施例３）金属層３０２の厚みを０．７
μｍとして図３の如く、ｐ型電極として一体的に形成さ
せた以外は、実施例１と同様にしてフリップチップ型Ｌ
ＥＤを形成させた。得られたＬＥＤは工程を簡略化した
にもかかわらず、実施例１とほぼ同様の信頼性を得るこ
とができた。Example 3 The thickness of the metal layer 302 is 0.7.
As shown in FIG. 3, a flip chip type L is formed in the same manner as in Example 1 except that the p type electrode is integrally formed.
The ED was formed. The obtained LED was able to obtain almost the same reliability as that of Example 1, even though the process was simplified.
【００４２】[0042]
【発明の効果】本発明はサファイア基板上の窒化物半導
体を利用したフリップチップ型光半導体素子であり、特
に光半導体素子に設けられた半導体接合を少なくとも３
層構成の保護膜で被覆することにより発光輝度を向上さ
せると共に短絡の少ないフリップチップ型光半導体素子
とすることができる。INDUSTRIAL APPLICABILITY The present invention is a flip-chip type optical semiconductor device using a nitride semiconductor on a sapphire substrate, and particularly at least three semiconductor junctions provided in the optical semiconductor device.
By covering with a protective film having a layered structure, it is possible to obtain a flip-chip type optical semiconductor device which improves emission luminance and has few short circuits.
【図１】 本発明のフリップチップ型光半導体素子の模
式的断面図を示す。FIG. 1 shows a schematic cross-sectional view of a flip-chip type optical semiconductor device of the present invention.
【図２】 本発明の別のフリップチップ型光半導体素子
を駆動基板上に配置させた模式的断面図を示す。FIG. 2 is a schematic sectional view in which another flip-chip type optical semiconductor element of the present invention is arranged on a driving substrate.
【図３】 本発明の他のフリップチップ型光半導体素子
の模式的断面図を示す。FIG. 3 shows a schematic sectional view of another flip-chip type optical semiconductor device of the present invention.
【図４】本発明と比較のために示すフリップチップ型光
半導体素子の模式的断面図を示す。FIG. 4 shows a schematic cross-sectional view of a flip-chip type optical semiconductor device shown for comparison with the present invention.
１００、２００、３００・・・光半導体素子
１０１、２０１、３０１・・・無機絶縁膜からなる第１
層
１０２、２０２・・・金属層
１０３、３０３・・・無機絶縁膜からなる第２層
１０４、２０４、３０４・・・透光性絶縁基板
１０５、２０５、３０５・・・バッファ層
１０６、２０６、３０６・・・ｎ型コンタクト層
１０７、２０７、３０７・・・活性層
１０８、２０８、３０８・・・ｐ型クラッド層
１０９、２０９、３０９・・・ｐ型コンタクト層
１１０、２１０、３１０・・・ｐ型半導体上に形成され
た電極
１１１、２１１・・・ｐ型電極
１１２、２１２、３１２・・・ｎ型電極
２０３・・・有機絶縁膜からなる第２層
２１４・・・駆動基板上に形成された電極パターン
２１５・・・駆動基板
３０２・・・ｐ型電極を構成する金属層
４００・・・光半導体素子
４０１・・・無機絶縁膜からなる第１層
４０４・・・透光性絶縁基板
４０５・・・バッファ層
４０６・・・ｎ型コンタクト層
４０７・・・活性層
４０８・・・ｐ型クラッド層
４０９・・・ｐ型コンタクト層
４１０・・・ｐ型半導体上に形成された電極
４１１・・・ｐ型電極
４１２・・・ｎ型電極100, 200, 300 ... Optical semiconductor element 101, 201, 301 ... First made of inorganic insulating film
Layers 102, 202 ... Metal layers 103, 303 ... Second layers 104, 204, 304 ... Translucent insulating substrates 105, 205, 305 ... Buffer layers 106, 206 ... 306 ... N-type contact layers 107, 207, 307 ... Active layers 108, 208, 308 ... P-type cladding layers 109, 209, 309 ... P-type contact layers 110, 210, 310 ... Electrodes 111, 211 ... P-type electrodes 112, 212, 312 ... N-type electrode 203 ... Second layer 214 made of organic insulating film ... Formed on drive substrate Electrode pattern 215 ... drive substrate 302 ... metal layer 400 forming p-type electrode ... optical semiconductor element 401 ... first layer 404 composed of inorganic insulating film ... translucent insulating substrate 405 .... Buffer layer 406 ... N-type contact layer 407 ... Active layer 408 ... P-type cladding layer 409 ... P-type contact layer 410 ... Electrode 411 formed on p-type semiconductor. .P type electrode 412 ... n type electrode
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平11−97742（ＪＰ，Ａ) 特開 平11−150298（ＪＰ，Ａ) 特開2000−36619（ＪＰ，Ａ) 特開 平６−318731（ＪＰ，Ａ) 特開 平５−160437（ＪＰ，Ａ) 特開 平１−179469（ＪＰ，Ａ) 特開 平６−268252（ＪＰ，Ａ) 特開 平11−191641（ＪＰ，Ａ) 特開 昭56−6417（ＪＰ，Ａ) 特開 昭61−203503（ＪＰ，Ａ) 特開 平９−116192（ＪＰ，Ａ) 特開 平９−199787（ＪＰ，Ａ) 実開 昭58−92751（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 33/00 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-11-97742 (JP, A) JP-A-11-150298 (JP, A) JP-A-2000-36619 (JP, A) JP-A-6-318731 (JP, A) JP 5-160437 (JP, A) JP 1-179469 (JP, A) JP 6-268252 (JP, A) JP 11-191641 (JP, A) Kai 56-6417 (JP, A) JP 61-203503 (JP, A) JP 9-116192 (JP, A) JP 9-199787 (JP, A) Actual JP Sho 58-92751 ( JP, U) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 33/00
Claims (6)
体の同一平面側に正と負の電極が設けられ、該電極表面
の露出部を除いて窒化物半導体層表面を被覆した保護膜
を有するフリップチップ型光半導体素子であって、 前記保護膜は絶縁性被膜からなる第１層と、該第１層上
の金属層と、該金属層上に絶縁性被膜からなる第２層の
少なくとも３層構造を有し、該金属層が前記電極の一部
を構成することを特徴とするフリップチップ型光半導体
素子。1. A protective film in which positive and negative electrodes are provided on the same plane side of a nitride semiconductor formed on a translucent insulating substrate, and the surface of the nitride semiconductor layer is covered except the exposed portion of the electrode surface. A flip-chip type optical semiconductor device having: a protective layer comprising: a first layer made of an insulating coating; a metal layer on the first layer; and a second layer made of an insulating coating on the metal layer. A flip-chip type optical semiconductor device having at least a three-layer structure, wherein the metal layer constitutes a part of the electrode.
素、酸化チタン、酸化ニオブ、酸化ハフニウム、酸化ア
ルミニウム、酸化ジルコニウム、窒化珪素及びポリイミ
ドから選択される少なくとも一種である請求項１に記載
のフリップチップ型光半導体素子。2. The first layer and / or the second layer is at least one selected from silicon oxide, titanium oxide, niobium oxide, hafnium oxide, aluminum oxide, zirconium oxide, silicon nitride and polyimide. The flip-chip type optical semiconductor device described.
が有機絶縁膜である請求項１又は２記載のフリップチッ
プ型光半導体素子。3. The flip-chip type optical semiconductor device according to claim 1, wherein the first layer is an inorganic insulating film and the second layer is an organic insulating film.
請求項１乃至３記載のフリップチップ型光半導体素子。4. The flip-chip type optical semiconductor device according to claim 1, wherein the metal layer has a shape divided into a plurality of parts.
発光素子から放出される光が第前記１層を透過して、前
記金属層で反射される請求項１乃至４記載のフリップチ
ップ型光半導体素子。5. The flip-chip type according to claim 1, wherein the optical semiconductor element is a light emitting element, and light emitted from the light emitting element passes through the first layer and is reflected by the metal layer. Optical semiconductor device.
発光素子が駆動基板に電極が接続され、配置されている
請求項１乃至５記載のフリップチップ型光半導体素子。6. The flip-chip type optical semiconductor element according to claim 1, wherein the optical semiconductor element is a light emitting element, and the light emitting element is arranged with electrodes connected to a driving substrate.
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| JP14187398A JP3531475B2 (en) | 1998-05-22 | 1998-05-22 | Flip chip type optical semiconductor device |
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|---|---|---|---|
| JP14187398A JP3531475B2 (en) | 1998-05-22 | 1998-05-22 | Flip chip type optical semiconductor device |
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|---|---|---|---|
| JP2003354383A Division JP4474892B2 (en) | 2003-10-14 | 2003-10-14 | Flip chip type LED |
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| JPH11340514A JPH11340514A (en) | 1999-12-10 |
| JP3531475B2 true JP3531475B2 (en) | 2004-05-31 |
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