JPH11340514A - Flip-chip optical semiconductor element - Google Patents
Flip-chip optical semiconductor elementInfo
- Publication number
- JPH11340514A JPH11340514A JP14187398A JP14187398A JPH11340514A JP H11340514 A JPH11340514 A JP H11340514A JP 14187398 A JP14187398 A JP 14187398A JP 14187398 A JP14187398 A JP 14187398A JP H11340514 A JPH11340514 A JP H11340514A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- nitride semiconductor
- film
- type
- flip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 128
- 230000003287 optical effect Effects 0.000 title claims description 37
- 150000004767 nitrides Chemical class 0.000 claims abstract description 63
- 229910052751 metal Inorganic materials 0.000 claims abstract description 45
- 239000002184 metal Substances 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 35
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 19
- 230000001681 protective effect Effects 0.000 claims abstract description 18
- 229920001721 polyimide Polymers 0.000 claims description 9
- 239000004642 Polyimide Substances 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 4
- 229910000484 niobium oxide Inorganic materials 0.000 claims description 4
- URLJKFSTXLNXLG-UHFFFAOYSA-N niobium(5+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Nb+5].[Nb+5] URLJKFSTXLNXLG-UHFFFAOYSA-N 0.000 claims description 4
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 4
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 4
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 abstract description 18
- 229910052594 sapphire Inorganic materials 0.000 abstract description 18
- 239000010980 sapphire Substances 0.000 abstract description 18
- 229910052697 platinum Inorganic materials 0.000 abstract description 9
- 238000005530 etching Methods 0.000 abstract description 8
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 6
- 239000010408 film Substances 0.000 description 57
- 239000007789 gas Substances 0.000 description 17
- 239000000853 adhesive Substances 0.000 description 8
- 230000001070 adhesive effect Effects 0.000 description 8
- 239000002019 doping agent Substances 0.000 description 7
- 235000019557 luminance Nutrition 0.000 description 7
- 238000005253 cladding Methods 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 6
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 6
- 229910002601 GaN Inorganic materials 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 229910001873 dinitrogen Inorganic materials 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000002994 raw material Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 125000005842 heteroatom Chemical group 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052749 magnesium Inorganic materials 0.000 description 2
- 239000011777 magnesium Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- 229910020068 MgAl Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910052790 beryllium Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052791 calcium Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 229910052711 selenium Inorganic materials 0.000 description 1
- 229910052596 spinel Inorganic materials 0.000 description 1
- 239000011029 spinel Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 229910052712 strontium Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Device Packages (AREA)
- Led Devices (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は各種インジケータや
光プリンタのプリンタヘッド用など種々の発光素子や太
陽電池などの受光素子として利用可能なフリップチップ
型光半導体素子に係わり、特に、駆動基板上への配置に
おいても位置精度に関わりなく短絡が極めて少ない高輝
度フリップチップ型光半導体素子に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-chip type optical semiconductor element which can be used as a light-emitting element for various indicators, a printer head of an optical printer, and a light-receiving element such as a solar cell. The present invention relates to a high-brightness flip-chip type optical semiconductor element in which a short circuit is extremely small irrespective of the positional accuracy even in the arrangement of (1).
【0002】[0002]
【従来技術】駆動基板の電極上にLEDチップの電極を
直接、Agペーストや半田などにより導通固定させるフ
リップチップ型光半導体素子がある。このようなLED
チップは、導通を取るためにワイヤを用いる必要がな
く、比較的簡単な工程で比較的小型なLEDチップを搭
載することができる。2. Description of the Related Art There is a flip-chip type optical semiconductor element in which an electrode of an LED chip is directly and electrically conductively fixed on an electrode of a driving substrate by using an Ag paste or solder. LED like this
The chip does not require the use of wires to establish conduction, and a relatively small LED chip can be mounted in a relatively simple process.
【0003】このようなフリップチップ型光半導体素子
の模式的断面図を図4に示す。図4にはサファイア基板
404上にバッファ層405を介してn型窒化物半導
体、p型窒化物半導体が形成されたLEDチップが示さ
れている。半導体表面側から導通を取る為に半導体の一
部を除去してp型及びn型窒化物半導体の表面をそれぞ
れ露出させてある。p型及びn型窒化物半導体の表面に
はそれぞれ各p型電極411及びn型電極412を形成
してある。したがって、p型電極411及びn型電極4
12はそれぞれ同一平面側に形成されている。FIG. 4 is a schematic sectional view of such a flip-chip type optical semiconductor device. FIG. 4 shows an LED chip in which an n-type nitride semiconductor and a p-type nitride semiconductor are formed on a sapphire substrate 404 via a buffer layer 405. Part of the semiconductor is removed to expose the surface of the p-type and n-type nitride semiconductors, respectively, in order to establish conduction from the semiconductor surface side. A p-type electrode 411 and an n-type electrode 412 are formed on the surface of the p-type and n-type nitride semiconductors, respectively. Therefore, the p-type electrode 411 and the n-type electrode 4
Reference numerals 12 are formed on the same plane.
【0004】LEDチップは予め駆動基板の電極パター
ン上にAgペーストなどを塗布した後、電極面を下にし
た状態でLEDチップを配置させる。Agペーストを硬
化させることで、LEDチップを固定すると共に駆動基
板の電極とLEDチップの各電極との導通を取ることが
できる。[0004] After an Ag paste or the like is applied on the electrode pattern of the driving substrate in advance, the LED chip is arranged with the electrode surface facing down. By curing the Ag paste, it is possible to fix the LED chip and to establish conduction between the electrode of the drive board and each electrode of the LED chip.
【0005】LEDチップは一片が350μm以下でL
EDチップ上の電極は一辺が約100μm程度と極めて
小さな場合がある。この場合、LEDチップをダイボン
ド機器を用いて精度良く配置させることが難しい。ま
た、上述のフリップチップ型光半導体素子は同一面側に
異なる極性を持った半導体接合が露出形成される場合が
ある。そのため、Agペーストなどを介してLEDチッ
プの電極と駆動基板の電極パターンとを接続する場合、
LEDチップの配置ずれによりAgペーストが半導体接
合間をショートしてしまう場合がある。また、Agペー
ストの粘度、LEDチップ表面との表面張力によりAg
ペーストが半導体接合箇所まで這い上がり、同様に半導
体接合間を短絡してしまう場合がある。短絡は発光輝度
の低下のみならず発光素子の破壊を生ずる。このよう
な、短絡は電極表面を除いて酸化珪素などの保護膜40
1を形成させることによりある程度制御することができ
る。[0005] LED chips each having a length of 350 μm or less
The electrode on the ED chip may be as small as about 100 μm on a side. In this case, it is difficult to accurately arrange the LED chips using a die bonding device. Further, in the above-described flip-chip type optical semiconductor device, there are cases where semiconductor junctions having different polarities are exposed on the same surface side. Therefore, when connecting the electrode of the LED chip and the electrode pattern of the drive board via Ag paste or the like,
Ag paste may short between semiconductor junctions due to misalignment of the LED chips. In addition, the Ag paste viscosity and the surface tension with the LED chip surface cause Ag
The paste may creep up to the semiconductor junction, and similarly short-circuit the semiconductor junction. The short circuit not only lowers the light emission luminance but also destroys the light emitting element. Such a short circuit is caused by the protection film 40 such as silicon oxide except for the electrode surface.
The formation of 1 allows some control.
【0006】しかしながら、より小型化かつ歩留まりの
高い光半導体素子が求められる現在においては十分では
なく、更なる改良が求められている。特に、絶縁性被膜
を成膜させると短絡を生ずる数が減るものの、いまだ十
分な歩留まりがあるフリップチップ型光半導体素子とす
ることができなかった。したがって、本発明はより短絡
の少ない高輝度発光可能なフリップチップ型光半導体素
子を提供することを目的とする。However, at present, there is a demand for smaller and higher-yield optical semiconductor devices, which is not sufficient, and further improvement is required. In particular, when an insulating film is formed, the number of short circuits is reduced, but a flip-chip type optical semiconductor device with a sufficient yield cannot be obtained. Accordingly, an object of the present invention is to provide a flip-chip type optical semiconductor device capable of emitting high luminance light with less short circuit.
【0007】[0007]
【課題を解決するための手段】本発明は透光性絶縁基板
に形成された窒化物半導体の同一平面側に正と負の電極
が設けられ、該電極表面の露出部を除いて窒化物半導体
層表面を被覆した保護膜を有するフリップチップ型光半
導体素子である。特に、保護膜は絶縁性被膜からなる第
1層と、第1層上の金属層と、金属層上に絶縁性被膜か
らなる第2層の少なくとも3層構造からなる。According to the present invention, a positive electrode and a negative electrode are provided on the same plane side of a nitride semiconductor formed on a light-transmitting insulating substrate, and the nitride semiconductor is formed except for an exposed portion of the electrode surface. This is a flip-chip type optical semiconductor device having a protective film covering a layer surface. In particular, the protective film has at least a three-layer structure of a first layer made of an insulating film, a metal layer on the first layer, and a second layer made of an insulating film on the metal layer.
【0008】これにより、制御性よく絶縁被膜を半導体
接合部等に形成することができると共にフリップチップ
型光半導体素子の電気的接続時においても極めて短絡の
少ないものとし得る。即ち、金属層(合金を含む)を形
成させることにより、導電性ペーストを構成する導電性
部材が絶縁性被膜を介して進入することを防ぎ短絡を防
止することができる。また、発光素子で放出された発光
波長を効率よく外部に放出させることができる、或いは
外部からの光を半導体に効率よく吸収できる受光素子と
することができる。Thus, the insulating film can be formed on the semiconductor junction and the like with good controllability, and the short-circuit can be made extremely small even when the flip-chip type optical semiconductor element is electrically connected. That is, by forming a metal layer (including an alloy), it is possible to prevent the conductive member constituting the conductive paste from entering through the insulating coating and to prevent a short circuit. Further, the light-emitting element can efficiently emit the emission wavelength emitted from the light-emitting element to the outside, or can be a light-receiving element that can efficiently absorb external light into the semiconductor.
【0009】本発明の請求項2に記載の構成は、第1層
及び/又は第2層が酸化珪素、酸化チタン、酸化ニオ
ブ、酸化ハフニウム、酸化アルミニウム、酸化ジルコニ
ウム、窒化珪素及びポリイミドから選択される少なくと
も一種である。これにより、より信頼性の高いフリップ
チップ型光半導体素子とすることができる。According to a second aspect of the present invention, the first layer and / or the second layer are selected from silicon oxide, titanium oxide, niobium oxide, hafnium oxide, aluminum oxide, zirconium oxide, silicon nitride, and polyimide. At least one kind. Thus, a flip-chip type optical semiconductor device having higher reliability can be obtained.
【0010】本発明の請求項3に記載の構成は、金属層
が電極の一部を構成するものである。これにより、比較
的簡単な構成で保護膜の工程を簡略化しつつ信頼性の高
いフリップチップ型光半導体素子とすることができる。According to a third aspect of the present invention, the metal layer forms a part of the electrode. Thus, a highly reliable flip-chip type optical semiconductor device can be obtained with a relatively simple configuration while simplifying the process of the protective film.
【0011】[0011]
【発明の実施の形態】本発明者は種々の実験の結果、窒
化物半導体素子上を被覆する被膜を特定構造とすること
により、信頼性の高いフリップチップ型光半導体素子と
しうることを見出し本発明を成すに至った。BEST MODE FOR CARRYING OUT THE INVENTION As a result of various experiments, the present inventor has found out that a highly reliable flip-chip type optical semiconductor device can be obtained by using a specific structure for a film covering a nitride semiconductor device. Invented the invention.
【0012】即ち、無機絶縁膜は緻密で欠陥のない薄膜
を形成することが難しいこと、及びフリップチップ型光
半導体素子の電気的接続に使用される導電性接着剤によ
り短絡すると考えられる。より具体的には導電性接着剤
を構成するAgなどの導電性部材は、周辺環境の水分等
によりイオン化される。イオン化された金属は、窒化物
半導体との通電に伴い無機絶縁膜内をマイグレーション
して短絡を生ずる場合がある。短絡に伴い半導体の機能
低下ばかりでなく、半導体素子が破壊される場合もあ
る。特に、半導体接合部での短絡は、窒化物半導体素子
に特に大きな影響を与えると考えられる。本発明は絶縁
膜間に金属膜を挟み込む保護膜の構成とすることによ
り、絶縁部材を通して半導体接合部などに形成される短
絡を防止し得るものである。なお、このような問題は発
光素子のみならず受光素子においても同様な問題であ
る。That is, it is considered that it is difficult to form a dense and defect-free thin film of the inorganic insulating film, and that the inorganic insulating film is short-circuited by a conductive adhesive used for electrical connection of the flip-chip type optical semiconductor element. More specifically, a conductive member such as Ag forming the conductive adhesive is ionized by moisture or the like in the surrounding environment. In some cases, the ionized metal migrates in the inorganic insulating film due to energization with the nitride semiconductor and causes a short circuit. Not only the function of the semiconductor is reduced due to the short circuit, but also the semiconductor element may be destroyed. In particular, a short circuit at the semiconductor junction is considered to have a particularly large effect on the nitride semiconductor device. According to the present invention, a short circuit formed at a semiconductor junction or the like through an insulating member can be prevented by using a protective film having a metal film sandwiched between insulating films. Note that such a problem is the same not only in the light emitting element but also in the light receiving element.
【0013】以下、本発明の具体的実施態様例について
図1を用いて説明する。図1には、サファイア基板10
4上にn型窒化物半導体、p型窒化物半導体をそれぞれ
成膜させた後、p型窒化物半導体を部分的にエッチング
させn型窒化物半導体層の表面まで露出させる。p型及
びn型窒化物半導体上に電極110、111、112を
形成させた後、プラズマCVD法により酸化珪素を全面
に成膜する。酸化珪素をマスクを利用したエッチングに
より、電極表面の一部を露出させ第1層101としての
絶縁膜を形成させた。次に、白金をスパッタリング法に
より成膜させ、第1層上に金属層102を形成させる。
さらに、第1層101と同様にして、酸化珪素をプラズ
マCVD法により絶縁性の第2層103として成膜させ
三層構成の保護膜を形成させた。形成させたフリップチ
ップ型光半導体素子の電極と、駆動回路基板の電極パタ
ーンとをCu含有のエポキシ樹脂を用いて電気的に接続
させた。駆動回路から電流を供給するとLEDチップが
発光する。LEDチップからの光はサファイアを直接透
過して外部に取り出させるものの他、保護膜を形成する
金属層により反射されサファイア取り出されるものがあ
る。そのため、LEDチップからの発光波長を高効率で
放出することができる。以下、本発明の各構成について
詳述する。Hereinafter, a specific embodiment of the present invention will be described with reference to FIG. FIG. 1 shows a sapphire substrate 10.
After an n-type nitride semiconductor and a p-type nitride semiconductor are respectively formed on 4, the p-type nitride semiconductor is partially etched to expose the surface of the n-type nitride semiconductor layer. After the electrodes 110, 111, and 112 are formed on the p-type and n-type nitride semiconductors, silicon oxide is formed over the entire surface by a plasma CVD method. By etching using silicon oxide as a mask, a part of the electrode surface was exposed to form an insulating film as the first layer 101. Next, platinum is formed by a sputtering method, and the metal layer 102 is formed over the first layer.
Further, in the same manner as in the first layer 101, silicon oxide was formed as an insulating second layer 103 by a plasma CVD method to form a three-layer protective film. The electrode of the formed flip-chip type optical semiconductor element was electrically connected to the electrode pattern of the drive circuit board using a Cu-containing epoxy resin. When a current is supplied from the drive circuit, the LED chip emits light. The light from the LED chip may be transmitted directly through the sapphire and extracted to the outside, or may be reflected by the metal layer forming the protective film and extracted from the sapphire. Therefore, the emission wavelength from the LED chip can be emitted with high efficiency. Hereinafter, each configuration of the present invention will be described in detail.
【0014】(保護膜)本発明の保護膜は、少なくとも
絶縁性被膜からなる第1層101、金属層102、絶縁
性被膜103からなる第2層で構成されている。特に、
保護膜は少なくとも光半導体素子の半導体接合部をフリ
ップチップ型光半導体素子の導通時に利用される導電性
ペーストや半田などの接触から防止するものである。し
たがって、各層は以下の如き特性を持っていることが好
ましい。(Protective Film) The protective film of the present invention comprises at least a first layer 101 made of an insulating film, a metal layer 102, and a second layer made of an insulating film 103. Especially,
The protective film is to prevent at least the semiconductor junction of the optical semiconductor element from being in contact with a conductive paste or solder used when the flip-chip type optical semiconductor element is conducting. Therefore, each layer preferably has the following characteristics.
【0015】(第1層101、201、301)第1層
としては窒化物半導体と接して形成することができるた
め、窒化物半導体との密着性が良いものが好ましい。ま
た、第1層101上に金属層102を形成するために絶
縁性の高い絶縁膜が好ましい。第1層101は発光素子
が発光する波長を効率よく反射する或いは、受光素子が
受光する波長に対して効率よく反射することで光利用効
率を高めることができる。具体的には、第1層101の
膜厚を発光素子の発光波長や受光素子の受光波長に対し
1/4倍の厚さとすることで反射率を向上させることが
できる。また、発光素子から放出された発光波長を金属
層102で反射させる場合は、第1層101が少なくと
も発光素子から放出される発光波長や受光素子で受光さ
れる受光波長に対して透光性の高い層とすることが好ま
しい。(First Layers 101, 201, 301) Since the first layer can be formed in contact with the nitride semiconductor, it is preferable that the first layer has good adhesion to the nitride semiconductor. Further, an insulating film with high insulating property is preferably used for forming the metal layer 102 over the first layer 101. The first layer 101 can efficiently reflect the wavelength at which the light emitting element emits light, or can efficiently reflect the wavelength at which the light receiving element receives light, thereby increasing the light use efficiency. Specifically, the reflectance can be improved by setting the thickness of the first layer 101 to 1/4 times the emission wavelength of the light-emitting element or the light-receiving wavelength of the light-receiving element. In the case where the emission wavelength emitted from the light emitting element is reflected by the metal layer 102, the first layer 101 is transparent to at least the emission wavelength emitted from the light emitting element and the light reception wavelength received by the light receiving element. It is preferable to use a high layer.
【0016】このような第1層101に用いられる材料
としては、酸化珪素、酸化チタン、酸化ニオブ、酸化ハ
フニウム、酸化アルミニウム、酸化ジルコニウム及び窒
化珪素などの金属酸化物や金属窒化物、さらにはポリイ
ミドなどの樹脂が好適に挙げられる。第1層101が無
機絶縁膜の場合はスパッタリング法や各種CVD法など
を利用することにより、小型な光半導体素子においても
制御性よく形成することができる。特に、緻密な無機絶
縁膜を成膜させるためはプラズマCVD法を利用するこ
とが好ましい。Materials used for the first layer 101 include metal oxides and metal nitrides such as silicon oxide, titanium oxide, niobium oxide, hafnium oxide, aluminum oxide, zirconium oxide and silicon nitride, and polyimide. And the like. When the first layer 101 is an inorganic insulating film, a small optical semiconductor element can be formed with good controllability by using a sputtering method, various CVD methods, or the like. In particular, in order to form a dense inorganic insulating film, it is preferable to use a plasma CVD method.
【0017】(金属層102、202、302)金属層
102は導電時に保護膜を構成する第2層103を介し
て進入する外部などからの金属イオンなどを実質的に防
止する働きをするものである。金属層102は、スパッ
タリング法や真空蒸着法などにより薄膜、かつ制御性良
く形成することができる他、欠陥の少ない膜として形成
しやすい。また、第1層101を透過した波長を効率よ
く反射する金属(合金や積層物を含む)を選択すること
により、集光性等を高め光取りだし効率を高めることが
できる。(Metal layers 102, 202, 302) The metal layer 102 has a function of substantially preventing metal ions or the like from entering from the outside via the second layer 103 constituting the protective film during conduction. is there. The metal layer 102 can be formed as a thin film with good controllability by a sputtering method, a vacuum evaporation method, or the like, and can be easily formed as a film with few defects. Further, by selecting a metal (including an alloy or a laminate) that efficiently reflects the wavelength transmitted through the first layer 101, it is possible to improve the light condensing property and the like, and to increase the light extraction efficiency.
【0018】このような金属層102は外部からのイオ
ンの進入を止める。或いは、導電性ペースト、導電性ペ
ーストを構成するフィラや半田の進入を防止しうるもの
であれば種々の金属でも選択することができる。金属層
の具体的材料としては、ニッケル、白金、金、アルミニ
ウム、タングステン、モリブデンやこれらの合金や積層
物が好適に挙げられる。The metal layer 102 stops the intrusion of ions from the outside. Alternatively, various kinds of metals can be selected as long as they can prevent the intrusion of the conductive paste, fillers and solder constituting the conductive paste. Preferred examples of the material of the metal layer include nickel, platinum, gold, aluminum, tungsten, molybdenum, and alloys and laminates thereof.
【0019】金属層はイオンマイグレーションを好適に
防止しうるものであるため、金属層自体がイオン化し難
いものが好ましい。特に、銀は、導電性が高く、窒化物
半導体のバンドギャップに対応する光に対して反射性は
よい。しかし、イオンマイグレーションを起こしやすい
銀を除いた金属元素で構成することが好ましい。また、
金属層102の厚みは発光素子からの発光波長を反射及
び小型化などを考慮すると百Åから数ミクロン程度の厚
みで形成することが好ましい。金属層102は短絡しな
い限り、窒化物半導体の全周を被覆するように形成して
も良いし、複数に分割した形状で形成することもでき
る。Since the metal layer can suitably prevent ion migration, it is preferable that the metal layer itself does not easily ionize. In particular, silver has high conductivity and good reflectivity for light corresponding to the band gap of the nitride semiconductor. However, it is preferable to use a metal element excluding silver, which easily causes ion migration. Also,
The thickness of the metal layer 102 is preferably about 100 to several microns in consideration of the wavelength of light emitted from the light-emitting element and miniaturization. As long as the metal layer 102 is not short-circuited, it may be formed so as to cover the entire circumference of the nitride semiconductor or may be formed into a plurality of divided shapes.
【0020】複数に分割された場合、p型或いはn型の
電極の一部を構成することもできる。これにより、電極
形成と同時に金属層302を形成することができる。そ
のため複数のマスクとエッチング工程を簡略して、工程
数を低減することができる。このような金属層302と
して具体的にはp型窒化物半導体の電極として機能させ
る場合は、オーミック接触等を考慮して、ニッケル、コ
バルト、金や白金などの金属元素で構成されていること
が好ましい。同様に、n型窒化物半導体の電極としても
機能させる場合は、タングステン、アルミニウムやチタ
ンなどの金属元素で構成されていることが好ましい。さ
らに、窒化物半導体を活性層を介してダブルへテロ構造
としたLEDに利用した場合、活性層の端面から放出さ
れる光が特に多いことから活性層を絶縁層を介した金属
層で被覆することにより、発光効率をより向上させるこ
とができる。When divided into a plurality of parts, a part of a p-type or n-type electrode can be formed. Thus, the metal layer 302 can be formed simultaneously with the formation of the electrodes. Therefore, a plurality of masks and an etching step can be simplified, and the number of steps can be reduced. When the metal layer 302 specifically functions as an electrode of a p-type nitride semiconductor, the metal layer 302 may be formed of a metal element such as nickel, cobalt, gold, or platinum in consideration of ohmic contact and the like. preferable. Similarly, in the case of functioning also as an electrode of an n-type nitride semiconductor, the electrode is preferably formed of a metal element such as tungsten, aluminum, or titanium. Further, when a nitride semiconductor is used for an LED having a double heterostructure via an active layer, the active layer is covered with a metal layer via an insulating layer since light emitted from an end face of the active layer is particularly large. Thereby, the luminous efficiency can be further improved.
【0021】(第2層103)第2層103は金属層1
02を被覆する絶縁被膜であり外部と窒化物半導体とを
電気的に絶縁するために設けられるものである。したが
って、金属層102上に直接形成される場合は金属層1
02と密着性がよく絶縁性が高いことが求められる。第
2層103に用いられる材料としては、第1層101と
同様、種々の金属酸化物、金属窒化物などの無機物質の
他、有機樹脂を種々選択することができる。より具体的
には、酸化珪素、酸化チタン、酸化ニオブ、酸化ハフニ
ウム、酸化アルミニウム、酸化ジルコニウム、窒化珪素
及びポリイミド樹脂などを好適に挙げることができる。
第2層103が無機絶縁膜の場合は緻密に形成させるほ
ど短絡の傾向が減少するが、緻密に形成させるためには
成膜時間がかかる傾向にある。(Second Layer 103) The second layer 103 is a metal layer 1
02 is an insulating film provided to electrically insulate the outside from the nitride semiconductor. Therefore, when directly formed on the metal layer 102, the metal layer 1
02 and high insulation properties are required. As the material used for the second layer 103, similarly to the first layer 101, various inorganic materials such as metal oxides and metal nitrides, and various organic resins can be selected. More specifically, preferred examples include silicon oxide, titanium oxide, niobium oxide, hafnium oxide, aluminum oxide, zirconium oxide, silicon nitride, and polyimide resin.
In the case where the second layer 103 is an inorganic insulating film, the tendency to short-circuit is reduced as the layer is densely formed, but it takes a long time to form the layer densely.
【0022】一方、第2層103はフリップチップ型光
半導体素子の最外郭に配置される場合がある。このよう
な、第2層103の場合は実装時における保護膜の損傷
を防止するため、ポリイミドなどの絶縁性有機物質を使
用することもできる。これにより、信頼性を更に向上さ
せることもできる。具体的には、窒化物半導体は、サフ
ァイア基板などの上に形成させた後、粘着シート上でス
クライブなどにより個々の窒化物半導体素子に分割され
る。分割された窒化物半導体素子が取り上げ可能なよう
に粘着シートをのばし、粘着シート下部から突き上げピ
ンによって個々の半導体素子を突き上げ、コレットに吸
着する。他方、搭載させる駆動基板側の電極にAgペー
ストなどの導電性ペーストを塗布する。コレットによっ
て吸着した窒化物半導体素子を導電性ペースト上に乗
せ、導電性接着剤を硬化させる。これによって、所望の
駆動基板上などに窒化物半導体素子を配置固定すること
ができる。On the other hand, the second layer 103 may be arranged at the outermost periphery of the flip-chip type optical semiconductor device. In the case of such a second layer 103, an insulating organic substance such as polyimide can be used in order to prevent damage to the protective film during mounting. Thereby, the reliability can be further improved. Specifically, after the nitride semiconductor is formed on a sapphire substrate or the like, the nitride semiconductor is divided into individual nitride semiconductor elements by scribing or the like on an adhesive sheet. The adhesive sheet is stretched so that the divided nitride semiconductor elements can be picked up, and the individual semiconductor elements are pushed up from below the adhesive sheet by push-up pins, and are attracted to the collet. On the other hand, a conductive paste such as an Ag paste is applied to the electrodes on the drive substrate side to be mounted. The nitride semiconductor element adsorbed by the collet is placed on the conductive paste, and the conductive adhesive is cured. Thus, the nitride semiconductor element can be arranged and fixed on a desired driving substrate or the like.
【0023】窒化物半導体素子の場合、比較的硬いサフ
ァイア基板などの上に窒化物半導体が形成される。その
ため、基板側においては比較的強度が高いものの、コレ
ットで吸着させる際、突き上げピンは絶縁被膜を形成さ
せた電極面側を突き上げる。そして半導体面(サファイ
ア基板に対して窒化物半導体側)を配線基板の導電部に
導電性接着剤を介してフリップチップボンディングさせ
る。In the case of a nitride semiconductor device, a nitride semiconductor is formed on a relatively hard sapphire substrate or the like. Therefore, although the strength is relatively high on the substrate side, the push-up pin pushes up the electrode surface side on which the insulating coating is formed when adsorbing with the collet. Then, the semiconductor surface (the nitride semiconductor side with respect to the sapphire substrate) is flip-chip bonded to the conductive portion of the wiring substrate via a conductive adhesive.
【0024】この場合、短絡不良を防止するために窒化
物半導体面、窒化物半導体端面及び露出している基板面
等に絶縁膜を形成しているにも関わらず、短絡不良の発
生率がかなり高くなる傾向がある。この原因として、発
光面が基板面の時は基板が硬いために突き上げピンによ
って傷や割れが発生し難い。特に、窒化物半導体面側を
突き上げピンによって突き上げる場合は、保護膜に傷や
割れ等が発生し易くなるために短絡の発生率が高いもの
と考えられる。In this case, although the insulating film is formed on the nitride semiconductor surface, the nitride semiconductor end surface, the exposed substrate surface, and the like in order to prevent short-circuit failure, the occurrence rate of short-circuit failure is considerably high. Tends to be higher. The cause is that when the light emitting surface is the substrate surface, the substrate is hard, so that the push-up pins are less likely to cause scratches and cracks. In particular, when the nitride semiconductor surface is pushed up by a push-up pin, it is considered that the protection film is easily damaged, cracked, or the like, so that a short-circuit occurrence rate is high.
【0025】そこで、有機樹脂による絶縁被膜を特に第
2層103として形成させた場合はフリップチップボン
ディング形式の窒化物半導体素子において、突き上げピ
ンによる窒化物半導体面の傷及び絶縁膜の割れを防止
し、短絡不良がなく信頼性の高い窒化物半導体素子とす
ることができる。Therefore, in the case where an insulating film made of an organic resin is formed as the second layer 103 in particular, in a flip chip bonding type nitride semiconductor device, scratches on the nitride semiconductor surface and cracks in the insulating film due to push-up pins are prevented. In addition, a highly reliable nitride semiconductor device without short circuit failure can be obtained.
【0026】即ち、第2層103を有機絶縁膜とするこ
とにより、配線基板への実装時における粘着シート下部
からの突き上げピンの物理的衝撃を緩和し、短絡の原因
となる絶縁膜の割れ等を効果的に防止できるものであ
る。このような、第2層103にポリイミド系薄膜を利
用した場合における具体的な膜厚は、突き上げピンで突
き上げた時に受ける物理的力の緩和、及び絶縁膜の耐圧
の点で1〜10μmとすることが好ましい。また、ポリ
イミド系薄膜の発光主波長における透過率が60%以下
であると、窒化物半導体素子端面からの漏光を抑制、光
学特性のばらつきの軽減される。そのため、配光特性の
安定性が得られるためより好ましい。That is, by using the organic insulating film as the second layer 103, the physical impact of the push-up pins from the lower part of the adhesive sheet at the time of mounting on the wiring board is alleviated, and the insulating film may be broken to cause a short circuit. Can be effectively prevented. The specific film thickness when a polyimide thin film is used for the second layer 103 is 1 to 10 μm in terms of relaxation of a physical force received when the second layer 103 is pushed up by the push-up pin and withstand voltage of the insulating film. Is preferred. When the transmittance at the main emission wavelength of the polyimide-based thin film is 60% or less, light leakage from the end face of the nitride semiconductor element is suppressed, and variation in optical characteristics is reduced. Therefore, it is more preferable because the stability of the light distribution characteristics can be obtained.
【0027】(光半導体素子)本発明の光半導体素子
は、窒化物半導体からなる受光素子や発光素子である。
透光性絶縁基板上に形成され少なくとも半導体接合を有
する窒化物半導体により構成することができる。具体的
には、透光性絶縁基板上にMOCVD法やHVPE法を
用いて窒化物半導体を形成させることができる。このよ
うな透光性絶縁基板としては、窒化ガリウム、サファイ
ア(Al2O3)やスピネル(MgAl2O4)などが挙げ
られる。半導体接合としては、MIS接合、PIN接合
の他、pn接合が挙げられる。また、光半導体素子の特
性により、ホモやダブルへテロ構造とすることができ
る。さらに、単一量子井戸構造や多重量子井戸構造とす
ることもできる。(Optical Semiconductor Element) The optical semiconductor element of the present invention is a light receiving element or a light emitting element made of a nitride semiconductor.
It can be made of a nitride semiconductor formed on a light-transmitting insulating substrate and having at least a semiconductor junction. Specifically, a nitride semiconductor can be formed over a light-transmitting insulating substrate by an MOCVD method or an HVPE method. Examples of such a light-transmitting insulating substrate include gallium nitride, sapphire (Al 2 O 3 ), spinel (MgAl 2 O 4 ), and the like. Examples of the semiconductor junction include a pn junction in addition to a MIS junction and a PIN junction. Further, depending on the characteristics of the optical semiconductor element, a homo or double hetero structure can be obtained. Furthermore, a single quantum well structure or a multiple quantum well structure can be used.
【0028】pin接合やpn接合が短絡することで、
半導体特性に大きな損傷が加わる。そのため、本発明が
有効に働くことになる。半導体の材料やその混晶度によ
って光半導体素子の発光波長及び受光波長を紫外光から
赤色領域まで種々選択することができる。By short-circuiting the pin junction and the pn junction,
Significant damage to semiconductor properties. Therefore, the present invention works effectively. The emission wavelength and the reception wavelength of the optical semiconductor element can be variously selected from the ultraviolet light to the red region depending on the material of the semiconductor and the degree of mixed crystal thereof.
【0029】なお結晶性の良い窒化物半導体を形成させ
るためにはサファイヤ基板を用いることが好ましい。こ
のサファイヤ基板上に格子不整合緩和のためにGaN、
AlN等のバッファー層を形成しその上にpn接合など
を有する窒化物半導体を形成させることにより半導体特
性の優れた発光素子や受光素子を構成させることができ
る。サファイアで基板を形成させると硬度が高く、基板
自体が透光性を持つと共に外部からの水分等の進入を防
ぐことができるため特に好ましい。In order to form a nitride semiconductor with good crystallinity, it is preferable to use a sapphire substrate. GaN on this sapphire substrate to reduce lattice mismatch,
By forming a buffer layer of AlN or the like and forming a nitride semiconductor having a pn junction or the like thereon, a light-emitting element or a light-receiving element having excellent semiconductor characteristics can be formed. Forming the substrate with sapphire is particularly preferable because the hardness is high, the substrate itself has a light-transmitting property, and the entry of moisture or the like from the outside can be prevented.
【0030】窒化物半導体は、不純物をドープしない状
態でn型導電性を示すが、n型ドーパントとしてSi、
Ge、Se、Te、Sn等を適宜導入することが好まし
い。また、n型ドーパントと微量のp型ドーパントとを
ドーピングしたダブルドーピングすることもできる。こ
れらのドーパントの種類とドーピング量を変えることに
よってキヤリア密度を制御し電気抵抗を下げることがで
きる。一方、p型窒化物半導体を形成させる場合は、p
型ドーパントであるZn、Mg、Be、Ca、Sr、B
a等をドープさせる。窒化ガリウム半導体は、p型ドー
パントをドープしただけでは低抵抗化しにくいためp型
ドーパント導入後に、低速電子線照射、プラズマ照射や
熱処理等させることで低抵抗化処理することができる。The nitride semiconductor shows n-type conductivity without being doped with an impurity.
It is preferable to appropriately introduce Ge, Se, Te, Sn, and the like. Further, double doping in which an n-type dopant and a small amount of a p-type dopant are doped can also be performed. By changing the type and doping amount of these dopants, the carrier density can be controlled and the electric resistance can be reduced. On the other hand, when forming a p-type nitride semiconductor,
Type dopants Zn, Mg, Be, Ca, Sr, B
a and the like are doped. Since the gallium nitride semiconductor is difficult to reduce the resistance only by doping the p-type dopant, the resistance can be reduced by introducing a low-speed electron beam, irradiating a plasma, or performing a heat treatment after introducing the p-type dopant.
【0031】半導体露出面側に一対の電極を形成するた
めには各半導体を所望の形状にエッチングしてあること
が好ましい。エッチングとしては、ドライエッチング
や、ウエットエッチングがある。ドライエッチングとし
ては例えば反応性イオンエッチング、イオンミリング、
集束ビームエッチング、ECRエッチング等が挙げられ
る。又、ウエットエッチングとしては、硝酸と燐酸の混
酸を用いることができる。ただし、エッチングを行う前
に所望の形状に窒化珪素や酸化珪素等の材料を用いてマ
スクを形成することは言うまでもない。以下、本発明の
実施例について詳述するがこれのみに限定されるもので
ないことはいうまでもない。In order to form a pair of electrodes on the semiconductor exposed surface side, each semiconductor is preferably etched into a desired shape. Examples of the etching include dry etching and wet etching. Examples of dry etching include reactive ion etching, ion milling,
Focused beam etching, ECR etching and the like can be mentioned. For wet etching, a mixed acid of nitric acid and phosphoric acid can be used. However, it goes without saying that a mask is formed in a desired shape using a material such as silicon nitride or silicon oxide before etching. Hereinafter, embodiments of the present invention will be described in detail, but it is needless to say that the present invention is not limited thereto.
【0032】[0032]
【実施例】(実施例1)洗浄されたサファイアのC面を
成膜表面としてMOCVD法を用いて窒化物半導体を成
膜した。成膜装置内にサファイア基板104を配置し6
50℃に加熱すると共に、TMG(トリメチルガリウ
ム)ガス、窒素ガスを原料ガス、水素ガスをキャリアガ
スとして流しバッファ層105を形成させた。一旦、原
料ガスの導入を止めた後、成膜温度を1150℃に上げ
TMGガス、窒素ガス、水素ガスにn型ドーパントガス
としてシランを加えて厚さ5μmのn型窒化ガリウム層
106を成膜した。次に、TMGガスの供給を停止し、
成膜温度を800℃に低下させた後、TMGガス、TM
A(トリメチルアルミニウム)ガス、窒素ガス及び水素
ガスを供給させて厚さ3nmの窒化インジウムガリウム
を発光層107として成膜させた。(Example 1) A nitride semiconductor was formed by MOCVD using the C surface of washed sapphire as a film forming surface. The sapphire substrate 104 is placed in the film forming apparatus and 6
While heating to 50 ° C., a buffer layer 105 was formed by flowing TMG (trimethyl gallium) gas and nitrogen gas as source gases and hydrogen gas as carrier gas. Once the introduction of the raw material gas is stopped, the film formation temperature is raised to 1150 ° C., and silane is added as an n-type dopant gas to TMG gas, nitrogen gas, and hydrogen gas to form a 5 μm-thick n-type gallium nitride layer 106. did. Next, the supply of TMG gas is stopped,
After lowering the film forming temperature to 800 ° C., TMG gas, TM
A (trimethylaluminum) gas, a nitrogen gas, and a hydrogen gas were supplied to form a 3 nm-thick indium gallium nitride film as the light-emitting layer 107.
【0033】次に、原料ガスの供給を停止して成膜温度
を1050℃に上げた後、再び原料ガスとしてTMGガ
ス、TMAガス、窒素ガス、キャリアガスとして水素ガ
ス、不純物ガスとしてシクロペンタジエチルマグネシウ
ムを加えて厚さ300Åのp型クラッド層108を成膜
させる。Next, the supply of the raw material gas was stopped and the film forming temperature was raised to 1050 ° C., and then again TMG gas, TMA gas, nitrogen gas as the raw material gas, hydrogen gas as the carrier gas, and cyclopentadiethyl as the impurity gas. A p-type cladding layer 108 having a thickness of 300 ° is formed by adding magnesium.
【0034】p型クラッド層108上にTMAガスの供
給を停止した以外はp型クラッド層の形成と同様にして
厚さ1500Åのp型コンタクト層109を成膜させ
る。(なお、p型窒化物半導体となる半導体層は成膜後
400℃以上で熱処理してある。)こうして活性層を介
してダブルへテロ構造である窒化物半導体を成膜した。
半導体ウエハの同一面側に電極を形成させるため、マス
クを利用して、活性層、p型クラッド層、p型コンタク
ト層を一部残しつつn型コンタクト層まで、部分的にエ
ッチングさせてある。同様に各LEDチップとして分離
できる大きさでサファイア基板上までそれぞれエッチン
グしてある。エッチング後、サファイア基板上には島状
の窒化物半導体層が形成されることとなる。The p-type contact layer 109 having a thickness of 1500 ° is formed on the p-type cladding layer 108 in the same manner as the formation of the p-type cladding layer except that the supply of the TMA gas is stopped. (Note that the semiconductor layer to be a p-type nitride semiconductor is heat-treated at 400 ° C. or more after film formation.) Thus, a nitride semiconductor having a double hetero structure was formed via the active layer.
In order to form electrodes on the same side of the semiconductor wafer, a mask is used to partially etch the n-type contact layer while partially leaving the active layer, the p-type cladding layer, and the p-type contact layer. Similarly, each of the LED chips is etched to a size that can be separated as far as the sapphire substrate. After the etching, an island-shaped nitride semiconductor layer is formed on the sapphire substrate.
【0035】p型コンタクト層109と接触し全面を被
覆する電極110として白金を500Åでスパッタリン
グ法を用いて成膜した。この電極110上には、100
μm角のp型電極111として白金を0.7μmで成膜
した。n型コンタクト層106上には直径100μmの
n型電極112としてタングステン/アルミニウムを2
00Å/0.7μmとして成膜した。これによって、島
状の窒化物半導体上には同一平面側に正負一対の電極1
11、112が形成されたことになる。Platinum was formed by sputtering at 500 ° as an electrode 110 which was in contact with the p-type contact layer 109 and covered the entire surface. On this electrode 110, 100
Platinum was formed to a thickness of 0.7 μm as a p-type electrode 111 of μm square. On the n-type contact layer 106, tungsten / aluminum is used as an n-type electrode 112 having a diameter of 100 μm.
The film was formed as 00 ° / 0.7 μm. Thus, a pair of positive and negative electrodes 1 are formed on the same plane on the island-shaped nitride semiconductor.
11 and 112 are formed.
【0036】各窒化物半導体が形成されたp型及びn型
の各電極上に第1層101を形成すべく、半導体ウエハ
をプラズマCVD装置内に配置させた。シランガス及び
酸化窒素ガスを原料ガスとして酸化珪素膜を半導体ウエ
ハの全面に形成させた。酸化珪素膜を形成後、プラズマ
CVD装置から取り出し、レジストマスクを利用してド
ライエッチングさせることによりp型電極111及びn
型電極112の表面を露出させた。レジストマスクを除
去して半導体ウエハ上に第1層101となる酸化珪素膜
が形成させた。A semiconductor wafer was placed in a plasma CVD apparatus to form the first layer 101 on each of the p-type and n-type electrodes on which each nitride semiconductor was formed. A silicon oxide film was formed on the entire surface of the semiconductor wafer using silane gas and nitrogen oxide gas as source gases. After forming the silicon oxide film, the p-type electrodes 111 and n are taken out from the plasma CVD apparatus and dry-etched using a resist mask.
The surface of the mold electrode 112 was exposed. By removing the resist mask, a silicon oxide film to be the first layer 101 was formed on the semiconductor wafer.
【0037】続いて、半導体ウエハをスパッタリング装
置内に配置させ、ターゲットをプラチナとしスパッタリ
ングすることにより、金属層102となる厚さ500Å
のプラチナを成膜させた。リフトオフによりp型電極1
11及びn型電極112の表面を露出させた。さらに、
第1層101と同様の条件で再び第2層102の酸化珪
素を形成させる。その後、p型電極111及びn型電極
112に形成されたマスクを除去する。これにより、各
p型電極111、n型電極112の表面及びサファイア
基板104以外は窒化物半導体の表面には、酸化珪素1
01、プラチナ102、酸化珪素103の三層構成とな
る保護膜が形成される。半導体ウエハを分離することに
より、各々フリップチップ型LEDを得ることができ
る。Subsequently, the semiconductor wafer is placed in a sputtering apparatus, and sputtering is performed using platinum as a target to form a metal layer 102 having a thickness of 500.degree.
Of platinum was deposited. P-type electrode 1 by lift-off
11 and the surface of the n-type electrode 112 were exposed. further,
The silicon oxide of the second layer 102 is formed again under the same conditions as the first layer 101. After that, the mask formed on the p-type electrode 111 and the n-type electrode 112 is removed. Thus, the surface of the nitride semiconductor except for the surfaces of the p-type electrode 111 and the n-type electrode 112 and the sapphire substrate 104 has silicon oxide 1
01, platinum 102 and silicon oxide 103 are formed. By separating the semiconductor wafer, flip-chip type LEDs can be obtained.
【0038】得られたLEDチップの内、1400個を
電極の間隔が約100μである一対の電極が形成された
駆動回路上にAgペーストを用いてダイボンディングさ
せた。各LEDに電流を流したところサファイア基板1
04を介して発光しており全て発光可能であった。Out of the obtained LED chips, 1,400 chips were die-bonded to a drive circuit on which a pair of electrodes each having a distance of about 100 μm was formed, using an Ag paste. When current is applied to each LED, sapphire substrate 1
Light was emitted through the light-emitting element No. 04, and all light emission was possible.
【0039】(比較例1)金属層、第2層を設けるかわ
りに第1層の厚みを実施例1の保護膜の厚みと同じ膜厚
とした以外は同様にして図4の如き、フリップチップ型
LEDを形成させた。実施例1と同様に駆動回路上にA
gペーストを用いて1400個のLEDをダイボンディ
ングさせた。各LEDに電流を流したところ不灯となっ
たものが5個あった。また、発光輝度が極端に暗くなっ
たものが8個あった。不灯となったものを集束イオンビ
ーム加工装置を用いて調べたところ、保護膜を介してA
gが貫通しているためにリークしていた。また、発光輝
度が極端に暗くなったものを除いた平均輝度を100と
した場合、実施例1の平均輝度は121であった。Comparative Example 1 A flip chip as shown in FIG. 4 was prepared in the same manner except that the thickness of the first layer was changed to the same thickness as the thickness of the protective film in Example 1 instead of providing the metal layer and the second layer. A shaped LED was formed. In the same manner as in the first embodiment,
1400 LEDs were die-bonded using the g paste. When current was applied to each LED, there were 5 lamps that did not light. Eight light emission luminances were extremely dark. When the unlit lamp was examined using a focused ion beam processing apparatus, A was detected through the protective film.
g was leaking because it penetrated. In addition, when the average luminance excluding the one in which the emission luminance was extremely dark was set to 100, the average luminance of Example 1 was 121.
【0040】(実施例2)実施例2は図2に示したLE
Dの如く、第2層203を酸化珪素で形成させるかわり
にポリイミド被膜とした。ポリイミド被膜を塗布硬化し
て第2層203を形成させた以外は、実施例1と同様に
してフリップチップ型LEDを構成させた。得られたL
EDを実施例1、比較例1と同様にして測定したところ
実施例1とほぼ同様の結果が得られた。なお、実施例2
は実施例1に対して経時劣化が少なくなる傾向にある。(Embodiment 2) In Embodiment 2, the LE shown in FIG.
As in D, a polyimide film was used instead of forming the second layer 203 with silicon oxide. A flip-chip LED was formed in the same manner as in Example 1 except that the second layer 203 was formed by applying and curing a polyimide film. L obtained
When ED was measured in the same manner as in Example 1 and Comparative Example 1, almost the same results as in Example 1 were obtained. Example 2
In the case of Example 1, the deterioration with the lapse of time tends to be smaller than that in Example 1.
【0041】(実施例3)金属層302の厚みを0.7
μmとして図3の如く、p型電極として一体的に形成さ
せた以外は、実施例1と同様にしてフリップチップ型L
EDを形成させた。得られたLEDは工程を簡略化した
にもかかわらず、実施例1とほぼ同様の信頼性を得るこ
とができた。(Embodiment 3) The thickness of the metal layer 302 is set to 0.7
As shown in FIG. 3, the flip-chip type L was formed in the same manner as in Example 1 except that the p-type electrode was integrally formed as shown in FIG.
An ED was formed. The obtained LED was able to obtain almost the same reliability as that of Example 1 although the process was simplified.
【0042】[0042]
【発明の効果】本発明はサファイア基板上の窒化物半導
体を利用したフリップチップ型光半導体素子であり、特
に光半導体素子に設けられた半導体接合を少なくとも3
層構成の保護膜で被覆することにより発光輝度を向上さ
せると共に短絡の少ないフリップチップ型光半導体素子
とすることができる。The present invention relates to a flip-chip type optical semiconductor device using a nitride semiconductor on a sapphire substrate.
By covering with a protective film having a layer structure, it is possible to improve the light emission luminance and to obtain a flip-chip type optical semiconductor element with few short circuits.
【図1】 本発明のフリップチップ型光半導体素子の模
式的断面図を示す。FIG. 1 is a schematic sectional view of a flip-chip type optical semiconductor device of the present invention.
【図2】 本発明の別のフリップチップ型光半導体素子
を駆動基板上に配置させた模式的断面図を示す。FIG. 2 is a schematic cross-sectional view in which another flip-chip type optical semiconductor device of the present invention is arranged on a driving substrate.
【図3】 本発明の他のフリップチップ型光半導体素子
の模式的断面図を示す。FIG. 3 is a schematic cross-sectional view of another flip-chip type optical semiconductor device of the present invention.
【図4】本発明と比較のために示すフリップチップ型光
半導体素子の模式的断面図を示す。FIG. 4 is a schematic cross-sectional view of a flip-chip type optical semiconductor device shown for comparison with the present invention.
100、200、300・・・光半導体素子 101、201、301・・・無機絶縁膜からなる第1
層 102、202・・・金属層 103、303・・・無機絶縁膜からなる第2層 104、204、304・・・透光性絶縁基板 105、205、305・・・バッファ層 106、206、306・・・n型コンタクト層 107、207、307・・・活性層 108、208、308・・・p型クラッド層 109、209、309・・・p型コンタクト層 110、210、310・・・p型半導体上に形成され
た電極 111、211・・・p型電極 112、212、312・・・n型電極 203・・・有機絶縁膜からなる第2層 214・・・駆動基板上に形成された電極パターン 215・・・駆動基板 302・・・p型電極を構成する金属層 400・・・光半導体素子 401・・・無機絶縁膜からなる第1層 404・・・透光性絶縁基板 405・・・バッファ層 406・・・n型コンタクト層 407・・・活性層 408・・・p型クラッド層 409・・・p型コンタクト層 410・・・p型半導体上に形成された電極 411・・・p型電極 412・・・n型電極100, 200, 300: Optical semiconductor element 101, 201, 301: First made of inorganic insulating film
Layers 102, 202: metal layers 103, 303: second layer made of an inorganic insulating film 104, 204, 304: translucent insulating substrate 105, 205, 305: buffer layers 106, 206, 306: n-type contact layer 107, 207, 307: active layer 108, 208, 308: p-type cladding layer 109, 209, 309: p-type contact layer 110, 210, 310 ... Electrodes 111, 211 formed on a p-type semiconductor 111, 211, p-type electrodes 112, 212, 312 ... n-type electrode 203 ... second layer made of an organic insulating film 214 ... formed on a driving substrate Electrode pattern 215... Driving substrate 302... Metal layer constituting p-type electrode 400. Optical semiconductor element 401. First layer made of inorganic insulating film 404. Substrate 405: Buffer layer 406: N-type contact layer 407: Active layer 408: P-type cladding layer 409: P-type contact layer 410: Electrode formed on p-type semiconductor 411: p-type electrode 412: n-type electrode
Claims (3)
体の同一平面側に正と負の電極が設けられ、該電極表面
の露出部を除いて窒化物半導体層表面を被覆した保護膜
を有するフリップチップ型光半導体素子であって、 前記保護膜は絶縁性被膜からなる第1層と、該第1層上
の金属層と、該金属層上に絶縁性被膜からなる第2層の
少なくとも3層構造を有することを特徴とするフリップ
チップ型光半導体素子。1. A protective film in which a positive electrode and a negative electrode are provided on the same plane side of a nitride semiconductor formed on a translucent insulating substrate, and the surface of the nitride semiconductor layer is covered except for an exposed portion of the electrode surface. Wherein the protective film comprises a first layer made of an insulating film, a metal layer on the first layer, and a second layer made of an insulating film on the metal layer. A flip-chip type optical semiconductor device having at least a three-layer structure.
素、酸化チタン、酸化ニオブ、酸化ハフニウム、酸化ア
ルミニウム、酸化ジルコニウム、窒化珪素及びポリイミ
ドから選択される少なくとも一種である請求項1に記載
のフリップチップ型光半導体素子。2. The method according to claim 1, wherein the first layer and / or the second layer is at least one selected from silicon oxide, titanium oxide, niobium oxide, hafnium oxide, aluminum oxide, zirconium oxide, silicon nitride, and polyimide. The flip-chip type optical semiconductor device according to the above.
いる請求項1に記載のフリップチップ型光半導体素子。3. The flip-chip type optical semiconductor device according to claim 1, wherein said metal layer forms a part of said electrode.
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