JP3130292B2 - Semiconductor light emitting device and method of manufacturing the same - Google Patents

Semiconductor light emitting device and method of manufacturing the same

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Publication number
JP3130292B2
JP3130292B2 JP10287623A JP28762398A JP3130292B2 JP 3130292 B2 JP3130292 B2 JP 3130292B2 JP 10287623 A JP10287623 A JP 10287623A JP 28762398 A JP28762398 A JP 28762398A JP 3130292 B2 JP3130292 B2 JP 3130292B2
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Japan
Prior art keywords
electrode
light emitting
layer
side electrode
semiconductor light
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Expired - Fee Related
Application number
JP10287623A
Other languages
Japanese (ja)
Other versions
JPH11191641A (en
Inventor
登美男 井上
賢一 小屋
憲男 山下
Original Assignee
松下電子工業株式会社
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
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    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0095Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • HELECTRICITY
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    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、たとえば青色発光
ダイオード等の光デバイスに利用される窒化ガリウム系
化合物を利用したフリップチップ型の半導体発光装置に
係り、特にP側電極からの反射光を効率よく回収して光
取り出し面から発光させるようにした半導体発光装置の
製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-chip type semiconductor light-emitting device using a gallium nitride compound used for an optical device such as a blue light-emitting diode, and more particularly to a method for efficiently reflecting light from a P-side electrode. The present invention relates to a method for manufacturing a semiconductor light emitting device that is well collected and emits light from a light extraction surface.

【0002】[0002]

【従来の技術】GaN,GaAlN,InGaN及びI
nAlGaN等のGaN系化合物半導体は、可視光発光
デバイスや高温動作電子デバイス用の半導体材料として
多用されるようになり、青色及び緑色の発光ダイオード
の分野での展開が進んでいる。
2. Description of the Related Art GaN, GaAlN, InGaN and I
GaN-based compound semiconductors such as nAlGaN have been widely used as semiconductor materials for visible light emitting devices and high-temperature operating electronic devices, and have been developed in the fields of blue and green light emitting diodes.

【0003】このGaN系化合物の半導体の製造では、
その表面において半導体膜を成長させるための結晶基板
として、一般的には絶縁性のサファイアが利用される。
このサファイアのような絶縁性の結晶基板を用いる場合
では、結晶基板側から電極を出すことができないので、
半導体層に設けるp,nの電極は結晶基板と対向する側
の一面に形成されることになる。
[0003] In the production of a semiconductor of this GaN compound,
Generally, insulating sapphire is used as a crystal substrate for growing a semiconductor film on the surface.
In the case of using an insulating crystal substrate such as sapphire, electrodes cannot be exposed from the crystal substrate side.
The p and n electrodes provided on the semiconductor layer are formed on one surface facing the crystal substrate.

【0004】図8に従来のGaN系半導体発光素子の概
略斜視図を示す。
FIG. 8 is a schematic perspective view of a conventional GaN-based semiconductor light emitting device.

【0005】GaN系半導体発光素子50は、絶縁性の
基板としてサファイア基板50aを用いてその上にn型
層51とp型層52を形成し、p型層52の一部をエッ
チングしてn型層51を露出したものである。そして、
n型層51にはボンディングのためのn側電極51aを
形成し、p型層52は発光域となるためその上面のほぼ
全体に透明電極52aを形成すると共にその一部にボン
ディングのためのp側電極52bを設けるというのが基
本的な構成である。
The GaN-based semiconductor light emitting device 50 uses a sapphire substrate 50a as an insulating substrate, forms an n-type layer 51 and a p-type layer 52 thereon, and partially etches the p-type layer 52 to form an n-type layer. The mold layer 51 is exposed. And
On the n-type layer 51, an n-side electrode 51a for bonding is formed, and on the p-type layer 52, which serves as a light emitting region, a transparent electrode 52a is formed on almost the entire upper surface thereof, and a p-type electrode The basic configuration is to provide the side electrode 52b.

【0006】ここで、透明電極52aはNiとAuの積
層膜またはCoとAuの積層膜としたものであり、p側
電極52bも同様の組み合わせの積層膜によって形成さ
れたものが殆どである。また、n側電極51aはTiと
Auの積層膜またはVとAlとの積層膜としたものが一
般に利用されている。
Here, the transparent electrode 52a is a laminated film of Ni and Au or a laminated film of Co and Au, and the p-side electrode 52b is mostly formed of a laminated film of the same combination. The n-side electrode 51a is generally used as a laminated film of Ti and Au or a laminated film of V and Al.

【0007】透明電極52a,p側電極52b及びn側
電極51aのそれぞれの材料は、GaN系にオーミック
接続できる条件を満たすことを大前提として選択された
ものである。すなわち、Ni,Co,Ti及びVが素子
側に対してオーミック接続するのに好適な電極材料であ
り、Auは酸化され難いのでボンディング性の向上が図
れるという理由で利用されている。
The material of each of the transparent electrode 52a, the p-side electrode 52b, and the n-side electrode 51a is selected on the premise that the condition for ohmic connection to the GaN system is satisfied. That is, Ni, Co, Ti, and V are electrode materials suitable for ohmic connection to the element side, and Au is hardly oxidized, and is used because the bonding property can be improved.

【0008】このような半導体発光素子50では、n型
層51とp型層52との間のp−n接合域またはその間
に積層されるInGaNを活性層とし、p型層52の表
面を主光取出し面としてリードフレーム等にマウントさ
れる。そして、n側電極51a及びp側電極52bのそ
れぞれにAuワイヤ(図示せず)をボンディングしてリ
ードフレーム側と導通させることにより、主光取出し面
からの発光が得られる。
In such a semiconductor light emitting device 50, the active layer is InGaN laminated between the pn junction region between the n-type layer 51 and the p-type layer 52 or between them, and the surface of the p-type layer 52 is mainly used. It is mounted on a lead frame or the like as a light extraction surface. Then, by bonding an Au wire (not shown) to each of the n-side electrode 51a and the p-side electrode 52b to conduct the light to the lead frame side, light emission from the main light extraction surface is obtained.

【0009】また、基板50aとして用いるサファイア
は光学的に透明であることとn側及びp側の電極51
a,52bが同じ側の面に含まれていることから、フリ
ップチップ型のアセンブリが可能である。これは、n側
及びp側の電極51a,52bのそれぞれにバンプ電極
を形成しておき、これらをマウント側の電極に超音波圧
着法等によって接合し、ワイヤレスボンディングのアセ
ンブリとしたものである。このフリップチップ型として
アセンブリするときは、図8に示す発光素子を上下反転
させた姿勢のときの基板50aの上面が主光取出し面と
なる。
The sapphire used as the substrate 50a is optically transparent and has n-side and p-side electrodes 51.
Since a and 52b are included on the same side surface, a flip-chip type assembly is possible. In this method, bump electrodes are formed on each of the n-side and p-side electrodes 51a and 52b, and these are bonded to the mount-side electrodes by an ultrasonic pressure bonding method or the like, thereby forming a wireless bonding assembly. When the flip-chip type is assembled, the upper surface of the substrate 50a when the light emitting element shown in FIG. 8 is turned upside down is the main light extraction surface.

【0010】一方、このような絶縁性のサファイアの基
板50aにGaN系化合物半導体層を積層する発光素子
50では、素子材料のたとえば誘電率ε等の物理定数や
素子構造に起因して、静電気に対して非常に弱いことが
知られている。たとえば、発光素子50をリードフレー
ムのマウント部に搭載してエポキシ樹脂等によって封止
したLEDランプの場合では、LEDランプと静電気が
チャージされたコンデンサとを対向させて両者間に放電
を生じさせたとき、順方向でおよそ100Vの静電圧
で、逆方向ではおよそ30Vの静電圧で破壊されてしま
う。
On the other hand, in such a light emitting device 50 in which a GaN-based compound semiconductor layer is laminated on an insulating sapphire substrate 50a, static electricity is generated due to physical constants such as a dielectric constant ε of the device material and the device structure. It is known to be very weak. For example, in the case of an LED lamp in which the light emitting element 50 is mounted on a mount portion of a lead frame and sealed with an epoxy resin or the like, the LED lamp and a capacitor charged with static electricity are opposed to each other to cause discharge between the two. In some cases, breakdown occurs at a static voltage of about 100 V in the forward direction and at about 30 V in the reverse direction.

【0011】これに対し、静電気等の過電流による発光
素子50の破壊を防止するためには、静電気保護素子と
してSiダイオードを備えることが有効である。この静
電気保護素子は、本願出願人が先に提案して、特願平9
−18782号として既に出願した明細書及び図面に記
載のものが適用でき、n型のシリコン基板を基材とした
Siダイオードを発光素子と逆極性の関係になるように
導通をとりながら接続した構成としたものである。
On the other hand, in order to prevent the light emitting element 50 from being destroyed by an overcurrent such as static electricity, it is effective to provide a Si diode as an electrostatic protection element. This electrostatic protection element is proposed by the applicant of the present application in advance, and is disclosed in Japanese Patent Application No. Hei.
A structure in which an Si diode having an n-type silicon substrate as a base material is connected to a light-emitting element while conducting so as to have a reverse polarity relationship, which can be applied to those described in the specification and drawings already filed as US Pat. It is what it was.

【0012】図9は図8の発光素子50を静電気保護用
のSiダイオード53に搭載して複合素子化した例であ
って、同図の(a)は平面図、同図の(b)は同図
(a)のC−C線矢視による縦断面図である。
FIG. 9 shows an example in which the light emitting device 50 of FIG. 8 is mounted on a Si diode 53 for electrostatic protection to form a composite device. FIG. 9A is a plan view, and FIG. It is a longitudinal cross-sectional view by the CC line arrow of FIG.

【0013】Siダイオード53はn型シリコン基板5
3aを素材としたもので、図9の(a)において右端側
に偏った位置の上面側から不純物イオンを注入して拡散
させて、p型半導体領域53bを部分的に形成したもの
である。そして、n型半導体領域に相当する部分にn側
電極54及びp型半導体領域53bに相当する部分にp
側電極55をそれぞれ形成し、更に下面にはリードフレ
ーム等と電気的に導通させるためのn電極56を設けて
いる。ここで、Siダイオード53のn側電極54とn
電極56との間の抵抗は保護抵抗として働く。
The Si diode 53 is an n-type silicon substrate 5
9A, a p-type semiconductor region 53b is partially formed by injecting and diffusing impurity ions from the upper surface at a position deviated rightward in FIG. 9A. Then, a portion corresponding to the n-type semiconductor region 53b and an n-side electrode 54 and a portion
Side electrodes 55 are respectively formed, and further, on the lower surface, an n-electrode 56 for electrically conducting with a lead frame or the like is provided. Here, the n-side electrode 54 of the Si diode 53 and n
The resistance between the electrodes 56 functions as a protection resistance.

【0014】Siダイオード53のn側電極54は発光
素子50のp側電極52bにマイクロバンプ57を介し
て接続され、p側電極55はn側電極51aにマイクロ
バンプ58を介して接続され、発光素子50とSiダイ
オード53とは逆極性によって接続されている。そし
て、p側電極55の一部はリードフレーム等との間に接
続するワイヤのボンディングエリアである。
The n-side electrode 54 of the Si diode 53 is connected to the p-side electrode 52b of the light emitting element 50 via the micro bump 57, and the p-side electrode 55 is connected to the n-side electrode 51a via the micro bump 58 to emit light. The element 50 and the Si diode 53 are connected with opposite polarities. A part of the p-side electrode 55 is a bonding area of a wire connected to a lead frame or the like.

【0015】このような逆極性の接続によって、高電圧
による過電流が印加されたときには、発光素子50に印
加される逆方向電圧はSiダイオード53の順方向電圧
付近すなわち0.9Vでバイパスが開くことによって、
発光素子50に印加される順方向電圧はSiダイオード
53の抵抗成分による電圧降下分とツェナー電圧Vz付
近(例えば10V)でバイパスが開くことにより、それ
ぞれ過電流が流される。したがって、静電気による発光
素子50の破壊を確実に防ぐことができる。
By the connection of the reverse polarity, when an overcurrent due to a high voltage is applied, the reverse voltage applied to the light emitting element 50 is close to the forward voltage of the Si diode 53, that is, the bypass is opened at 0.9V. By
As for the forward voltage applied to the light emitting element 50, an overcurrent is caused to flow by opening the bypass near the voltage drop due to the resistance component of the Si diode 53 and near the zener voltage Vz (for example, 10V). Therefore, destruction of the light emitting element 50 due to static electricity can be reliably prevented.

【0016】ここで、フリップチップ型の半導体発光素
子では、透明電極52aの上側に発光層が形成されるの
で、この発光層からの光はサファイア基板50aを抜け
てその上面を光取り出し面として発光するものと、透明
電極52a側に向かうものとがある。このため、この透
明電極52aへ向かう光を透明電極に代わる反射率の高
い厚膜電極で反射させるようにすれば、光取り出し面か
らの発光効率を上げることができる。この場合、厚膜電
極がボンディングパッド部も含めてp側電極となる。こ
の場合も、電極材料の選定の条件としてGaN系の半導
体積層膜へのオーミック接続が可能であることに変わり
はなく、電極材料の選択にはこのオーミック接続の条件
に加えて、発光層からの光を効率よく反射させる材料と
することも条件に含めば、最適化が図られることにな
る。
Here, in the flip-chip type semiconductor light emitting device, since a light emitting layer is formed above the transparent electrode 52a, light from this light emitting layer passes through the sapphire substrate 50a and emits light using the upper surface as a light extraction surface. There are two types: one that goes to the transparent electrode 52a side. For this reason, if the light traveling toward the transparent electrode 52a is reflected by a thick-film electrode having a high reflectance instead of the transparent electrode, the luminous efficiency from the light extraction surface can be increased. In this case, the thick film electrode becomes a p-side electrode including the bonding pad portion. Also in this case, the condition for the selection of the electrode material is that the ohmic connection to the GaN-based semiconductor laminated film is still possible, and the selection of the electrode material is in addition to the condition for the ohmic connection, Optimization is achieved by including a material that reflects light efficiently.

【0017】[0017]

【発明が解決しようとする課題】透明電極52aの代わ
りに厚膜電極とし、ボンディングパッドも含めてp側電
極とした場合、このp側電極を図8で示したものと同じ
材料すなわちNiとAuの積層膜またはCoとAuの積
層膜とすれば、p型の半導体積層膜とのオーミック接続
が可能でしかもマイクロバンプ57の接合性もよいもの
が得られる。
When a thick film electrode is used instead of the transparent electrode 52a and a p-side electrode including a bonding pad is used, this p-side electrode is made of the same material as that shown in FIG. 8, that is, Ni and Au. Or a laminated film of Co and Au, it is possible to obtain a film which can be ohmic-connected to a p-type semiconductor laminated film and has good bonding properties of the microbumps 57.

【0018】ところが、NiとAuとの積層膜では、一
般にオーミックコンタクトをとるNiの層はきわめて薄
く、Auはこれに比べると厚く形成される。CoとAu
との組み合わせでも同様にCoは薄くてAuは厚い。こ
のような厚さの関係は、最適なオーミック性すなわち電
極と半導体(p型GaN層)との接触抵抗を最も小さく
するための条件からくるものである。
However, in the laminated film of Ni and Au, the layer of Ni for making ohmic contact is generally very thin, and Au is formed thicker than this. Co and Au
Similarly, Co is thin and Au is thick. Such a relationship of the thickness comes from the condition for the optimum ohmic property, that is, the condition for minimizing the contact resistance between the electrode and the semiconductor (p-type GaN layer).

【0019】このようにAuのほうがNiやCoよりも
厚いと、熱処理された後には合金化されて、p側電極は
金色または黄色を帯びた金色となってしまい、p型の半
導体積層膜とp側電極の界面がこのような金色または黄
色を帯びた金色の層が形成されることになる。
If Au is thicker than Ni or Co as described above, it is alloyed after the heat treatment, and the p-side electrode becomes gold or yellowish gold. A gold layer having such a gold or yellowish color at the interface of the p-side electrode is formed.

【0020】ここで、金属を真空蒸着して形成した新鮮
な表面に種々の波長の光を垂直に投射したときの反射率
は波長によって変化することが知られている。これは、
たとえば平成8年版の「理科年表」の第519頁所載の
金属面の分光反射率の表として示されている。この表に
よれば、Auの蒸着面に光を照射した場合では、波長が
0.550μm(緑色に相当)以上であれば反射率は8
0%以上であるのに対し、波長が0.500μmになる
と反射率は50%以下に急激に低下している。そして、
波長が0.450μm(青色に相当)であれば、40%
以下にまで下がり、波長が短くなるにつれて反射率は大
きく減衰していることが判る。
Here, it is known that the reflectivity when vertically projecting light of various wavelengths onto a fresh surface formed by vacuum-depositing a metal changes depending on the wavelength. this is,
For example, it is shown as a table of spectral reflectance of a metal surface on page 519 of "Science Chronology" of the 1996 edition. According to this table, when light is applied to the Au deposition surface, the reflectance is 8 if the wavelength is 0.550 μm (corresponding to green) or more.
When the wavelength is 0.500 μm, the reflectance sharply drops to 50% or less, while the reflectance is 0% or more. And
40% if the wavelength is 0.450 μm (corresponding to blue)
It can be seen that the reflectance decreases greatly as the wavelength becomes shorter.

【0021】したがって、p型の半導体積層膜とp側電
極の界面に金色または黄色を帯びた金色の層があると、
発光層からの光は吸収される量のほうが大きく、光取出
し面側への反射回収の効率は大幅に低下してしまう。
Therefore, if there is a gold layer or a yellowish yellow layer at the interface between the p-type semiconductor laminated film and the p-side electrode,
The amount of light absorbed from the light emitting layer is larger, and the efficiency of reflection collection on the light extraction surface side is greatly reduced.

【0022】このように、電極材料としてAuを使用す
る場合、フリップチップ型のようにp側電極からの反射
光も光取出し面側に回収して発光効率を上げようとして
も、その効果は十分ではない。
As described above, when Au is used as the electrode material, even if the light reflected from the p-side electrode is collected on the light extraction surface side to increase the luminous efficiency as in the flip chip type, the effect is sufficient. is not.

【0023】さらに前記した平成8年版の「理科年表」
の第519頁所載の金属面の分光反射率の表によれば、
可視光領域において、最も反射率の高い金属材料は、A
gである。しかし、半導体デバイスの分野において、電
極材料としてAgを使用する場合にはそのマイグレーシ
ョンの発生を防止することが必要である。このマイグレ
ーションは水分や電場等について或る特定の条件のとき
にAgがイオン化することによって発生するもので、回
路の短絡等を引き起こす原因となる。
Furthermore, the above-mentioned "science chronology" of the 1996 edition
According to the table of the spectral reflectance of the metal surface described on page 519,
In the visible light region, the metal material having the highest reflectance is A
g. However, in the field of semiconductor devices, when Ag is used as an electrode material, it is necessary to prevent the occurrence of migration. This migration is caused by the ionization of Ag under certain conditions with respect to moisture, electric field, and the like, and causes a short circuit in the circuit.

【0024】この発光素子の場合もAgをp側電極に使
用すれば、エポキシ樹脂で封止したLEDランプにおい
て、発光素子に印加される電場とエポキシ樹脂内を浸透
してきた水分によって、Agマイグレーションを起こ
し、発光素子のp側電極とn側電極間のリーク不良が短
時間の通電で発生するといった問題が生じる。
In the case of this light emitting element as well, if Ag is used for the p-side electrode, in an LED lamp sealed with an epoxy resin, Ag migration is prevented by an electric field applied to the light emitting element and moisture permeating the epoxy resin. This causes a problem that a leak failure between the p-side electrode and the n-side electrode of the light emitting element occurs by short-time energization.

【0025】本発明において解決すべ課題は、反射率が
最も高いAgをマイグレーションを発生させることなく
p側電極に使用することができるフリップチップ型の半
導体発光装置の製造方法を提供することである。
It is an object of the present invention to provide a method of manufacturing a flip-chip type semiconductor light emitting device in which Ag having the highest reflectance can be used for a p-side electrode without causing migration.

【0026】[0026]

【課題を解決するための手段】本発明は、絶縁性であっ
て光透過型の基板の上にGaN系化合物半導体のn型層
及びp型層を積層し、前記n型層の表面にn側電極を形
成し、前記p型層の表面のほぼ全面に薄膜の透明電極を
形成するとともにこの透明電極の上であって前記p型層
の表面の一部を占める領域にp側電極を形成したフリッ
プチップ型の半導体発光素子と、前記フリップチップ型
の半導体発光素子のp側及びn側電極に対応する位置に
2つの電極が形成された第1の主面と全面電極が形成さ
れた第2の主面を持つサブマウント素子とからなり、前
記サブマウント素子の第1の主面の2つの電極上にマイ
クロバンプを介して前記フリップチップ型の半導体発光
素子を対峙させて導通させる半導体発光装置の製造方法
であって、前記半導体発光素子を前記サブマウント素子
が行列状に形成されたウエハーの上に両素子の電極を対
峙させマイクロバンプを介して導通接合させた後に、前
記ウエハーを前記発光素子とともにAgを溶解した電解
メッキ液に浸漬し、前記ウエハーの電極を電解用電源の
負電極に接続し、電解メッキ法により前記Agを前記透
明電極の表面に反射層として付着形成することを特徴と
する。
According to the present invention, an n-type layer and a p-type layer of a GaN-based compound semiconductor are laminated on an insulating and light-transmitting substrate, and n-type layers are formed on the surface of the n-type layer. Forming a side electrode, forming a thin-film transparent electrode on almost the entire surface of the p-type layer, and forming a p-side electrode in a region on the transparent electrode and occupying a part of the surface of the p-type layer. A flip-chip type semiconductor light emitting device, a first main surface having two electrodes formed at positions corresponding to the p-side and n-side electrodes of the flip-chip type semiconductor light emitting device, and a second surface having a whole surface electrode formed thereon. And a sub-mount element having two main surfaces, and the flip-chip type semiconductor light-emitting element is made to face and conduct through two bumps on the first main surface of the sub-mount element via micro-bumps. A method of manufacturing a device, comprising: After the body light emitting elements are electrically connected to each other via a microbump with the electrodes of both elements facing each other on a wafer on which the submount elements are formed in a matrix, electrolytic plating is performed by dissolving Ag together with the light emitting elements. The electrode of the wafer is connected to a negative electrode of a power supply for electrolysis, and the Ag is deposited on the surface of the transparent electrode as a reflective layer by electrolytic plating.

【0027】本発明によれば、p側電極が透明電極のま
まの発光素子であってもサブマウント素子が行列状に形
成されたウエハーに搭載後、電解メッキ法を用いること
によって、透明電極にAgの反射層を簡単に付着形成す
ることができ、外部量子効率に優れた複合素子として、
また、サブマウント素子をSiダイオードとすることに
より、静電耐圧にも優れた複合素子として提供できる。
According to the present invention, even if the p-side electrode is a light-emitting element with a transparent electrode, the sub-mount element is mounted on a wafer formed in a matrix, and then the electro-plating method is used. Ag compound layer can be easily attached and formed, and as a composite device with excellent external quantum efficiency,
Further, by using a Si diode as the submount element, it is possible to provide a composite element having excellent electrostatic withstand voltage.

【0028】[0028]

【発明の実施の形態】以下に、本発明の実施の形態の具
体例を図面を参照しながら説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0029】図1は本発明の半導体発光装置におけるG
aN系化合物半導体発光素子の概要であって、同図の
(a)は平面図、同図の(b)は同図(a)のA−A線
矢視による縦断面図である。
FIG. 1 shows G in the semiconductor light emitting device of the present invention.
FIG. 1A is a schematic view of an aN-based compound semiconductor light emitting device, in which FIG. 1A is a plan view, and FIG. 1B is a longitudinal sectional view taken along line AA of FIG.

【0030】図1の(a)及び(b)において、発光素
子1は、絶縁性の透明なサファイア基板1aの表面に複
数の半導体薄膜層を従来周知の有機金属気相成長法によ
って成膜したものである。この薄膜の積層体は、たとえ
ば下から順にGaNバッファ層1b,n型GaN層1
c,InGaN活性層1d,p型AlGaN層1e及び
p型GaN層1fとしたものであり、ダブルヘテロ構造
または量子井戸構造となっている。
1A and 1B, in the light emitting device 1, a plurality of semiconductor thin film layers are formed on the surface of an insulating transparent sapphire substrate 1a by a conventionally known metal organic chemical vapor deposition method. Things. For example, a GaN buffer layer 1b and an n-type GaN layer 1
c, an InGaN active layer 1d, a p-type AlGaN layer 1e, and a p-type GaN layer 1f, which have a double hetero structure or a quantum well structure.

【0031】n型GaN層1cの一つのコーナー部の上
面はエッチングによって段差状に除去され、この除去さ
れた部分にn側電極2を蒸着法によって形成している。
また、エッチングによる切除部分を除いた最上層のp型
GaN層1fの上面には、p側電極3が同様に蒸着法に
よって形成されている。そして、これらのn側電極2及
びp側電極3の上にはそれぞれマイクロバンプ4,5を
形成している。ただし、マイクロバンプ4,5は、サブ
マウント素子側の電極上に形成される場合もある。
The upper surface of one corner of the n-type GaN layer 1c is removed in a step shape by etching, and an n-side electrode 2 is formed on the removed portion by a vapor deposition method.
A p-side electrode 3 is similarly formed on the upper surface of the uppermost p-type GaN layer 1f excluding a portion cut off by etching by a vapor deposition method. Micro bumps 4 and 5 are formed on the n-side electrode 2 and the p-side electrode 3, respectively. However, the micro bumps 4 and 5 may be formed on the electrode on the submount element side in some cases.

【0032】図2は発光素子1を備えた半導体発光装置
の概略図である。
FIG. 2 is a schematic view of a semiconductor light emitting device having the light emitting element 1.

【0033】リードフレーム6の上端に形成されたマウ
ント部6aには、静電気保護用のSiダイオード素子7
をサブマウント素子として搭載して、これを適切なAg
ペーストによって接着固定している。そして、このSi
ダイオード素子7の上面に、図1の(b)に示した発光
素子1を上下反転した姿勢として配置している。
A mount portion 6a formed at the upper end of the lead frame 6 has a Si diode element 7 for electrostatic protection.
Is mounted as a submount element, and
It is bonded and fixed with paste. And this Si
On the upper surface of the diode element 7, the light emitting element 1 shown in FIG.

【0034】発光素子1のマイクロバンプ4,5は、そ
れぞれSiダイオード素子7のp側電極7b及びn側電
極7aに電気的に導通させてエポキシ樹脂8によって封
止され、図示の姿勢においてサファイア基板1aの上面
を光取出し面としている。
The micro-bumps 4 and 5 of the light emitting element 1 are electrically connected to the p-side electrode 7b and the n-side electrode 7a of the Si diode element 7 and are sealed with the epoxy resin 8, respectively. The upper surface of 1a is a light extraction surface.

【0035】発光素子1への通電があるときには、半導
体積層膜中のInGaN活性層1dが発光層となり、従
来例でも示したようにこの発光層からの光がサファイア
基板1aの光取り出し面側及びp側電極3に向かう。そ
して、このp側電極3に向かう光を効率よく反射させる
ようにすればよいが、このp側電極3の電極材料として
Auを含むものでは青色の光の反射率が小さくなるとい
うものであった。
When the light-emitting element 1 is energized, the InGaN active layer 1d in the semiconductor laminated film becomes a light-emitting layer, and light from this light-emitting layer emits light from the light-extraction surface of the sapphire substrate 1a to the light-emitting side as shown in the conventional example. It goes to the p-side electrode 3. Then, the light directed toward the p-side electrode 3 may be efficiently reflected. However, if the electrode material of the p-side electrode 3 includes Au, the reflectance of blue light is reduced. .

【0036】これに対し、本発明では、p側電極3から
の反射効率を上げるためにその材料をp型GaN層1f
に接触するコンタクト層3aとしてNiやCoまたはS
bを50nmの膜厚で形成し、その上に反射層3bとし
て青色及び緑色の光に対して反射率の高い銀白色系金属
のAlまたはZnを1.5μmの膜厚で積層している。
ここで、コンタクト層3aを薄くする理由は、p型Ga
N層に対して良好なオーミックコンタクトをとるため
と、それに用いられる金属は、青色や緑色の光に対して
反射率が必ずしも良好ではないために、光の大部分が透
過できる薄さにするためで、その上に積層された反射率
の高い反射層3bで光を反射する構成にしている。ま
た、この反射層3bは、光が透過できないように十分な
膜厚にする必要がある。これにより、p側電極3に向か
う光を効率よく反射させることができる。また、反射層
3bがZnの場合は、マイクロバンプ4,5との接合性
を良くするために反射層3bの上にAuの層を形成す
る。
On the other hand, in the present invention, in order to increase the reflection efficiency from the p-side electrode 3, the material is changed to the p-type GaN layer 1f.
Ni, Co or S as a contact layer 3a that contacts
b is formed to a thickness of 50 nm, and a reflective layer 3b is formed thereon by stacking a 1.5 μm-thick silver-white metal Al or Zn having a high reflectance with respect to blue and green light.
Here, the reason for thinning the contact layer 3a is that p-type Ga
In order to make a good ohmic contact with the N layer and to make the metal used for it thin enough to transmit most of the light because the reflectivity for blue and green light is not always good. Thus, light is reflected by the reflective layer 3b having a high reflectance laminated thereon. Further, it is necessary that the thickness of the reflective layer 3b is sufficient to prevent light from passing therethrough. Thus, light traveling toward the p-side electrode 3 can be efficiently reflected. When the reflective layer 3b is made of Zn, an Au layer is formed on the reflective layer 3b in order to improve the bonding property with the micro bumps 4 and 5.

【0037】また、反射層3bに青色や緑色の光に対し
て反射率が最も高いAgを用いる場合は、マイグレーシ
ョン現象が付随する。しかも、このフリップチップ型の
半導体発光素子の場合では、p側電極3とn側電極2が
同一面に隣接しているので、マイグレーション現象が起
こりやすい状況となり、短時間の通電により電極間のリ
ークモード不良が発生するという不利な面がある。
When Ag having the highest reflectance for blue or green light is used for the reflective layer 3b, a migration phenomenon is accompanied. In addition, in the case of the flip-chip type semiconductor light emitting device, the p-side electrode 3 and the n-side electrode 2 are adjacent to the same surface, so that a migration phenomenon is likely to occur. There is a disadvantage that mode failure occurs.

【0038】これに対し、本発明では、反射層3bにA
gを用いる場合は、Pd又はPtの合金として反射層3
bを形成する。AgにPdまたはPtを混ぜることによ
り反射率は少し低下するがAgのマイグレーションは抑
制される。その混合の適正値はPdの場合30wt%程
度、Ptの場合は10wt%程度で、この反射層3bの
膜厚を1.5μmで形成する。
On the other hand, in the present invention, A
When g is used, the reflection layer 3 is formed as an alloy of Pd or Pt.
b is formed. When Pd or Pt is mixed with Ag, the reflectance slightly decreases, but the migration of Ag is suppressed. The appropriate value of the mixing is about 30 wt% in the case of Pd, and about 10 wt% in the case of Pt, and the film thickness of the reflective layer 3 b is 1.5 μm.

【0039】図3は本発明の半導体発光装置であって発
光素子とサブマウント素子からなる複合素子の部分の概
要である。同図の(a)はその概略平面図、同図の
(b)は同図(a)のB−B線矢視による縦断面図であ
る。
FIG. 3 is an outline of a semiconductor light emitting device according to the present invention, which is a composite element comprising a light emitting element and a submount element. (A) of the same figure is a schematic plan view thereof, and (b) of the same figure is a longitudinal sectional view taken along line BB of the same figure (a).

【0040】ここで用いるGaN系化合物半導体発光素
子は、従来の透明電極52aを持つ発光素子50であ
り、サブマウント素子(Siダイオード)7上にマイク
ロバンプを介して接合され、複合素子とした後に、反射
層10を透明電極上に青色及び緑色の光に対して反射率
の高い銀白色系金属材料のAgまたはZnを1.5μm
の膜厚で電解メッキ法により形成したものである。この
場合、複合素子とした後に反射層10を形成するので、
その断面形状は図2と異なっている。つまり、図2の場
合は、発光素子1のp側電極3の部分にのみ反射層3b
が形成されているが、図3の場合は、発光素子50の透
明電極52a、p側電極52b、マイクロバンプ5及び
Siダイオードのn側電極7aの表面全体に反射層10
が形成されるが、反射層としての機能を果たすのは透明
電極52a上に形成された部分である。この反射層10
と発光素子50のp側電極部分以外は図2と同じ構成で
ある。
The GaN-based compound semiconductor light-emitting element used here is a conventional light-emitting element 50 having a transparent electrode 52a, which is bonded on a submount element (Si diode) 7 via a microbump to form a composite element. The reflective layer 10 is formed by forming a silver-white metallic material, Ag or Zn, having a high reflectance to blue and green light on the transparent electrode by 1.5 μm.
It is formed by electrolytic plating with a film thickness of. In this case, since the reflection layer 10 is formed after forming the composite element,
Its cross-sectional shape is different from that of FIG. In other words, in the case of FIG. 2, the reflective layer 3b is formed only on the p-side electrode 3 of the light emitting element 1.
In the case of FIG. 3, the reflective layer 10 is formed on the entire surface of the transparent electrode 52a, the p-side electrode 52b, the microbump 5, and the n-side electrode 7a of the Si diode.
Is formed, but it is the portion formed on the transparent electrode 52a that functions as a reflective layer. This reflection layer 10
The configuration is the same as that of FIG. 2 except for the light emitting element 50 and the p-side electrode portion.

【0041】また、この形態においても反射層10とし
てAgを用いる場合は、マイグレーション対策が必要で
ある。この場合、図4(a)に示すように反射層10で
あるAgメッキ層の表面にNiのメッキ層からなる保護
膜11を形成する。これにより、樹脂内に浸透してくる
水分とAgとの接触を断ちマイグレーションが抑制でき
る。保護膜11としてNiを使用するる理由は、均一な
メッキ層形成が容易に行えるためである。上記保護膜の
形成により、Agマイグレーションによる電極間のリー
クモード不良は飛躍的に減少する。
Also, in this embodiment, when Ag is used as the reflective layer 10, a migration countermeasure is required. In this case, as shown in FIG. 4A, a protective film 11 made of a Ni plating layer is formed on the surface of the Ag plating layer that is the reflection layer 10. Thereby, the contact between water and Ag that have penetrated into the resin can be cut off to suppress migration. The reason why Ni is used as the protective film 11 is that a uniform plating layer can be easily formed. Due to the formation of the protective film, leak mode defects between electrodes due to Ag migration are dramatically reduced.

【0042】この保護膜11の効果は、図4(b)に示
す厚膜のp側電極の反射層3bをAgを用いて形成した
発光素子の場合も同様である。
The effect of the protective film 11 is the same in the case of a light emitting element in which the reflective layer 3b of the thick p-side electrode shown in FIG. 4B is formed using Ag.

【0043】このように、透明電極52aの表面にAg
等の金属をメッキ法によって付着させた反射層10を設
けることによって、活性層からの光は反射層10によっ
て主光取り出し面側に反射される。したがって、光が発
光素子50の外に出たものを再度通過させて回収する従
来構造に比べると、発光エネルギーの減衰を小さく抑え
ることができ、発光輝度の向上が図られる。
As described above, Ag is applied to the surface of the transparent electrode 52a.
By providing the reflective layer 10 on which a metal such as is adhered by a plating method, light from the active layer is reflected by the reflective layer 10 to the main light extraction surface side. Therefore, as compared with the conventional structure in which the light that has exited the light emitting element 50 is passed again and collected, the attenuation of the light emission energy can be suppressed to be small, and the light emission luminance can be improved.

【0044】また、発光域となる透明電極52aは他の
部分よりも高温となる傾向にあり、透明電極52aは極
めて薄くその熱伝導率も小さいので、発光輝度の熱に対
する影響は無視できない。これに対し、透明電極52a
にはAgメッキによる反射層10が積層されて肉厚化さ
れているので、Agの高い熱伝導率によって放熱量も増
える。したがって、Agによる発光輝度の向上だけでな
く、過熱を防いで耐性の向上も図れる。そして、反射層
10は透明電極52aの表面だけでなく、バンプ電極5
やSiダイオード7のn側電極7aの表面にも形成され
るので、表面積の拡大とAgによる熱伝導を利用して放
熱性を更に向上させることができる。
The temperature of the transparent electrode 52a, which is a light-emitting region, tends to be higher than that of other portions. Since the transparent electrode 52a is extremely thin and has a small thermal conductivity, the influence of light emission luminance on heat cannot be ignored. On the other hand, the transparent electrode 52a
Since the reflective layer 10 formed by Ag plating is laminated and thickened, the heat dissipation increases due to the high thermal conductivity of Ag. Therefore, not only the emission luminance by Ag can be improved, but also the resistance can be improved by preventing overheating. The reflective layer 10 is formed not only on the surface of the transparent electrode 52a but also on the bump electrode 5a.
Also, since it is formed on the surface of the n-side electrode 7a of the Si diode 7, the heat dissipation can be further improved by utilizing the expansion of the surface area and the heat conduction by Ag.

【0045】また、保護膜11を更に被せることによっ
て、透明電極52aの表面を更に厚膜化できるので、そ
の熱容量の増加と放熱性が更に向上し、発光素子50の
耐性が改善される。
Further, by further covering the protective film 11, the surface of the transparent electrode 52a can be further thickened, so that the heat capacity and the heat dissipation are further improved, and the durability of the light emitting element 50 is improved.

【0046】図5は本発明の半導体発光装置の反射層1
0及び保護膜11の製造方法の工程を示す概略図であ
る。
FIG. 5 shows the reflection layer 1 of the semiconductor light emitting device of the present invention.
FIG. 2 is a schematic view illustrating steps of a method for manufacturing a protective film 11 and a protective film 11.

【0047】図において、n型のシリコンを材料とした
ウエハー12にSiダイオード7のパターンを形成した
ものを材料として準備する。このウエハー12は、図3
に示すSiダイオード素子のp型半導体領域7eを形成
するとともに、n側及びp側の電極7a,7bのパター
ンを一面側に形成し、他面側にはn電極7cを形成した
ものである。
In the drawing, a wafer 12 made of n-type silicon and having a pattern of Si diodes 7 formed thereon is prepared as a material. This wafer 12 is shown in FIG.
In addition to the formation of the p-type semiconductor region 7e of the Si diode element shown in FIG. 1, the patterns of the n-side and p-side electrodes 7a and 7b are formed on one side, and the n-side electrode 7c is formed on the other side.

【0048】一方、n側及びp側の電極51a,52b
にマイクロバンプ4,5をメッキ方式またはスタッド方
式によって形成したウエハーからダイシングした発光素
子50の単体をエキスパンドシート上に並べておく。そ
して、発光素子50をコレットにより吸着ピックアップ
し、ウエハー12のn側及びp側の電極7a,7bのパ
ターンに合わせて、マイクロバンプ5,4を接触させ加
重,熱,超音波により溶融接合させウエハー12上に固
定する。この場合、マイクロバンプはウエハー12のn
側及びp側の電極7a,7b側に形成しておいても良
い。
On the other hand, the n-side and p-side electrodes 51a, 52b
The light emitting elements 50 singly diced from a wafer having micro bumps 4 and 5 formed by plating or stud are arranged on an expanded sheet. Then, the light emitting element 50 is picked up by a collet, and the micro bumps 5 and 4 are brought into contact with each other in accordance with the patterns of the n-side and p-side electrodes 7a and 7b of the wafer 12, and the wafer is melt-bonded by weighting, heat and ultrasonic waves. 12 on. In this case, the micro bumps are
It may be formed on the side of the electrodes 7a and 7b on the p-side and the p-side.

【0049】次いで、発光素子50を搭載したウエハー
12を電解メッキ槽13の中の電解メッキ液14の中に
浸漬する。この電解メッキ槽13にはメッキのための陽
電極13aをウエハー12と対峙する位置に配置し、ウ
エハー12の裏面のn電極7cをメッキの陰電極として
備え、これらの陽電極13aとn電極7cとの間に電源
を接続することによって、電解メッキ槽13の中のメッ
キ液を電気分解する。これによりまず反射層のAgメッ
キの場合は、メッキ液中のAgイオンがウエハー12の
n電極7cに導通するn側電極7a,マイクロバンプ
5,発光素子50のp側電極52b及び透明電極52a
の表面に析出付着され、図3に示したようにAgの反射
層10が形成される。
Next, the wafer 12 on which the light emitting elements 50 are mounted is immersed in the electrolytic plating solution 14 in the electrolytic plating tank 13. In the electrolytic plating tank 13, a positive electrode 13a for plating is arranged at a position facing the wafer 12, and an n-electrode 7c on the back surface of the wafer 12 is provided as a negative electrode for plating. By connecting a power source between the plating solution and the plating solution, the plating solution in the electrolytic plating tank 13 is electrolyzed. Accordingly, first, in the case of Ag plating of the reflective layer, the n-side electrode 7a, the microbump 5, and the p-side electrode 52b and the transparent electrode 52a of the light emitting element 50, in which Ag ions in the plating solution are conducted to the n-electrode 7c of the wafer 12.
Is deposited and adhered to the surface of the substrate to form an Ag reflective layer 10 as shown in FIG.

【0050】その後、ウエハー12を取り出して十分洗
浄した後、ダイサーによりダイシングし、これによって
発光素子50の透明電極52aを含む部分にAgの反射
層10を形成した発光素子50とSiダイオード7とに
よる複合素子が得られる。
Thereafter, the wafer 12 is taken out and washed sufficiently, and then diced by a dicer. Thereby, the light emitting element 50 in which the Ag reflective layer 10 is formed on the portion including the transparent electrode 52a of the light emitting element 50 and the Si diode 7 are used. A composite device is obtained.

【0051】なお、図4(a)に示した保護膜11を設
ける例の場合では、Agの反射層10を形成した後に、
別の電解メッキ槽の中の保護膜11用の金属メッキ液中
に浸漬し、同様の操作によって保護膜11を電解メッキ
法によって形成すればよい。また、図4(b)に示すよ
うに厚膜のp側電極3をもつ発光素子1においても、p
側電極3にAgを用いる場合は、ウエハー12に接合後
電解メッキ槽の中の保護膜11用の金属メッキ液中に浸
漬し、同様の操作によって保護膜11を電解メッキ法に
よって形成することができる。
In the case of the example in which the protective film 11 is provided as shown in FIG. 4A, after forming the reflective layer 10 of Ag,
The protective film 11 may be immersed in a metal plating solution for the protective film 11 in another electrolytic plating tank, and the protective film 11 may be formed by an electrolytic plating method by the same operation. Also, as shown in FIG. 4B, in the light emitting element 1 having the thick p-side electrode 3,
When Ag is used for the side electrode 3, after bonding to the wafer 12, the protective film 11 may be immersed in a metal plating solution for the protective film 11 in the electrolytic plating tank, and the protective film 11 may be formed by the electrolytic plating method by the same operation. it can.

【0052】図6はSiダイオード7を製造するための
ウエハー12に形成されたn側電極7aとp側電極7b
のパターン及びn電極7cとの導通構造を示す図であ
る。
FIG. 6 shows an n-side electrode 7a and a p-side electrode 7b formed on a wafer 12 for manufacturing the Si diode 7.
FIG. 5 is a diagram showing a pattern and a conductive structure with an n-electrode 7c.

【0053】図6(a)に示すように、メッキ形成面は
n側電極7aと同電位のバンプ5と発光素子50のp側
電極52bと透明電極52aであるので、陰電極として
は裏面のn電極7cではなく、n側電極7aが好まし
い。というのは、裏面のn電極7cと表面のn側電極7
aとの間には単位面積当たり数オームの抵抗Rが存在す
るので、透明電極52aにメッキをつきやすくするため
にはn側電極7aにメッキの陰電極を取るのが好ましい
のである。さらに図6(b)に示すように隣接するn側
電極7aは同電位にするために接続電極9によって全て
導通させるのが好ましいのである。
As shown in FIG. 6A, the plating surface is the bump 5 having the same potential as the n-side electrode 7a, the p-side electrode 52b of the light emitting element 50, and the transparent electrode 52a. It is preferable to use the n-side electrode 7a instead of the n-electrode 7c. That is, the n-side electrode 7c on the back surface and the n-side electrode 7 on the front surface
Since a resistance R of several ohms per unit area exists between the transparent electrode 52a and the transparent electrode 52a, it is preferable to use a negative electrode for plating on the n-side electrode 7a in order to facilitate plating on the transparent electrode 52a. Further, as shown in FIG. 6B, it is preferable that all adjacent n-side electrodes 7a are made conductive by the connection electrodes 9 in order to make them the same potential.

【0054】しかし、メッキ電極間に流す電流は、0.
03mA/mm2 程度と小電流であるため、裏面電極7
cをメッキの陰電極としても不都合は生じない。
However, the electric current flowing between the plating electrodes is 0.1.
Since the current is as small as about 03 mA / mm 2,
No inconvenience occurs even if c is used as a negative electrode for plating.

【0055】以上により、透明電極52aの全面にAg
メッキによる反射層10が形成されるので、先に説明し
たように、活性層から透明電極52aを抜ける光は反射
層10によって反射されるので、発光輝度が向上する。
また、Agメッキはp側電極52b,マイクロバンプ5
及びSiダイオード7のn側電極7aにも付着するの
で、各部の放熱が促され、発光への熱の影響を抑えるこ
とができる。
As described above, Ag is formed on the entire surface of the transparent electrode 52a.
Since the reflection layer 10 is formed by plating, as described above, the light that passes through the transparent electrode 52a from the active layer is reflected by the reflection layer 10, so that the light emission luminance is improved.
Ag plating is performed on the p-side electrode 52b, the micro bump 5
In addition, since it also adheres to the n-side electrode 7a of the Si diode 7, heat radiation of each part is promoted, and the influence of heat on light emission can be suppressed.

【0056】なお、図示の例では静電気保護用のSiダ
イオード7との組み合わせとしたが、発光素子50のn
側及びp側の電極51a,52bに導通する電極を備え
ていて、電解メッキのための導通構造が得られる基板等
を対象としてもよい。
In the illustrated example, the combination with the Si diode 7 for protecting the static electricity is used.
A substrate or the like which has electrodes conducting to the p-side and p-side electrodes 51a and 52b and can provide a conducting structure for electrolytic plating may be used.

【0057】図7は請求項1の要件を備えた本発明の半
導体発光装置であり、反射層10の表面に保護膜11を
形成した複合素子をリードフレームに搭載接合し、シリ
コーン樹脂とエポキシ樹脂でモールドしたLEDランプ
の縦断面図である。
FIG. 7 shows a semiconductor light emitting device according to the present invention having the requirements of claim 1, wherein a composite element having a protective film 11 formed on the surface of a reflective layer 10 is mounted and joined to a lead frame, and a silicone resin and an epoxy resin are attached. It is a longitudinal cross-sectional view of the LED lamp molded with.

【0058】この構造を詳しく説明すると、リードフレ
ームのマウント部6aに図4の(a)に示す反射層10
の表面に保護膜11を形成した複合素子を導通接続した
後に、フリップチップ型半導体発光素子50とSiダイ
オード素子7の接合隙間にシリコーン樹脂15を充填す
る。そして、このマウント部を含めてリードフレーム6
の先端をエポキシ樹脂8でモールドする。ただし、フリ
ップチップ型半導体発光素子50の光取り出し面上には
シリコーン樹脂は被覆しないようにする。その理由は、
シリコーン樹脂の光透過率がモールド用のエポキシ樹脂
より悪く、また屈折率がエポキシ樹脂より小さいため光
取り出し効率が悪くなるためである。
The structure will be described in detail. The reflection layer 10 shown in FIG.
After the composite element having the protective film 11 formed on the surface thereof is conductively connected, the bonding gap between the flip-chip type semiconductor light emitting element 50 and the Si diode element 7 is filled with the silicone resin 15. Then, the lead frame 6 including this mounting portion
Is molded with epoxy resin 8. However, the light extraction surface of the flip-chip type semiconductor light emitting element 50 is not covered with the silicone resin. The reason is,
This is because the light transmittance of the silicone resin is lower than that of the epoxy resin for molding, and the light extraction efficiency is lower because the refractive index is smaller than that of the epoxy resin.

【0059】この実施の形態は、反射層にAgを用いた
場合に生じるAgマイグレーションをさらに確実に防止
できる方法を示すものである。すなわち、第2の実施の
形態において、Agの反射層10の表面をNiの保護膜
11で覆った場合、樹脂を浸透してくる水分を遮断する
のでAgマイグレーションは抑制可能であるが、保護膜
11の形成工程でピンホールなどAg表面を被覆できな
い部分が生じる場合がある。その場合、ピンホールから
水分が侵入し、熱と電場が加わってAgがイオン化して
とけだしAgマイグレーションによるリークモード不良
が発生する。このようなピンホールが万一存在する場合
でも、シリコーン樹脂を図7に示す複合素子の接合隙間
に充填していれば、Agのマイグレーションは確実に抑
制されリークモード不良は発生しない。
This embodiment shows a method that can more reliably prevent Ag migration that occurs when Ag is used for the reflective layer. That is, in the second embodiment, when the surface of the Ag reflective layer 10 is covered with the Ni protective film 11, the migration of the resin is blocked, so that the Ag migration can be suppressed. In the formation process of No. 11, there may be a case where a portion that cannot cover the Ag surface, such as a pinhole, occurs. In that case, moisture invades from the pinhole, and heat and an electric field are applied to ionize Ag and melt, and a leak mode defect due to Ag migration occurs. Even if such a pinhole is present, if the silicone resin is filled in the bonding gap of the composite element shown in FIG. 7, migration of Ag is reliably suppressed and no leak mode defect occurs.

【0060】Agマイグレーションの加速信頼性試験の
結果を次の3通りの場合でまとめたものを表1に示す。
Table 1 summarizes the results of the Ag migration acceleration reliability test in the following three cases.

【0061】[0061]

【表1】 [Table 1]

【0062】は、反射層10がAg、保護膜なし、シ
リコーン樹脂なし、は、反射層10がAg、保護膜が
Ni、シリコーン樹脂なし、は、反射層がAg、保護
膜がNi、シリコーン樹脂を充填したものである。加速
試験の条件は、温度が85℃、湿度が85%、通電は、
Vf=3.3V、If=12mAである。
In the case of, the reflective layer 10 is made of Ag, without a protective film, and without a silicone resin. In the case of, the reflective layer 10 is made of Ag, with a protective film of Ni, and without a silicone resin. In the case of, the reflective layer is made of Ag, with a protective film of Ni, and a silicone resin. Is filled. The conditions of the acceleration test are as follows: temperature is 85 ° C, humidity is 85%,
Vf = 3.3 V and If = 12 mA.

【0063】表1に示すように、は24時間でリーク
モード不良が100%発生するのに対し、は、1/3
のサンプルが240時間以上でリークモード不良は発生
しておらず、また、は、500時間以上たってもリー
クモード不良は全く発生していないことが分かる。
As shown in Table 1, 100% of leak mode failures occurred in 24 hours, but 1/3
It can be seen that no leak mode failure occurred for the sample of 240 hours or more, and no leak mode failure occurred even for 500 hours or more.

【0064】[0064]

【発明の効果】本発明では、従来の透明電極を持つGa
N系化合物半導体発光素子をサブマウント素子が行列状
に形成されたウエハー上に搭載接合した後に、電解メッ
キ法によって発光素子の透明電極上に簡単に反射率の高
い反射層が形成できるので、従来のチップを用いて輝度
の向上が可能である。また、反射層にAgを用いた場合
でも、その上に保護膜を簡単に形成できるのでAgマイ
グレーションの抑制も可能であり、高輝度の発光装置が
得られる。また、透明電極及びその付近に肉厚状にメッ
キ層が形成されるので、発光面の放熱も促進され、耐性
の向上も可能となる。
According to the present invention, a Ga having a conventional transparent electrode is used.
After mounting and bonding an N-based compound semiconductor light emitting device on a wafer with submount elements formed in a matrix, a reflective layer with high reflectivity can be easily formed on the transparent electrode of the light emitting device by electrolytic plating. It is possible to improve the luminance by using this chip. Further, even when Ag is used for the reflective layer, a protective film can be easily formed thereon, so that Ag migration can be suppressed and a light emitting device with high luminance can be obtained. In addition, since a thick plating layer is formed on the transparent electrode and in the vicinity thereof, heat radiation on the light emitting surface is promoted, and resistance can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施の形態によるフリップチップ型
の半導体発光素子であって、 (a)は平面図 (b)は同図(a)のA−A線矢視による概略縦断面図
FIG. 1 is a flip-chip type semiconductor light emitting device according to an embodiment of the present invention, wherein (a) is a plan view and (b) is a schematic longitudinal sectional view taken along line AA of FIG.

【図2】図1の発光素子を備えたLEDランプの概略図FIG. 2 is a schematic diagram of an LED lamp including the light emitting device of FIG.

【図3】本発明の一実施の形態による半導体発光装置の
複合素子部の概略であって、 (a)は平面図 (b)は同図(a)のB−B線矢視による縦断面図
3A and 3B are schematic views of a composite element portion of a semiconductor light emitting device according to an embodiment of the present invention, in which FIG. 3A is a plan view, and FIG. 3B is a longitudinal section taken along line BB in FIG. Figure

【図4】反射層の表面に保護層を形成した例を示す縦断
面図であって、 (a)は電解メッキ法で形成された反射層の場合を示す
縦断面図 (b)は厚膜p側電極の反射層の場合を示す縦断面図
4A and 4B are longitudinal sectional views showing an example in which a protective layer is formed on the surface of a reflective layer, wherein FIG. 4A is a longitudinal sectional view showing a case of a reflective layer formed by an electrolytic plating method, and FIG. Longitudinal sectional view showing the case of the reflective layer of the p-side electrode

【図5】本発明の製造方法における工程の概略図FIG. 5 is a schematic view of the steps in the manufacturing method of the present invention.

【図6】本発明のメッキ工程を説明する図であって、 (a)は、電解メッキの導通構造を示す図 (b)はSiダイオードウエハーに形成されたn側電極
とp側電極のパターンの平面図
6A and 6B are diagrams illustrating a plating process of the present invention, wherein FIG. 6A illustrates a conductive structure of electrolytic plating, and FIG. 6B illustrates a pattern of an n-side electrode and a p-side electrode formed on a Si diode wafer. Top view of

【図7】複合素子をリードフレームに搭載接合してモー
ルドした例を示す縦断面図
FIG. 7 is a longitudinal sectional view showing an example in which the composite element is mounted on a lead frame and joined and molded.

【図8】GaN系化合物半導体の発光素子の例を示す斜
視図
FIG. 8 is a perspective view showing an example of a GaN-based compound semiconductor light emitting device.

【図9】図8の発光素子をSiダイオードに搭載して複
合素子化した例であって、 (a)は平面図 (b)は同図(a)C−C線矢視による縦断面図
9A and 9B are examples in which the light emitting device of FIG. 8 is mounted on a Si diode to form a composite device, wherein FIG. 9A is a plan view, FIG. 9B is a longitudinal sectional view taken along line CC of FIG.

【符号の説明】[Explanation of symbols]

1 発光素子 1a 結晶基板 1b GaNバッファ層 1c n型GaN層 1d InGaN活性層 1e p型AlGaN層 1f p型GaN層 2 n側電極 3 p側電極 3a オーミック接合層 3b 反射層 4,5 マイクロバンプ 6 リードフレーム 6a マウント部 7 Siダイオード素子 7a n側電極 7b p側電極 7c n電極 7d n型シリコン基板 7e p型半導体領域 8 エポキシ樹脂 9 接続電極 10 反射層 11 保護膜 12 ウエハー 13 電解槽 13a 陽電極 14 電解メッキ液 15 シリコーン樹脂 Reference Signs List 1 light emitting element 1a crystal substrate 1b GaN buffer layer 1c n-type GaN layer 1d InGaN active layer 1ep p-type AlGaN layer 1f p-type GaN layer 2 n-side electrode 3 p-side electrode 3a ohmic junction layer 3b reflection layer 4,5 microbump 6 Lead frame 6a Mount part 7 Si diode element 7a n-side electrode 7b p-side electrode 7c n-electrode 7d n-type silicon substrate 7e p-type semiconductor region 8 epoxy resin 9 connection electrode 10 reflective layer 11 protective film 12 wafer 13 electrolytic tank 13a positive electrode 14 Electroplating solution 15 Silicone resin

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭57−106087(JP,A) 特開 平6−314825(JP,A) 特開 平6−69546(JP,A) 特開 昭61−220344(JP,A) 特開 平9−232632(JP,A) 特開 平8−64871(JP,A) 特開 平5−159618(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 33/00 H01S 5/00 - 5/50 H01L 21/18 H01L 21/44 H01L 29/40 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-57-106087 (JP, A) JP-A-6-314825 (JP, A) JP-A-6-69546 (JP, A) JP-A-61-1986 220344 (JP, A) JP-A-9-232632 (JP, A) JP-A-8-64871 (JP, A) JP-A-5-159618 (JP, A) (58) Fields investigated (Int. 7 , DB name) H01L 33/00 H01S 5/00-5/50 H01L 21/18 H01L 21/44 H01L 29/40

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 絶縁性であって光透過型の基板の上にG
aN系化合物半導体のn型層及びp型層を積層し、前記
n型層の表面にn側電極を形成し、前記p型層の表面の
ほぼ全面に薄膜の透明電極を形成するとともにこの透明
電極の上であって前記p型層の表面の一部を占める領域
にp側電極を形成したフリップチップ型の半導体発光素
子と、前記フリップチップ型の半導体発光素子のp側及
びn側電極に対応する位置に2つの電極が形成された第
1の主面と全面電極が形成された第2の主面を持つサブ
マウント素子とからなり、前記サブマウント素子の第1
の主面の2つの電極上にマイクロバンプを介して前記フ
リップチップ型の半導体発光素子を対峙させて導通させ
る半導体発光装置の製造方法であって、前記半導体発光
素子を前記サブマウント素子が行列状に形成されたウエ
ハーの上に両素子の電極を対峙させマイクロバンプを介
して導通接合させた後に、前記ウエハーを前記発光素子
とともにAgを溶解した電解メッキ液に浸漬し、前記ウ
エハーの電極を電解用電源の負電極に接続し、電解メッ
キ法により前記Agを前記透明電極の表面に反射層とし
て付着形成することを特徴とする半導体発光装置の製造
方法。
1. A method in which G is placed on an insulating and light-transmitting substrate.
An n-type layer and a p-type layer of an aN-based compound semiconductor are laminated, an n-side electrode is formed on the surface of the n-type layer, and a thin-film transparent electrode is formed on almost the entire surface of the p-type layer. A flip-chip type semiconductor light emitting device in which a p-side electrode is formed in a region on the electrode and occupying a part of the surface of the p-type layer; and a p-side and n-side electrode of the flip-chip type semiconductor light emitting device. A submount element having a first main surface on which two electrodes are formed at corresponding positions and a second main surface on which a full-surface electrode is formed;
A method of manufacturing a semiconductor light-emitting device in which the flip-chip type semiconductor light-emitting elements are opposed to each other via micro-bumps on two main surfaces of the semiconductor light-emitting element to conduct the semiconductor light-emitting elements, wherein the sub-mount elements are arranged in a matrix. After the electrodes of both elements are opposed to each other on the wafer formed on the wafer and electrically connected via micro-bumps, the wafer is immersed together with the light emitting elements in an electrolytic plating solution in which Ag is dissolved, and the electrodes of the wafer are electrolyzed. A method for manufacturing a semiconductor light emitting device, comprising: connecting to a negative electrode of a power source for use; and forming the Ag as a reflective layer on the surface of the transparent electrode by electrolytic plating.
JP10287623A 1997-10-14 1998-10-09 Semiconductor light emitting device and method of manufacturing the same Expired - Fee Related JP3130292B2 (en)

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