JPH10308537A - Semiconductor light-emitting element - Google Patents

Semiconductor light-emitting element

Info

Publication number
JPH10308537A
JPH10308537A JP11807297A JP11807297A JPH10308537A JP H10308537 A JPH10308537 A JP H10308537A JP 11807297 A JP11807297 A JP 11807297A JP 11807297 A JP11807297 A JP 11807297A JP H10308537 A JPH10308537 A JP H10308537A
Authority
JP
Japan
Prior art keywords
semiconductor
insulating substrate
electrode
light emitting
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11807297A
Other languages
Japanese (ja)
Inventor
Tadahiro Okazaki
忠宏 岡崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP11807297A priority Critical patent/JPH10308537A/en
Publication of JPH10308537A publication Critical patent/JPH10308537A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)
  • Led Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light-emitting element whose yield and reliability are not lowered due to a wire bonding operation, even when a substrate on which a semiconductor layer is laminated in order to form a light- emitting layer is an insulating substrate, in which the substrate is not charged with static electricity, which is not broken down due to static electricity and whose performance is not lowered. SOLUTION: A light-emitting element chip 1 is composed of an insulating substrate, of a semiconductor laminated part which is laminated so as to form a light-emitting layer on the insulating substrate, of a first electrode (a p-side electrode 28) which is formed so as to be connected to a first-conductivity-type semiconductor layer on the surface side of the semiconductor laminated part, and of a second electrode (an n-side electrode 29) which is formed so as to be connected to a second-conductivity-type semiconductor layer in the semiconductor laminated part. In addition, the rear of the insulating substrate at the light-emitting element chip is bonded onto a conductive member (a first lead 2), and the second electrode is connected directly to a conductive layer by a conductive adhesive 9 via the side face of the insulating substrate.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はサファイア基板など
の絶縁性基板上に発光層を形成すべく半導体層が積層さ
れる半導体発光素子に関する。さらに詳しくは、絶縁性
基板上に積層される半導体層の表面側に2つの電極が設
けられる半導体発光素子に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light emitting device in which a semiconductor layer is laminated on an insulating substrate such as a sapphire substrate to form a light emitting layer. More specifically, the present invention relates to a semiconductor light emitting device in which two electrodes are provided on a surface side of a semiconductor layer stacked on an insulating substrate.

【0002】[0002]

【従来の技術】たとえば青色系の光を発光する発光素子
チップ(以下、LEDチップという)20を用いた発光
ランプは、図4に断面図が示されるような構造になって
いる。この青色系のLEDチップ20は、サファイア基
板21上にチッ化ガリウム(GaN)系化合物半導体を
積層して形成される。そのため、基板21の裏面から一
方の電極を取り出すことができず、第1のリード11の
先端部の湾曲部内にダイボンディングされたLEDチッ
プ20のp側電極28およびn側電極29は、第1のリ
ード11の先端部の突出部11aおよび第2のリード1
2の先端部とそれぞれ金線13によりワイヤボンディン
グされている。そして、その周囲が発光層で発光する光
を透過させる樹脂で被覆されて樹脂パッケージ14が形
成されることにより、発光ランプとして形成される。
2. Description of the Related Art For example, a light-emitting lamp using a light-emitting element chip (hereinafter, referred to as an LED chip) 20 that emits blue light has a structure as shown in a sectional view in FIG. The blue LED chip 20 is formed by stacking a gallium nitride (GaN) compound semiconductor on a sapphire substrate 21. For this reason, one electrode cannot be taken out from the back surface of the substrate 21, and the p-side electrode 28 and the n-side electrode 29 of the LED chip 20 die-bonded in the curved portion at the tip of the first lead 11 Protrusion 11a at the tip of the lead 11 and the second lead 1
2 are respectively wire-bonded with gold wires 13. Then, the periphery thereof is covered with a resin that transmits light emitted by the light emitting layer to form the resin package 14, thereby forming a light emitting lamp.

【0003】すなわち、LEDチップ20の基板が絶縁
性基板であるため、基板の裏面側に電極を設けることが
困難で、リードの先端にダイボンディングをしただけで
は一方の電極の電気的接続を得ることができない。その
ためp側電極28およびn側電極29の両方を金線など
のワイヤにより電気的に接続しなければならない。
That is, since the substrate of the LED chip 20 is an insulating substrate, it is difficult to provide an electrode on the back side of the substrate, and only by die bonding to the tip of a lead, one electrode can be electrically connected. Can not do. Therefore, both the p-side electrode 28 and the n-side electrode 29 must be electrically connected by a wire such as a gold wire.

【0004】[0004]

【発明が解決しようとする課題】金線などのワイヤによ
る電気的接続は、そのワイヤボンディング作業が熟練を
要すると共に、ボンディング強度により電気的接続が不
充分であったり、断線したりするため、歩留りが低下し
たり、信頼性が低下するという問題がある。そのため、
前述の絶縁性基板を有するLEDチップで、積層された
半導体層の表面側からp側およびn側の両電極がワイヤ
ボンディングされると一方の電極のみのワイヤボンディ
ングの場合に比べて前述の問題が倍増する。
The electrical connection using a wire such as a gold wire requires skill in wire bonding, and the electrical connection is insufficient or broken due to the bonding strength. And the reliability decreases. for that reason,
In the LED chip having the above-described insulating substrate, when the p-side and the n-side electrodes are wire-bonded from the surface side of the stacked semiconductor layers, the above-described problem is caused as compared with the case of wire bonding of only one electrode. Double.

【0005】さらに、前述のように第1のリードにダイ
ボンディングされてp側電極が第1のリードに電気的に
接続されるとp側電極とn側電極との間に絶縁性基板が
挟持されることになり、コンデンサとなってダイボンデ
ィングの前に帯電した静電気を逃がすことができない。
また第1のリードにn側電極が接続されても絶縁性の接
着剤によりダイボンディングされていると絶縁性基板が
フロートの状態でダイボンディングの前に帯電した静電
気を逃がすことができない。さらに、リードを介して外
部から静電気が入ってきた場合、この絶縁性基板に静電
気が蓄積しやすくなる。この静電気の蓄積が多くなると
キャリア(電子またはホール)が半導体層に移動して半
導体の結晶構造にクラックを生じさせ、発光特性を劣化
させるという問題がある。
Further, as described above, when the p-side electrode is electrically connected to the first lead by die bonding to the first lead, an insulating substrate is sandwiched between the p-side electrode and the n-side electrode. Therefore, it becomes a capacitor and cannot discharge static electricity charged before die bonding.
Further, even if the n-side electrode is connected to the first lead, if the insulating substrate is die-bonded with an insulating adhesive, the static electricity charged before the die bonding cannot be released in a floating state of the insulating substrate. Furthermore, when static electricity enters from the outside via the leads, the static electricity tends to accumulate on this insulating substrate. When the accumulation of the static electricity increases, carriers (electrons or holes) move to the semiconductor layer to cause cracks in the crystal structure of the semiconductor, which causes a problem of deteriorating light emission characteristics.

【0006】本発明はこのような問題を解決するために
なされたもので、発光層を形成すべく半導体層が積層さ
れる基板が絶縁性基板で、p側およびn側の両電極が基
板の表面に積層された半導体層側に設けられる場合であ
っても、ワイヤボンディングによる歩留りの低下や信頼
性の低下を招かないと共に、その基板に静電気を帯電さ
せないで、静電気による破壊や性能の低下を生じさせな
い半導体発光素子を提供することを目的とする。
The present invention has been made to solve such a problem. The substrate on which a semiconductor layer is laminated to form a light emitting layer is an insulating substrate, and both the p-side and n-side electrodes are formed of a substrate. Even if it is provided on the side of the semiconductor layer laminated on the surface, it does not cause a decrease in yield and reliability due to wire bonding, and it does not charge the substrate with static electricity. It is an object of the present invention to provide a semiconductor light emitting device that does not cause the light emitting device.

【0007】[0007]

【課題を解決するための手段】本発明による半導体発光
素子は、絶縁性基板と、該絶縁性基板上に発光層を形成
すべく半導体層が積層される半導体積層部と、該半導体
積層部の表面側の第1導電型の半導体層に電気的に接続
して設けられる第1の電極と、前記半導体積層部の一部
がエッチングにより除去されて露出する第2導電型の半
導体層に電気的に接続して設けられる第2の電極とから
発光素子チップがなり、該発光素子チップの前記絶縁性
基板の裏面が導電性部材上にボンディングされると共
に、前記第2の電極が前記絶縁性基板の側面を経て導電
性接着剤により直接前記導電性部材と接続されている。
A semiconductor light emitting device according to the present invention comprises an insulating substrate, a semiconductor laminated portion on which a semiconductor layer is laminated to form a light emitting layer on the insulating substrate, and a semiconductor laminated portion. A first electrode provided to be electrically connected to the first conductive type semiconductor layer on the front surface side; and a second conductive type semiconductor layer exposed by removing a part of the semiconductor laminated portion by etching. And a second electrode connected to the light emitting element chip, the back surface of the insulating substrate of the light emitting element chip is bonded to a conductive member, and the second electrode is connected to the insulating substrate. Is directly connected to the conductive member by a conductive adhesive.

【0008】この構成にすることにより、第2の電極が
直接導電性部材と導電性の接着剤により接続されている
ため、信頼性が低下しやすいワイヤボンディングを第1
の電極側のみにすることができる。
[0008] With this configuration, since the second electrode is directly connected to the conductive member by the conductive adhesive, the wire bonding, which tends to reduce the reliability, is performed by the first electrode.
On the electrode side only.

【0009】前記発光素子チップのダイボンディングが
導電性接着剤により行われ、該導電性接着剤の一部が前
記絶縁性基板の側面を経て前記第2の電極に繋がるよう
に設けられることにより、絶縁性基板の両面が同電位に
なるため、絶縁性基板はコンデンサの作用をせず、帯電
している静電気は放電し、その後も静電気が帯電するこ
とがない。その結果、静電気により半導体層の結晶構造
を破壊したりすることがない。
The light emitting element chip is die-bonded with a conductive adhesive, and a part of the conductive adhesive is provided so as to be connected to the second electrode via a side surface of the insulating substrate. Since both surfaces of the insulating substrate are at the same potential, the insulating substrate does not act as a capacitor, the charged static electricity is discharged, and the static electricity is not charged thereafter. As a result, the crystal structure of the semiconductor layer is not destroyed by static electricity.

【0010】前記発光層を形成すべく半導体層が積層さ
れる半導体積層部がチッ化ガリウム系化合物半導体から
なっておれば、とくに静電気に弱いチッ化ガリウム系化
合物半導体を用いた青色系の半導体発光素子の信頼性を
向上することができる。ここにチッ化ガリウム系化合物
半導体とは、III 族元素のGaとV族元素のNとの化合
物またはIII 族元素のGaの一部がAl、Inなどの他
のIII 族元素と置換したものおよび/またはV族元素の
Nの一部がP、Asなどの他のV族元素と置換した化合
物からなる半導体をいう。
If the semiconductor laminated portion on which the semiconductor layers are laminated to form the light emitting layer is made of a gallium nitride compound semiconductor, a blue semiconductor light emission using a gallium nitride compound semiconductor which is particularly susceptible to static electricity is provided. The reliability of the device can be improved. Here, the gallium nitride-based compound semiconductor refers to a compound of a group III element Ga and a group V element N, or a compound in which a part of the group III element Ga is replaced with another group III element such as Al and In. And / or a semiconductor made of a compound in which part of N of a group V element is substituted with another group V element such as P or As.

【0011】前記半導体発光素子がランプ型の発光素子
であれば、発光素子チップをダイボンディングするリー
ドの先端部を前記導電性部材とすることができ、また前
記半導体発光素子が発光素子チップをプリント基板上に
直接ボンディングして使用する場合や両端部に電極が設
けられる絶縁基板上に発光素子チップがマウントされる
チップ型発光素子の場合であれば、絶縁性基板上に設け
られる配線パターン(電極パターンを含む)を前記導電
性部材とすることができる。
If the semiconductor light-emitting element is a lamp-type light-emitting element, the tip of a lead for die-bonding the light-emitting element chip can be the conductive member. In the case of bonding directly to a substrate or in the case of a chip type light emitting element in which a light emitting element chip is mounted on an insulating substrate provided with electrodes at both ends, a wiring pattern (electrode provided on an insulating substrate) (Including patterns) can be used as the conductive member.

【0012】[0012]

【発明の実施の形態】つぎに、図面を参照しながら本発
明の半導体発光素子について説明をする。
Next, a semiconductor light emitting device of the present invention will be described with reference to the drawings.

【0013】本発明の半導体発光素子に用いられるLE
Dチップ1は、図2にその一例の断面説明図が示される
ように、サファイアなどからなる絶縁性基板21と、絶
縁性基板21上に発光層を形成すべく半導体層が積層さ
れる半導体積層部26と、半導体積層部26の表面側の
p形層25(第1導電型の半導体層)に電気的に接続し
て設けられるp側電極28(第1の電極)と、半導体積
層部26の一部がエッチングにより除去されて露出する
n形層23(第2導電型の半導体層)に電気的に接続し
て設けられるn側電極29(第2の電極)とからなって
いる。そして、図1に本発明の半導体発光素子の一実施
形態の断面説明図が示されるように、そのLEDチップ
1の絶縁性基板21の裏面が接着剤4により接着され
て、第1のリード2の先端部にダイボンディングされて
いる。そして、第1のリード2の先端部(導電性部材)
とn側電極29とが導電性接着剤9により電気的に接続
されている。
LE used in the semiconductor light emitting device of the present invention
As shown in FIG. 2, a cross-sectional view of an example of the D chip 1 includes an insulating substrate 21 made of sapphire or the like, and a semiconductor laminate in which a semiconductor layer is formed on the insulating substrate 21 to form a light emitting layer. A portion 26, a p-side electrode 28 (first electrode) electrically connected to a p-type layer 25 (first conductivity type semiconductor layer) on the surface side of the semiconductor laminated portion 26, and a semiconductor laminated portion 26. And an n-side electrode 29 (second electrode) provided to be electrically connected to the n-type layer 23 (second conductivity type semiconductor layer) that is partially removed by etching. Then, as shown in FIG. 1, a cross-sectional explanatory view of one embodiment of the semiconductor light emitting device of the present invention, the back surface of the insulating substrate 21 of the LED chip 1 is adhered by the adhesive 4 to form the first lead 2. Is die-bonded to the tip of the Then, the tip of the first lead 2 (conductive member)
And the n-side electrode 29 are electrically connected by the conductive adhesive 9.

【0014】LEDチップ1は、たとえば図2に示され
るように、サファイアからなる絶縁性基板21上にたと
えばGaNからなる低温バッファ層、クラッド層となる
n形のGaNおよび/またはAlGaN系化合物半導体
(AlとGaとの比率が種々変わり得ることを意味す
る、以下同じ)の積層構造からなるn形層23が1〜5
μm程度、バンドギャップエネルギーがクラッド層のそ
れよりも小さくなる材料、たとえばInGaN系(In
とGaの比率が種々変わり得ることを意味する、以下同
じ)化合物半導体からなる活性層24が0.05〜0.3
μm程度、p形のGaNおよび/またはAlGaN系化
合物半導体からなるp形層(クラッド層)25が0.2
〜1μm程度それぞれ積層され、半導体積層部26が形
成されている。そして、その表面に設けられる図示しな
いたとえばNiとAuの合金層からなる電流拡散メタル
層などを介して、p形層25に電気的に接続してp側電
極28がたとえばTiとAuとの積層構造により設けら
れ、積層された半導体層の一部がエッチングされて露出
するn形層23と電気的に接続してn側電極29がたと
えばTiとAlの合金層により設けられることにより、
LEDチップ1が形成されている。
As shown in FIG. 2, for example, the LED chip 1 has a low-temperature buffer layer made of, for example, GaN and an n-type GaN and / or AlGaN-based compound semiconductor (made of a cladding layer) on an insulating substrate 21 made of sapphire. The n-type layer 23 having a laminated structure of 1 to 5 means that the ratio of Al and Ga can be variously changed.
A material whose band gap energy is smaller than that of the cladding layer by about μm, for example, an InGaN-based (In
The active layer 24 made of a compound semiconductor is in the range of 0.05 to 0.3.
The thickness of the p-type layer (cladding layer) 25 made of p-type GaN and / or AlGaN-based compound semiconductor is about 0.2 μm.
The semiconductor laminated portion 26 is formed by laminating about 1 μm each. Then, the p-side electrode 28 is electrically connected to the p-type layer 25 via a current diffusion metal layer made of an alloy layer of Ni and Au (not shown) provided on the surface thereof, so that the p-side electrode 28 is formed of a laminate of Ti and Au, for example. The n-side electrode 29 is provided by a structure, and is electrically connected to the n-type layer 23 in which a part of the laminated semiconductor layer is etched and exposed, so that the n-side electrode 29 is provided by, for example, an alloy layer of Ti and Al.
An LED chip 1 is formed.

【0015】このLEDチップ1が図1に示されるよう
に、第1のリード2の湾曲部にたとえばエポキシ系の接
着剤4によりダイボンディングされると共に、n側電極
29側の絶縁性基板21の側面を経てn側電極29と第
1のリード2とが電気的に接続されるようにAgペース
トなどの導電性接着剤9が設けられている。この導電性
接着剤9による電気的接続は、n側電極29部分から絶
縁基板21の側面に沿って流れるように銀ペーストなど
の導電性接着剤を塗布して乾燥させることにより形成さ
れる。図2に示されるように、LEDチップ1の絶縁性
基板21の上層はバッファ層を含むn形層23のみで、
そのn形層23にn側電極29が設けられているため、
導電性接着剤9がその側面を経て設けられていてもp形
層とショートする恐れはない。その結果、n側電極29
と第1のリード2とはワイヤボンディングをすることな
く電気的に接続される。そして、p側電極28のみが第
2のリード3との間に金線5などのワイヤボンディング
により電気的に接続されている。そして、その周囲がL
EDチップ1により発光する光を透過するエポキシ樹脂
などによりモールドされることにより、パッケージ6が
形成されることにより、発光ランプが形成されている。
なお、第1および第2のリード2、3は、たとえばAl
などの導電性部材からなっている。
As shown in FIG. 1, the LED chip 1 is die-bonded to the curved portion of the first lead 2 by using, for example, an epoxy-based adhesive 4 and the insulating substrate 21 on the n-side electrode 29 side. A conductive adhesive 9 such as Ag paste is provided so that the n-side electrode 29 and the first lead 2 are electrically connected via the side surface. The electrical connection by the conductive adhesive 9 is formed by applying a conductive adhesive such as a silver paste so as to flow along the side surface of the insulating substrate 21 from the n-side electrode 29 and drying. As shown in FIG. 2, the upper layer of the insulating substrate 21 of the LED chip 1 is only the n-type layer 23 including the buffer layer.
Since the n-side electrode 29 is provided on the n-type layer 23,
Even if the conductive adhesive 9 is provided through the side surface, there is no danger of short-circuit with the p-type layer. As a result, the n-side electrode 29
And the first lead 2 are electrically connected without wire bonding. Only the p-side electrode 28 is electrically connected to the second lead 3 by wire bonding such as the gold wire 5. And the surrounding is L
The package 6 is formed by molding with an epoxy resin or the like that transmits light emitted by the ED chip 1, thereby forming a light emitting lamp.
The first and second leads 2 and 3 are made of, for example, Al.
And the like.

【0016】本発明によれば、以上のように、発光部を
形成する半導体積層部26が設けられる基板21が絶縁
性基板で、p側電極28およびn側電極29の両方とも
が積層された半導体層の表面側に設けられている半導体
発光素子であっても、一方のn側電極29は導電性接着
剤9によりLEDチップ1の側面を介して直接電気的に
接続されているので、ワイヤボンディングをする必要が
ない。その結果、基板に半導体基板が用いられ、裏面に
一方の電極が設けられるLEDチップと同様にワイヤボ
ンディングは一方の電極のみで行えばよく、ワイヤボン
ディングに基づく不良の増加や信頼性の低下を招くこと
がない。
According to the present invention, as described above, the substrate 21 on which the semiconductor laminated portion 26 forming the light emitting portion is provided is an insulating substrate, and both the p-side electrode 28 and the n-side electrode 29 are laminated. Even in the case of a semiconductor light emitting element provided on the surface side of the semiconductor layer, one n-side electrode 29 is directly electrically connected to the LED chip 1 via the side surface of the LED chip 1 by the conductive adhesive 9. There is no need for bonding. As a result, as in the case of an LED chip in which a semiconductor substrate is used as a substrate and one electrode is provided on the back surface, wire bonding only needs to be performed with one electrode, which causes an increase in defects due to wire bonding and a decrease in reliability. Nothing.

【0017】前述の例では、LEDチップ1をダイボン
ディングする接着剤4にエポキシ系の絶縁性接着剤を用
いたが、この接着剤にAgペーストなどの導電性接着剤
を用いることができる。その場合、LEDチップ1をダ
イボンディングするために塗布する接着剤4の量をn側
電極29側で多めに塗布しておき、LEDチップ1をダ
イボンディングすることにより、その接着剤4がLED
チップ1の絶縁性基板に沿って這い上がり、n側電極2
9と第1のリード2との接続用の導電性接着剤9を同時
に設けることができる。この構成にすることにより、少
ない工数でn側電極29と第1のリード2との電気的接
続をすることができると共に、絶縁性基板21の上面
(図2のA参照)を覆うn形層と下面(図2のB参照)
を覆う接着剤(導電性)4とが電気的に連結されて同電
位になっているため、絶縁性基板21にキャリアが帯電
してコンデンサを形成することがない。そのため、外部
に導出されるリード2、3を介して静電気が入ってきて
も絶縁性基板21に帯電することがない。その結果、静
電気が蓄積して半導体層側に流れて結晶構造を劣化させ
ることがなく、発光特性も低下しないで高特性を維持す
ることができて信頼性が向上する。
In the above-described example, an epoxy-based insulating adhesive is used as the adhesive 4 for die-bonding the LED chip 1, but a conductive adhesive such as an Ag paste can be used as the adhesive. In this case, a large amount of the adhesive 4 to be applied for die bonding the LED chip 1 is applied on the n-side electrode 29 side, and the LED chip 1 is die-bonded, so that the adhesive 4
Crawling along the insulating substrate of the chip 1 and n-side electrode 2
A conductive adhesive 9 for connecting the first lead 9 to the first lead 2 can be provided at the same time. With this configuration, the n-side electrode 29 and the first lead 2 can be electrically connected with a small number of steps, and the n-type layer covering the upper surface of the insulating substrate 21 (see FIG. 2A). And lower surface (see FIG. 2B)
(Electrically conductive) 4 covering the substrate is electrically connected and at the same potential, so that the carrier is not charged on the insulating substrate 21 and a capacitor is not formed. Therefore, even if static electricity enters through the leads 2 and 3 led out, the insulating substrate 21 is not charged. As a result, static electricity does not accumulate and flows toward the semiconductor layer to degrade the crystal structure, and high characteristics can be maintained without deteriorating light emission characteristics, thereby improving reliability.

【0018】さらに前述の例では、LEDチップ1がリ
ードの先端にボンディングされて樹脂で被覆される発光
ランプの例であったが、図3に示されるように、ガラス
エポキシなどの絶縁性基板からなるプリント基板上の配
線パターンに形成される場合でも同様である。すなわ
ち、絶縁性基板7の表面に配線パターン8a、8bが形
成され、その表面にLEDチップ1がダイボンディング
される場合でも、1つの配線パターン8aに接着剤4に
よりダイボンディングされると共に、LEDチップ1の
絶縁性基板の表面に積層されるn形層に電気的に接続し
て設けられるn側電極29が前記1つの配線パターン8
aに接続されるように、Agペーストなどの導電性接着
剤9がLEDチップ1の絶縁性基板21の側面を介して
設けられることにより、ワイヤボンディングをすること
なくn側電極29が1つの配線パターン8aと電気的に
接続される。そして他方のp側電極28は金線などのワ
イヤボンディングにより他の配線パターン8bと接続さ
れる。この場合も接着剤4に導電性接着剤が用いられる
ことにより、LEDチップ1の絶縁性基板21の両面が
同電位に保持されるため、この絶縁性基板21を介して
静電気が帯電することがない。その結果、プリント基板
上に直接ダイボンディングされる半導体発光素子でも、
そのワイヤボンディングの工数を少なくすることができ
ると共に、前述と同様に発光特性を高度に維持した信頼
性の高い半導体発光素子となる。プリント基板でなくて
セラミックスなどの絶縁基板の両端部に端子電極(電極
パターン)が設けられて、その一方にLEDチップ1が
マウントされるチップ型発光素子でも同様である。
Further, in the above-described example, the LED chip 1 is an example of a light-emitting lamp which is bonded to the tip of a lead and covered with a resin. However, as shown in FIG. The same applies to the case of forming a wiring pattern on a printed circuit board. That is, even when the wiring patterns 8a and 8b are formed on the surface of the insulating substrate 7 and the LED chip 1 is die-bonded to the surface, the LED chip 1 is die-bonded to one wiring pattern 8a by the adhesive 4 and The n-side electrode 29 electrically connected to the n-type layer laminated on the surface of the one insulating substrate is provided with the one wiring pattern 8.
The conductive adhesive 9 such as Ag paste is provided through the side surface of the insulating substrate 21 of the LED chip 1 so that the n-side electrode 29 is connected to one wiring without wire bonding. It is electrically connected to the pattern 8a. The other p-side electrode 28 is connected to another wiring pattern 8b by wire bonding such as a gold wire. Also in this case, since a conductive adhesive is used for the adhesive 4, both surfaces of the insulating substrate 21 of the LED chip 1 are held at the same potential, so that static electricity may be charged via the insulating substrate 21. Absent. As a result, even with a semiconductor light emitting device directly die-bonded on a printed circuit board,
The number of steps of the wire bonding can be reduced, and a highly reliable semiconductor light emitting device maintaining high light emitting characteristics as described above can be obtained. The same applies to a chip type light emitting element in which terminal electrodes (electrode patterns) are provided at both ends of an insulating substrate such as a ceramic substrate instead of a printed substrate, and the LED chip 1 is mounted on one of them.

【0019】なお、前述の各例ではLEDチップがダブ
ルヘテロ接合構造であったが、ダブルヘテロ接合構造で
なくても通常のpn接合構造のもでもよい。また、チッ
化ガリウム系化合物半導体でなくても絶縁性基板上に半
導体層が積層される構造の半導体発光素子であれば同様
に本発明の構造とすることができる。
In each of the above-described examples, the LED chip has a double hetero junction structure. However, the LED chip does not have to have a double hetero junction structure but may have a normal pn junction structure. Also, the structure of the present invention can be similarly applied to a semiconductor light emitting element having a structure in which a semiconductor layer is stacked on an insulating substrate even if it is not a gallium nitride compound semiconductor.

【0020】[0020]

【発明の効果】本発明によれば、絶縁性基板上に半導体
層が積層されて一面側に2つの電極が設けられる半導体
発光素子においても、ワイヤボンディングの数を増やす
必要がない。そのため、歩留りの低下や信頼性の低下を
招来することがない。
According to the present invention, it is not necessary to increase the number of wire bondings even in a semiconductor light emitting device in which a semiconductor layer is stacked on an insulating substrate and two electrodes are provided on one surface side. Therefore, the yield and the reliability are not reduced.

【0021】さらにLEDチップの絶縁性基板の裏面が
導電性接着剤によりダイボンディングされ、その上層の
半導体層の電極と電気的に接続されることにより、静電
気がLEDチップの絶縁性基板に帯電して、それが元で
素子を破壊するということがない。そのため、絶縁性基
板が用いられる半導体発光素子においても、発光特性を
高度に維持することができ、信頼性の高い半導体発光素
子が得られる。
Further, the back surface of the insulating substrate of the LED chip is die-bonded with a conductive adhesive, and is electrically connected to the electrode of the upper semiconductor layer, so that static electricity is charged on the insulating substrate of the LED chip. Therefore, it does not destroy the element by itself. Therefore, even in a semiconductor light emitting device using an insulating substrate, the light emitting characteristics can be maintained at a high level, and a highly reliable semiconductor light emitting device can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体発光素子の一実施形態の断面説
明図である。
FIG. 1 is an explanatory sectional view of one embodiment of a semiconductor light emitting device of the present invention.

【図2】図1のLEDチップの一例の断面説明図であ
る。
FIG. 2 is an explanatory sectional view of an example of the LED chip of FIG. 1;

【図3】本発明の半導体発光素子の他の実施形態の断面
説明図である。
FIG. 3 is an explanatory sectional view of another embodiment of the semiconductor light emitting device of the present invention.

【図4】従来の絶縁性基板を有するLEDチップを用い
た発光ランプの一例の説明図である。
FIG. 4 is an explanatory diagram of an example of a conventional light emitting lamp using an LED chip having an insulating substrate.

【符号の説明】[Explanation of symbols]

1 LEDチップ 2 第1のリード 3 第2のリード 9 導電性接着剤 21 絶縁性基板 23 n形層 25 p形層 26 半導体積層部 28 p側電極 29 n側電極 REFERENCE SIGNS LIST 1 LED chip 2 first lead 3 second lead 9 conductive adhesive 21 insulating substrate 23 n-type layer 25 p-type layer 26 semiconductor lamination portion 28 p-side electrode 29 n-side electrode

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性基板と、該絶縁性基板上に発光層
を形成すべく半導体層が積層される半導体積層部と、該
半導体積層部の表面側の第1導電型の半導体層に電気的
に接続して設けられる第1の電極と、前記半導体積層部
の一部がエッチングにより除去されて露出する第2導電
型の半導体層に電気的に接続して設けられる第2の電極
とから発光素子チップがなり、該発光素子チップの前記
絶縁性基板の裏面が導電性部材上にボンディングされる
と共に、前記第2の電極が前記絶縁性基板の側面を経て
導電性接着剤により直接前記導電性部材と接続されてな
る半導体発光素子。
An electrical connection is made between an insulating substrate, a semiconductor laminated portion on which a semiconductor layer is laminated to form a light emitting layer on the insulating substrate, and a first conductivity type semiconductor layer on the surface side of the semiconductor laminated portion. A first electrode provided by being electrically connected to the first electrode and a second electrode provided by being electrically connected to a second conductive type semiconductor layer in which a part of the semiconductor laminated portion is removed by etching and exposed. A light emitting element chip is formed, the back surface of the insulating substrate of the light emitting element chip is bonded on a conductive member, and the second electrode is directly connected to the conductive substrate by a conductive adhesive through a side surface of the insulating substrate. Semiconductor light-emitting element connected to a conductive member.
【請求項2】 前記発光素子チップのダイボンディング
が導電性接着剤により行われ、該導電性接着剤の一部が
前記絶縁性基板の側面を経て前記第2の電極に繋がるよ
うに設けられてなる請求項1記載の半導体発光素子。
2. The light emitting element chip is die-bonded with a conductive adhesive, and a part of the conductive adhesive is provided so as to be connected to the second electrode via a side surface of the insulating substrate. The semiconductor light-emitting device according to claim 1.
【請求項3】 前記発光層を形成すべく半導体層が積層
される半導体積層部がチッ化ガリウム系化合物半導体か
らなる請求項1または2記載の半導体発光素子。
3. The semiconductor light emitting device according to claim 1, wherein the semiconductor laminated portion on which the semiconductor layer is laminated to form the light emitting layer is made of a gallium nitride compound semiconductor.
【請求項4】 前記導電性部材が、発光素子チップをダ
イボンディングするリードの先端部または絶縁性基板上
に設けられる配線パターンである請求項1、2または3
記載の半導体発光素子。
4. The conductive member is a wiring pattern provided on an end portion of a lead for die-bonding a light emitting element chip or on an insulating substrate.
The semiconductor light-emitting device according to claim 1.
JP11807297A 1997-05-08 1997-05-08 Semiconductor light-emitting element Pending JPH10308537A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11807297A JPH10308537A (en) 1997-05-08 1997-05-08 Semiconductor light-emitting element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11807297A JPH10308537A (en) 1997-05-08 1997-05-08 Semiconductor light-emitting element

Publications (1)

Publication Number Publication Date
JPH10308537A true JPH10308537A (en) 1998-11-17

Family

ID=14727317

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11807297A Pending JPH10308537A (en) 1997-05-08 1997-05-08 Semiconductor light-emitting element

Country Status (1)

Country Link
JP (1) JPH10308537A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100562488B1 (en) * 1997-07-15 2006-06-08 로무 가부시키가이샤 Semiconductor light emitting device
JP2011510493A (en) * 2008-01-19 2011-03-31 鶴山麗得電子實業有限公司 LED, package structure with LED, and method of manufacturing LED

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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JP2011510493A (en) * 2008-01-19 2011-03-31 鶴山麗得電子實業有限公司 LED, package structure with LED, and method of manufacturing LED

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