JP3627822B2 - Semiconductor light emitting device and manufacturing method thereof - Google Patents

Semiconductor light emitting device and manufacturing method thereof Download PDF

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JP3627822B2
JP3627822B2 JP19422494A JP19422494A JP3627822B2 JP 3627822 B2 JP3627822 B2 JP 3627822B2 JP 19422494 A JP19422494 A JP 19422494A JP 19422494 A JP19422494 A JP 19422494A JP 3627822 B2 JP3627822 B2 JP 3627822B2
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side electrode
light emitting
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semiconductor light
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JPH0864872A (en
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幸男 尺田
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Rohm Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body

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Description

【０００１】
【産業上の利用分野】
本願発明は、半導体発光素子およびその製造方法に関し、特に発光作用を行わせるための素子本体に対してサブマウント部材を付加的に取り付けて構成される半導体発光素子およびその製造方法に関する。
【０００２】
【従来の技術】
近年においては、有機金属化学気相成長法（以下、ＭＯＣＶＤ法という）を利用して、サファイア基板上に窒化ガリウム系化合物半導体の結晶を成長させることなどにより、高輝度特性を備えた青色発光用の半導体発光素子が開発されるに至っている。
【０００３】
上記高輝度の青色発光用半導体発光素子は、図９に示すように、透明のサファイア基板７０上にＧａＮのバッファ層７１を成長させ、このバッファ層７１の表面上に、Ｎ型半導体層７２（ＧａＮ層、ＡｌＧａＮ層）、発光層７３（ＩｎＧａＮ層）、およびＰ型半導体層７４（ＡｌＧａＮ層、ＧａＮ層）を積層状に成長させたものである。そして、上記Ｎ型半導体層７２におけるＧａＮ層と、Ｐ型半導体層７４におけるＧａＮ層とに、Ｎ側電極７５およびＰ側電極７６がそれぞれ形成される。
【０００４】
一方、被マウント部材である図示例のリードフレーム７７に対する上記半導体発光素子の取り付け構造は、上記Ｎ側電極７５およびＰ側電極７６を双方共に、ワイヤ７８，７９を用いてリードフレーム７７のＮ側端子部７７ａとＰ側端子部７７ｂとにそれぞれボンディングされた状態にある。そして、このように取り付けられた半導体発光素子は、同図に矢印で示すように、上記電極７６の配設側の面から光を発するように構成されている。
【０００５】
【発明が解決しようとする課題】
ところで、上記従来の半導体発光素子は、リードフレーム等の被マウント部材における２箇所に対してワイヤボンディングを施す必要があり、その搭載作業あるいは結線作業の工程数が増加するなどして、作業の煩雑化ならびに複雑化を余儀なくされているのが実情であった。
【０００６】
また、この種の半導体発光素子は、電極の配設面側から光から発せられる構成であることから、図１０に示すように、発光領域Ａ内に電極７６が存在しており、この電極７６の配設箇所は非発光部となる。したがって、実質的発光領域は上記電極７６に相当する分だけ狭くなり、図示例のものでは、素子全体中に占める実質的発光領域は全表面積の１／２以下になる。この結果、上述のように高輝度特性を備えているにも拘らず、十分な発光量を得ることができず、各種表示ボード等への使用時における高い明度の要請に応じることが困難になるという問題を有している。
【０００７】
本願発明は、上述の事情のもとで考え出されたものであって、半導体発光素子の被マウント部材に対するワイヤボンディングの個数を削減して、その結線作業を簡便に行えるようにするとともに、半導体発光素子における実質的発光領域を可及的に増大させて十分な発光量の確保および明度の向上を図ることをその課題とする。
【０００８】
【課題を解決するための手段】
上記の課題を解決するため、本願発明では、次の技術的手段を講じている。
【０００９】
すなわち、本願の請求項１に記載した発明は、透明のサファイア基板の表面上にＮ型半導体層、発光層、およびＰ型半導体層を形成し、かつ上記Ｐ型半導体層の表面にＰ側電極が形成され、上記Ｎ型半導体層における露出表面部にＮ側電極を形成して構成される素子本体と、
導電性基板の表面に対して絶縁状態となるように形成された補助Ｎ側電極層および導通状態となるように直接的かつ平面的に形成された補助Ｐ側電極層を有するサブマウント部材と、を備えるとともに、
上記素子本体の上記Ｎ側電極および上記Ｐ側電極の表面部分は絶縁層で覆われており、この絶縁層には上記双方の電極にそれぞれ独立して通じる各貫通孔が穿設され、かつ上記絶縁層の表面側には各貫通孔を介して上記双方の電極にそれぞれ導通状態となる各付着用金属層が相互に独立して形成されているとともに、この各付着用金属層は、上記サブマウント部材の双方の補助電極層に対して接合付着された状態となるように構成されていることにより、
上記サブマウント部材と上記素子本体との双方の表面側を相互に対向させて配置し、かつ、上記補助Ｎ側電極層と上記Ｎ側電極との間、および上記補助Ｐ側電極層と上記Ｐ側電極との間がそれぞれ導通状態となるように、上記サブマウント部材と上記素子本体とを一体化させ、上記透明のサファイア基板の裏面側から光が発せられるようにしたことを特徴としている。
【００１２】
また、本願の請求項２に記載した発明は、上記請求項１に記載した半導体発光素子の製造方法であって、
上記素子本体を作製した後に、その表面部分に対して上記絶縁層を形成し、この後、その絶縁層に上記各貫通孔を穿設し、しかる後、その絶縁層の表面側に上記各付着用金属層を形成する第１の工程と、上記サブマウント部材を作製する第２の工程とを別々に実行し、
その後、上記素子本体の表面側と上記サブマウント部材の表面側とを対向させた状態の下で、上記各付着金属層と上記各補助電極層とを直接的に接着させるようにしたことを特徴としている。
【００１３】
【発明の作用および効果】
上記請求項１に記載した発明によれば、リードフレーム等のＰ側端子部に対して、上記半導体発光素子のサブマウント部材をボンディングすることにより、素子本体のＰ側電極は、サブマウント部材の補助Ｐ側電極層から導電性基板を介して上記リードフレーム等のＰ側端子部に導通した状態となる。したがって、素子本体のＰ側電極に対するワイヤボンディングが不要になり、この種の半導体発光素子のマウント作業あるいは結線作業が簡便化されるという利点が得られる。
【００１４】
さらに、上記素子本体からの発光は、両電極の配設面とは反対側の面であるサファイア基板の裏面からなされることになり、従来のようにＰ側電極が発光を阻害することはなくなる。これにより、サファイア基板の裏面の大半が実質的発光領域となり、十分な発光量を確保できるとともに、この種の半導体発光素子の使用時における高い明度の要請に応じることが可能になる。
【００１５】
また、上記素子本体の発光層からサブマウント部材側に発せられた光は、サブマウント部材の表面の補助電極層等で反射することになるので、上記素子本体における透明性基板の裏面からのトータル発光量は、上記の反射光をも含んでさらに増大し、より高い明度を得ることが可能になる。
【００１６】
また、上記素子本体の両電極の表面部分を覆っている絶縁層のさらに表面側に独立して形成されている各付着用金属層を、上記サブマウント部材の両補助電極層に接合付着させるだけで、上記サブマウント部材の両補助電極を上記素子本体の両電極に対して導通状態にできるようになる。したがって、上記サブマウント部材と上記素子本体との電気的接続作業が簡単に行えるとともに、その相対的位置誤差についても厳格な制約が緩和され、位置決めあるいは位置合わせの自由度が増大する。
【００１８】
上記請求項２に記載した発明によれば、量産化の促進が図られるとともに、製作作業の複雑化が回避される。
【００１９】
【実施例の説明】
以下、本願発明の好ましい実施例を、図面を参照しつつ具体的に説明する。
【００２０】
図１は本願発明の第１実施例に係る半導体発光素子の構成要素である素子本体を示す概略縦断正面図、図２はその概略平面図、図３は上記半導体発光素子の構成要素であるサブマウント部材を示す概略縦断正面図、図４はその概略平面図、図５は上記半導体発光素子の全体構成ならびにリードフレームへの取り付け状態を示す概略縦断面図である。
【００２１】
図１に示すように、第１実施例に係る半導体発光素子１の素子本体２は、基本的には、絶縁基板であるサファイア基板３上に、Ｎ型半導体層４と、発光層５と、Ｐ型半導体層６とを備えて構成される積層部７を形成したものである。詳細には、上記積層部７は、透明または半透明のサファイア基板３の表面上に窒化ガリウム（ＧａＮ）のバッファ層８を成長させ、その表面側に、下層部分から順に、Ｎ型ＧａＮの層４１と、Ｎ型Ａｌ０．２ Ｇａ０．８ Ｎの層４２と、発光層としてのＩｎ０．１５Ｇａ０．８５Ｎの層５と、Ｐ型Ａｌ０．２ Ｇａ０．８ Ｎの層６１と、Ｐ型ＧａＮの層６２と、を形成したものである。そして、上記発光層５からは、青色に対応した波長（好ましくは４７０ｎｍ）の光が発せられるようになっている。
【００２２】
加えて、上記Ｎ型ＧａＮの層４１およびＮ型Ａｌ０．２ Ｇａ０．８ Ｎの層４２には、Ｓｉが添加され、Ｐ型Ａｌ０．２ Ｇａ０．８ Ｎの層６１およびＰ型ＧａＮの層６２には、Ｍｇが添加されているとともに、上記Ｉｎ０．１５Ｇａ０．８５Ｎの層５にはＺｎが添加されている。そして、上記Ｉｎ０．１５Ｇａ０．８５Ｎの層５におけるＩｎのＧａに対する組成比（混晶比）を増加させた場合には、この層５から発せられる光の波長が長くなるとともに、上記Ｚｎの添加量を増加させた場合には、上記組成比を増加させた場合よりもさらに光の波長が長くなるという特性を備えている。なお、上記各層の厚みは、下層側から各層４１、４２、５、６１、６２のそれぞれの順に、たとえば３μｍ、３００ｎｍ、５０ｎｍ、３００ｎｍ、１５０ｎｍに設定されている。
【００２３】
上記図示例の素子本体２は、最終的に単一のチップとして得られるたとえば平面視が一辺０．５ｍｍの正方形状のものであるが、実際の製造に際しては、ＭＯＣＶＤ法により上記図示例の構造のものを所定面積のウエハとして一括して形成した後、ダイシングにより上記単一のチップに分割することにより得られる。
【００２４】
そして、上記Ｎ型半導体層４におけるＧａＮ層４１のエッチングにより除去した露出表面部にＮ側電極９が形成され、Ｐ型半導体層６におけるＧａＮ層の表面部にＰ側電極１０が形成されている。なお、このＮ側電極９とＰ側電極１０とは、概略的には、図２に示すような平面視形状とされた上で配設されている。
【００２５】
一方、図３に示すように、この第１実施例に係る半導体発光素子１のサブマウント部材１１は、不透明の導電性を有するシリコン基板１２の表面にＳｉＯ２ でなる絶縁酸化皮膜１３を形成し、その中央部をエッチングで除去して補助Ｐ側電極層１４を形成し、かつその外周側における上記酸化皮膜１３の表面部に補助Ｎ側電極層１５を形成したものである。この双方の補助電極層１４，１５は、ＡｕとＳｎとの合金あるいはインジウム系の合金を使用して蒸着により形成したものであり、後述するように電極とハンダ用メタルとを兼用するものである。
【００２６】
そして、上記補助Ｐ側電極層１４と補助Ｎ側電極層１５とは、概略的には、図４に示すような平面視形状とされた上で配設されている。加えて、同図に示すように、シリコン基板１２の一側部には、２箇所の補助Ｎ側電極層１５に導通される帯状の補助Ｎ側電極層１５ａが、上記絶縁酸化皮膜１３の表面部に形成されている。
【００２７】
次に、上記の構成を備えた素子本体２とサブマウント部材１１とを接合一体化させて半導体発光素子１を製造する方法、ならびにこれによって得られる半導体発光素子１の構成について説明する。
【００２８】
まず、上記素子本体２とサブマウント部材１１とを別々に製作した後に、この両者の表面側どうしを対向させて配置し、素子本体２のＮ側電極９およびＰ側電極１０に対してそれぞれ、サブマウント部材１１の補助Ｎ側電極層１５および補助Ｐ側電極層１４をハンダ付けする。このはんだ付け作業は、上記サブマウント部材１１の双方の補助電極層１５，１４がハンダ用メタルを兼用していることから、これらの補助電極層１５，１４を適宜溶融固化させることにより行われる。
【００２９】
この結果、図５に示すように、素子本体２のサファイア基板３の裏面３ａから矢印で示すように光が発せられる状態になる。加えて、上記素子本体の２のＰ側電極１０はサブマウント部材１１のシリコン基板１２に導通状態となる一方、素子本体２のＮ側電極９は上記シリコン基板１２に対して絶縁状態となる。なお、図１に示す素子本体２の積層部７の高さ寸法は、図５に示す積層部７の高さ寸法と比較して、説明の便宜上、長尺になっている。
【００３０】
そして、上記のようにして得られた半導体発光素子１をリードフレーム１７上に搭載するには、同図に示すように、リードフレーム１６のＰ側端子部１６ａの上面部に上記サブマウント部材１１の下面が導通状態になるようにボンディングされるとともに、サブマウント部材１１の上記帯状の補助Ｎ側電極層１５ａとリードフレーム１６のＮ側端子部１６ｂとの間にワイヤボンディング１７が施される。
【００３１】
これにより、上記素子本体２のＰ側電極１０は、導電性シリコン基板１２を通じてリードフレーム１６のＰ側端子部１６ａに導通状態とされ、かつ上記素子本体２のＮ側電極９は、ワイヤ１７を通じてリードフレーム１６のＮ側端子部１６ｂに導通状態とされる。この後は、上記半導体発光素子１の外周部を樹脂封止することなどによって、青色発光用のＬＥＤランプが得られる。
【００３２】
このような構成とすることにより、素子本体２の透明サファイア基板３の裏面３ａにおけるＮ側電極９の形成箇所以外の領域が発光領域となり、上記裏面３ａの全面積の約７５％が発光領域として利用される。したがって、従来のように電極による発光阻害が激減され、十分な発光量および高い明度を有する発光デバイスが得られることになる。
【００３３】
加えて、上記素子本体２の発光層５から下方に向かって発せられた光は、不透明のサブマウント部材１１（補助電極層１４，１５）で反射された後、サファイア基板３の裏面３ａから外方に向かって照射されることになるので、光の利用効率が向上するという利点も得られる。
【００３４】
さらに、上記サブマウント部材１１を使用したことにより、Ｐ側電極１０に対するワイヤボンディングが不要になり、結線作業の簡便化ならびに製作容易化が図られることになる。
【００３５】
次に、本願発明に係る半導体発光素子１の第２実施例を、図６、７、８を参照しつつ説明する。なお、以下の第２実施例の説明に際して、上述の第１実施例と共通の構成要件については同一符号を付してその説明を省略する。
【００３６】
この第２実施例に係る半導体発光素子１が上述の第１実施例と異なる点は、図６および図７に示すように、素子本体２の表面全域をＣＶＤ法を用いてＳｉＯ２ やＳｉ３ Ｎ４ 等からなる絶縁層１８で覆うとともに、この絶縁層１８にＮ側電極９およびＰ側電極１０にそれぞれ通じる貫通孔１９，２０を穿設し、かつ上記絶縁層１８の表面部にＡｕとＳｎとの合金あるいはインジウム系の合金等でなる金属層２１，２２を相互に独立して形成した点にある。この場合、上記各貫通孔１９，２０には、上記各金属層２１，２２が埋設されることになるので、上記一方の金属層２１は上記Ｎ側電極９に導通した状態になり、他方の金属層２２は上記Ｐ側電極１０に導通した状態になる。
【００３７】
なお、サブマウント部材１１の構成は、図７に示す各金属層２１，２２の平面視における形状および配設状態に対応して補助Ｎ側電極層１５と補助Ｐ側電極層１４とが形成されており、その他の部分、たとえば補助Ｎ側電極層１５がＳｉＯ２ 等の絶縁性皮膜１３を介して形成されている点などについては上述の第１実施例と同一の構成である。
【００３８】
そして、上記素子本体２とサブマウント部材１１とは、両者の表面側どうしが対向配置された状態で、図８に示すように各金属層２１，２２と各補助電極層１５，１４とが接合一体化されることにより、半導体発光素子１が得られる。また、図示の構成によっても、上記素子本体２のＰ側電極１０はリードフレーム１６のＰ側端子部１６ａに導電性シリコン基板１２を介して導通状態とされ、かつ上記素子本体２のＮ側電極９はリードフレーム１６のＮ側端子部１６ｂにワイヤ１７を介して導通状態とされる。
【００３９】
そして、この場合には、各金属層２１，２２と各補助電極層１５，１４との位置合わせが容易に行えることから、これらの両層の接合作業（ハンダ付け作業）、ひいては素子本体２とサブマウント部材１１との接合作業が極めて簡便に行えることになる。
【００４０】
また、この第２実施例によっても、上記第１実施例と同様に、十分な発光量を確保できることは言うまでもない。
【図面の簡単な説明】
【図１】本願発明の第１実施例に係る半導体発光素子の構成要素である素子本体を示す概略縦断正面図である。
【図２】上記第１実施例に係る素子本体の概略平面図である。
【図３】上記第１実施例に係る半導体発光素子の構成要素であるサブマウント部材の概略縦断正面図である。
【図４】上記第１実施例に係るサブマウント部材の概略平面図である。
【図５】上記第１実施例に係る半導体発光素子の全体構成ならびにその被マウント部材への取り付け状態を示す概略縦断側面図である。
【図６】本願発明の第２実施例に係る半導体発光素子の構成要素である素子本体を示す概略縦断正面図である。
【図７】上記第２実施例に係る素子本体の概略平面図である。
【図８】上記第２実施例に係る半導体発光素子の全体構成ならびにその被マウント部材への取り付け状態を示す概略縦断側面図である。
【図９】従来の半導体発光素子の全体構成ならびにその被マウント部材への取り付け状態を示す概略縦断側面図である。
【図１０】従来の半導体発光素子の概略平面図である。
【符号の説明】
１ 半導体発光素子
２ 素子本体
３ 透明絶縁性基板（サファイア基板）
４ Ｎ型半導体層
５ 発光層
６ Ｐ型半導体層
９ Ｎ側電極
１０ Ｐ側電極
１１ サブマウント部材
１２ 導電性基板（シリコン基板）
１４ 補助Ｐ側電極層
１５ 補助Ｎ側電極層[0001]
[Industrial application fields]
The present invention relates to a semiconductor light emitting device and a method for manufacturing the same, and more particularly to a semiconductor light emitting device configured by additionally attaching a submount member to an element body for performing a light emitting action and a method for manufacturing the same.
[0002]
[Prior art]
In recent years, by using metalorganic chemical vapor deposition (hereinafter referred to as MOCVD method), a crystal of a gallium nitride compound semiconductor is grown on a sapphire substrate. Semiconductor light emitting devices have been developed.
[0003]
As shown in FIG. 9, the high-luminance blue light-emitting semiconductor light-emitting device has a GaN buffer layer 71 grown on a transparent sapphire substrate 70, and an N-type semiconductor layer 72 ( A GaN layer, an AlGaN layer), a light emitting layer 73 (InGaN layer), and a P-type semiconductor layer 74 (AlGaN layer, GaN layer) are grown in a laminated form. An N-side electrode 75 and a P-side electrode 76 are formed on the GaN layer in the N-type semiconductor layer 72 and the GaN layer in the P-type semiconductor layer 74, respectively.
[0004]
On the other hand, in the mounting structure of the semiconductor light emitting element to the lead frame 77 of the illustrated example which is a mounted member, both the N side electrode 75 and the P side electrode 76 are connected to the N side of the lead frame 77 using wires 78 and 79. The terminal portion 77a and the P-side terminal portion 77b are bonded to each other. The semiconductor light emitting element attached in this way is configured to emit light from the surface on the side where the electrode 76 is disposed, as indicated by an arrow in FIG.
[0005]
[Problems to be solved by the invention]
By the way, the conventional semiconductor light emitting element needs to be wire-bonded at two places on a mounted member such as a lead frame, and the number of steps for mounting or connecting is increased. The reality is that it has been forced to become complicated and complicated.
[0006]
In addition, since this type of semiconductor light emitting element emits light from the electrode mounting surface side, an electrode 76 exists in the light emitting region A as shown in FIG. The arrangement location is a non-light emitting portion. Therefore, the substantial light emitting region is narrowed by an amount corresponding to the electrode 76, and in the example shown in the drawing, the substantial light emitting region occupying the entire element is 1/2 or less of the total surface area. As a result, a sufficient amount of light emission cannot be obtained in spite of having the high luminance characteristics as described above, and it becomes difficult to meet the demand for high brightness when used for various display boards. Has the problem.
[0007]
The invention of the present application has been conceived under the above circumstances, and the number of wire bondings to a mounted member of a semiconductor light-emitting element can be reduced so that the connection work can be easily performed, and a semiconductor It is an object of the present invention to increase a substantial light-emitting region in a light-emitting element as much as possible to secure a sufficient light emission amount and improve brightness.
[0008]
[Means for Solving the Problems]
In order to solve the above problems, the present invention takes the following technical means.
[0009]
That is, according to the first aspect of the present invention, an N-type semiconductor layer, a light emitting layer, and a P-type semiconductor layer are formed on the surface of a transparent sapphire substrate, and a P-side electrode is formed on the surface of the P-type semiconductor layer. An element body formed by forming an N-side electrode on the exposed surface portion of the N-type semiconductor layer,
A submount member having an auxiliary N-side electrode layer formed so as to be insulated from the surface of the conductive substrate, and an auxiliary P-side electrode layer formed directly and planarly so as to be conductive; With
The surface portions of the N-side electrode and the P-side electrode of the element body are covered with an insulating layer, and each through-hole that communicates with each of the electrodes independently is formed in the insulating layer, and On the surface side of the insulating layer, each adhesion metal layer that is in a conductive state with each of the two electrodes through each through-hole is formed independently of each other. By being configured to be bonded and attached to both auxiliary electrode layers of the mount member,
Both the submount member and the element body are disposed so that the surface sides thereof face each other, and between the auxiliary N-side electrode layer and the N-side electrode, and between the auxiliary P-side electrode layer and the P The submount member and the element main body are integrated so that each side electrode is in a conductive state, and light is emitted from the back side of the transparent sapphire substrate.
[0012]
The invention described in claim 2 of the present application is a method for manufacturing a semiconductor light emitting device according to claim 1 ,
After the element body is manufactured , the insulating layer is formed on the surface portion, and then the through holes are formed in the insulating layer, and then the adhesion is made on the surface side of the insulating layer. a first step of forming a use metal layer, and a second step that pollock create the sub-mount member then performed separately,
Then, under the state of being opposed to the surface side of the surface side and the sub-mount member of the device body, that it has to be directly bonded to the upper Symbol each deposited metal layer and the respective auxiliary electrode layer It is a feature.
[0013]
Operation and effect of the invention
According to the first aspect of the present invention, by bonding the submount member of the semiconductor light emitting element to the P side terminal portion of a lead frame or the like, the P side electrode of the element main body is connected to the submount member. The auxiliary P-side electrode layer is electrically connected to the P-side terminal portion such as the lead frame through the conductive substrate. This eliminates the need for wire bonding to the P-side electrode of the element body, and provides an advantage of simplifying the mounting or connecting work of this type of semiconductor light emitting element.
[0014]
Further, light emission from the element body is performed from the back surface of the sapphire substrate, which is the surface opposite to the surface on which both electrodes are disposed, and the P-side electrode does not hinder light emission as in the conventional case. . Thereby, most of the back surface of the sapphire substrate becomes a substantial light emitting region, and a sufficient amount of light emission can be secured, and it is possible to meet a demand for high brightness when using this type of semiconductor light emitting element.
[0015]
In addition, since light emitted from the light emitting layer of the element body to the submount member side is reflected by the auxiliary electrode layer on the surface of the submount member, the total from the back surface of the transparent substrate in the element body. The amount of emitted light is further increased including the above reflected light, and higher brightness can be obtained.
[0016]
Further, each deposited metal layer is formed independently on the further surface of the insulating layer covering the surface portion of the electrodes of the upper Symbol element body, are joined adhere to both the auxiliary electrode layer of the submount member Thus, both auxiliary electrodes of the submount member can be brought into conduction with both electrodes of the element body. Therefore, the electrical connection between the submount member and the element body can be easily performed, and strict restrictions on the relative position error are eased, and the degree of freedom in positioning or alignment increases.
[0018]
According to the invention described above Symbol claim 2, along with the promotion of mass production can be achieved, complication of the fabrication operations are avoided.
[0019]
[Explanation of Examples]
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.
[0020]
1 is a schematic longitudinal front view showing an element body which is a component of a semiconductor light emitting element according to a first embodiment of the present invention, FIG. 2 is a schematic plan view thereof, and FIG. 3 is a sub view which is a component of the semiconductor light emitting element. FIG. 4 is a schematic plan view showing the mount member, FIG. 4 is a schematic plan view thereof, and FIG. 5 is a schematic vertical cross-sectional view showing the overall configuration of the semiconductor light emitting device and the state of attachment to the lead frame.
[0021]
As shown in FIG. 1, the element body 2 of the semiconductor light emitting element 1 according to the first embodiment basically has an N-type semiconductor layer 4, a light emitting layer 5, an sapphire substrate 3 that is an insulating substrate, A stacked portion 7 configured to include a P-type semiconductor layer 6 is formed. More specifically, the stacked unit 7 grows a gallium nitride (GaN) buffer layer 8 on the surface of a transparent or semi-transparent sapphire substrate 3, and an N-type GaN layer sequentially from the lower layer portion on the surface side. 41, an N-type Al 0.2 Ga 0.8 N layer 42, an In 0.15 Ga 0.85 N layer 5 as a light emitting layer, and a P-type Al 0.2 Ga 0.8 N layer 61 and a P-type GaN layer 62 are formed. The light emitting layer 5 emits light having a wavelength corresponding to blue (preferably 470 nm).
[0022]
In addition, Si is added to the N-type GaN layer 41 and the N-type Al 0.2 Ga 0.8 N layer 42, and the P-type Al 0.2 Ga 0.8 N layer 61 and the P-type are added. Mg is added to the GaN layer 62, and Zn is added to the In 0.15 Ga 0.85 N layer 5. When the composition ratio (mixed crystal ratio) of In to Ga in the In 0.15 Ga 0.85 N layer 5 is increased, the wavelength of light emitted from the layer 5 becomes longer, and When the added amount of Zn is increased, the light wavelength is further increased as compared with the case where the composition ratio is increased. In addition, the thickness of each said layer is set to 3 micrometers, 300 nm, 50 nm, 300 nm, 150 nm in order of each layer 41, 42, 5, 61, 62 from the lower layer side, for example.
[0023]
The element body 2 in the illustrated example is a square shape finally obtained as a single chip, for example, having a square shape with a side of 0.5 mm in plan view. However, in actual manufacturing, the structure of the illustrated example is formed by MOCVD. Can be obtained by dividing the wafer into a single chip by dicing.
[0024]
An N-side electrode 9 is formed on the exposed surface portion removed by etching of the GaN layer 41 in the N-type semiconductor layer 4, and a P-side electrode 10 is formed on the surface portion of the GaN layer in the P-type semiconductor layer 6. . The N-side electrode 9 and the P-side electrode 10 are generally arranged in a plan view as shown in FIG.
[0025]
On the other hand, as shown in FIG. 3, the submount member 11 of the semiconductor light emitting device 1 according to the first embodiment is formed by forming an insulating oxide film 13 made of SiO 2 on the surface of an opaque conductive silicon substrate 12. The auxiliary P-side electrode layer 14 is formed by removing the central portion by etching, and the auxiliary N-side electrode layer 15 is formed on the surface portion of the oxide film 13 on the outer peripheral side. Both the auxiliary electrode layers 14 and 15 are formed by vapor deposition using an alloy of Au and Sn or an indium-based alloy. As will be described later, both the electrode and the solder metal are used. .
[0026]
The auxiliary P-side electrode layer 14 and the auxiliary N-side electrode layer 15 are roughly arranged in a plan view as shown in FIG. In addition, as shown in the figure, a band-shaped auxiliary N-side electrode layer 15 a that is electrically connected to two auxiliary N-side electrode layers 15 is provided on one side of the silicon substrate 12. It is formed in the part.
[0027]
Next, a method for manufacturing the semiconductor light emitting device 1 by joining and integrating the device body 2 and the submount member 11 having the above configuration, and the configuration of the semiconductor light emitting device 1 obtained thereby will be described.
[0028]
First, after the element body 2 and the submount member 11 are separately manufactured, the surface sides of the two are opposed to each other, and the N-side electrode 9 and the P-side electrode 10 of the element body 2 are respectively disposed. The auxiliary N-side electrode layer 15 and the auxiliary P-side electrode layer 14 of the submount member 11 are soldered. This soldering operation is performed by appropriately melting and solidifying these auxiliary electrode layers 15 and 14 since both auxiliary electrode layers 15 and 14 of the submount member 11 also serve as solder metal.
[0029]
As a result, as shown in FIG. 5, light is emitted from the back surface 3 a of the sapphire substrate 3 of the element body 2 as indicated by an arrow. In addition, the two P-side electrodes 10 of the element body are electrically connected to the silicon substrate 12 of the submount member 11, while the N-side electrode 9 of the element body 2 is insulated from the silicon substrate 12. In addition, the height dimension of the lamination | stacking part 7 of the element main body 2 shown in FIG. 1 is long compared with the height dimension of the lamination | stacking part 7 shown in FIG. 5 for convenience of explanation.
[0030]
In order to mount the semiconductor light emitting device 1 obtained as described above on the lead frame 17, the submount member 11 is formed on the upper surface of the P-side terminal portion 16a of the lead frame 16, as shown in FIG. Bonding is performed so that the lower surface of the submount member 11 is in a conductive state, and wire bonding 17 is applied between the band-shaped auxiliary N-side electrode layer 15 a of the submount member 11 and the N-side terminal portion 16 b of the lead frame 16.
[0031]
As a result, the P-side electrode 10 of the element body 2 is brought into conduction with the P-side terminal portion 16 a of the lead frame 16 through the conductive silicon substrate 12, and the N-side electrode 9 of the element body 2 is passed through the wire 17. The N-side terminal portion 16b of the lead frame 16 is brought into conduction. Thereafter, an LED lamp for blue light emission is obtained by resin sealing the outer peripheral portion of the semiconductor light emitting element 1.
[0032]
By adopting such a configuration, a region other than the formation position of the N-side electrode 9 on the back surface 3a of the transparent sapphire substrate 3 of the element body 2 becomes a light emitting region, and about 75% of the total area of the back surface 3a is a light emitting region. Used. Therefore, the light emission inhibition by the electrodes is drastically reduced as in the prior art, and a light emitting device having a sufficient light emission amount and high brightness can be obtained.
[0033]
In addition, the light emitted downward from the light emitting layer 5 of the element body 2 is reflected by the opaque submount member 11 (auxiliary electrode layers 14 and 15), and then is emitted from the back surface 3a of the sapphire substrate 3. it means that is irradiated towards also the advantage that use efficiency of light is improved.
[0034]
Furthermore, the use of the submount member 11 eliminates the need for wire bonding to the P-side electrode 10 and simplifies the wiring work and facilitates production.
[0035]
Next, a second embodiment of the semiconductor light emitting device 1 according to the present invention will be described with reference to FIGS. In the following description of the second embodiment, the same constituent elements as those in the first embodiment described above are denoted by the same reference numerals, and the description thereof is omitted.
[0036]
The semiconductor light emitting device 1 according to the second embodiment is different from the first embodiment described above in that, as shown in FIGS. 6 and 7, the entire surface of the device body 2 is made of SiO 2 or Si 3 using the CVD method. The insulating layer 18 is covered with an insulating layer 18 made of N 4 or the like, and through holes 19 and 20 are formed in the insulating layer 18 so as to communicate with the N-side electrode 9 and the P-side electrode 10, respectively. The metal layers 21 and 22 made of an alloy with Sn or an indium alloy are formed independently of each other. In this case, since the metal layers 21 and 22 are embedded in the through holes 19 and 20, the one metal layer 21 is brought into conduction with the N-side electrode 9, and the other The metal layer 22 is brought into conduction with the P-side electrode 10.
[0037]
The submount member 11 is configured such that the auxiliary N-side electrode layer 15 and the auxiliary P-side electrode layer 14 are formed corresponding to the shape and arrangement state of the metal layers 21 and 22 shown in FIG. The other portions, for example, the auxiliary N-side electrode layer 15 is formed through an insulating film 13 such as SiO 2 are the same as those in the first embodiment.
[0038]
The element body 2 and the submount member 11 are bonded to each other with the metal layers 21 and 22 and the auxiliary electrode layers 15 and 14 as shown in FIG. By being integrated, the semiconductor light emitting element 1 is obtained. Even in the illustrated configuration, the P-side electrode 10 of the element body 2 is brought into conduction with the P-side terminal portion 16a of the lead frame 16 through the conductive silicon substrate 12, and the N-side electrode of the element body 2 is also provided. 9 is brought into conduction with the N-side terminal portion 16 b of the lead frame 16 through the wire 17.
[0039]
In this case, since the alignment between the metal layers 21 and 22 and the auxiliary electrode layers 15 and 14 can be easily performed, the joining work (soldering work) of these two layers, and the element main body 2 as well. The joining work with the submount member 11 can be performed very simply.
[0040]
Needless to say, the second embodiment can secure a sufficient amount of light emission as in the first embodiment.
[Brief description of the drawings]
FIG. 1 is a schematic longitudinal sectional front view showing an element body which is a component of a semiconductor light emitting element according to a first embodiment of the present invention.
FIG. 2 is a schematic plan view of an element body according to the first embodiment.
FIG. 3 is a schematic longitudinal front view of a submount member which is a component of the semiconductor light emitting device according to the first embodiment.
FIG. 4 is a schematic plan view of a submount member according to the first embodiment.
FIG. 5 is a schematic longitudinal sectional side view showing the overall configuration of the semiconductor light emitting device according to the first embodiment and its attached state to a mounted member.
FIG. 6 is a schematic longitudinal sectional front view showing an element body which is a component of a semiconductor light emitting element according to a second embodiment of the present invention.
FIG. 7 is a schematic plan view of an element body according to the second embodiment.
FIG. 8 is a schematic longitudinal sectional side view showing the overall configuration of the semiconductor light emitting device according to the second embodiment and its mounting state on a mounted member.
FIG. 9 is a schematic longitudinal sectional side view showing an overall configuration of a conventional semiconductor light emitting element and its attached state to a mounted member.
FIG. 10 is a schematic plan view of a conventional semiconductor light emitting device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor light-emitting device 2 Element body 3 Transparent insulating substrate (sapphire substrate)
4 N-type semiconductor layer 5 Light emitting layer 6 P-type semiconductor layer 9 N-side electrode 10 P-side electrode 11 Submount member 12 Conductive substrate (silicon substrate)
14 Auxiliary P-side electrode layer 15 Auxiliary N-side electrode layer

Claims (2)

透明のサファイア基板の表面上にＮ型半導体層、発光層、およびＰ型半導体層を形成し、かつ上記Ｐ型半導体層の表面にＰ側電極が形成され、上記Ｎ型半導体層における露出表面部にＮ側電極を形成して構成される素子本体と、
導電性基板の表面に対して絶縁状態となるように形成された補助Ｎ側電極層および導通状態となるように直接的かつ平面的に形成された補助Ｐ側電極層を有するサブマウント部材と、を備えるとともに、
上記素子本体の上記Ｎ側電極および上記Ｐ側電極の表面部分は絶縁層で覆われており、この絶縁層には上記双方の電極にそれぞれ独立して通じる各貫通孔が穿設され、かつ上記絶縁層の表面側には各貫通孔を介して上記双方の電極にそれぞれ導通状態となる各付着用金属層が相互に独立して形成されているとともに、この各付着用金属層は、上記サブマウント部材の双方の補助電極層に対して接合付着された状態となるように構成されていることにより、
上記サブマウント部材と上記素子本体との双方の表面側を相互に対向させて配置し、かつ、上記補助Ｎ側電極層と上記Ｎ側電極との間、および上記補助Ｐ側電極層と上記Ｐ側電極との間がそれぞれ導通状態となるように、上記サブマウント部材と上記素子本体とを一体化させ、上記透明のサファイア基板の裏面側から光が発せられるようにしたことを特徴とする、半導体発光素子。An N-type semiconductor layer, a light emitting layer, and a P-type semiconductor layer are formed on the surface of the transparent sapphire substrate, and a P-side electrode is formed on the surface of the P-type semiconductor layer. An element body formed by forming an N-side electrode on
A submount member having an auxiliary N-side electrode layer formed so as to be insulated from the surface of the conductive substrate, and an auxiliary P-side electrode layer formed directly and planarly so as to be conductive; With
The surface portions of the N-side electrode and the P-side electrode of the element body are covered with an insulating layer, and each through-hole that communicates with each of the electrodes independently is formed in the insulating layer, and On the surface side of the insulating layer, each adhesion metal layer that is in a conductive state with each of the two electrodes through each through-hole is formed independently of each other. By being configured to be bonded and attached to both auxiliary electrode layers of the mount member,
Both the submount member and the element body are disposed so that the surface sides thereof face each other, and between the auxiliary N-side electrode layer and the N-side electrode, and between the auxiliary P-side electrode layer and the P The submount member and the element main body are integrated so that each of the side electrodes is in a conductive state, and light is emitted from the back side of the transparent sapphire substrate, Semiconductor light emitting device. 上記請求項１に記載した半導体発光素子の製造方法であって、
上記素子本体を作製した後に、その表面部分に対して上記絶縁層を形成し、この後、その絶縁層に上記各貫通孔を穿設し、しかる後、その絶縁層の表面側に上記各付着用金属層を形成する第１の工程と、上記サブマウント部材を作製する第２の工程とを別々に実行し、
その後、上記素子本体の表面側と上記サブマウント部材の表面側とを対向させた状態の下で、上記各付着金属層と上記各補助電極層とを直接的に接着させるようにしたことを特徴とする、半導体発光素子の製造方法。A method of manufacturing a semiconductor light emitting device according to claim 1 ,
After the element body is manufactured , the insulating layer is formed on the surface portion, and then the through holes are formed in the insulating layer, and then the adhesion is made on the surface side of the insulating layer. a first step of forming a use metal layer, and a second step that pollock create the sub-mount member then performed separately,
Then, under the state of being opposed to the surface side of the surface side and the sub-mount member of the device body, that it has to be directly bonded to the upper Symbol each deposited metal layer and the respective auxiliary electrode layer A method for manufacturing a semiconductor light emitting device.
JP19422494A 1994-08-11 1994-08-18 Semiconductor light emitting device and manufacturing method thereof Expired - Fee Related JP3627822B2 (en)

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