JPH0864872A - Semiconductor light emitting element and manufacture thereof - Google Patents

Semiconductor light emitting element and manufacture thereof

Info

Publication number
JPH0864872A
JPH0864872A JP19422494A JP19422494A JPH0864872A JP H0864872 A JPH0864872 A JP H0864872A JP 19422494 A JP19422494 A JP 19422494A JP 19422494 A JP19422494 A JP 19422494A JP H0864872 A JPH0864872 A JP H0864872A
Authority
JP
Japan
Prior art keywords
layer
side electrode
light emitting
auxiliary
semiconductor light
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19422494A
Other languages
Japanese (ja)
Other versions
JP3627822B2 (en
Inventor
Yukio Shakuda
幸男 尺田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP19422494A priority Critical patent/JP3627822B2/en
Priority to US08/513,624 priority patent/US5557115A/en
Publication of JPH0864872A publication Critical patent/JPH0864872A/en
Application granted granted Critical
Publication of JP3627822B2 publication Critical patent/JP3627822B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49107Connecting at different heights on the semiconductor or solid-state body

Landscapes

  • Fastening Of Light Sources Or Lamp Holders (AREA)
  • Led Device Packages (AREA)
  • Led Devices (AREA)

Abstract

PURPOSE: To simply conduct a wiring operation and to increase a substantial light emitting region of a semiconductor light emitting element as much as possible by deleting the number of bonding wires for the lead frame, etc., of the element. CONSTITUTION: The semiconductor light emitting element comprises an element assembly 2 composed by forming semiconductor layers on the surface of a transparent insulating board 3 and forming an N-type side electrode 9 and a P-type side electrode 10 at predetermined positions of the layers, and a sub- mounting member 11 having an auxiliary N-type side electrode layer 15 so formed as to reach an insulating state from the surface of the conductive substrate 12 and an auxiliary P-type side electrode layer 14 so formed as to reach a continuity state. Accordingly, both the surface sides of the member 11 and the assembly 2 are oppositely disposed, and the member 11 is integrated with the assembly 2 so as to each conductive states between the layer 15 and the electrode 9 and between the layer 14 and the electrode 10.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本願発明は、半導体発光素子およ
びその製造方法に関し、特に発光作用を行わせるための
素子本体に対してサブマウント部材を付加的に取り付け
て構成される半導体発光素子およびその製造方法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light emitting device and a method for manufacturing the same, and more particularly, to a semiconductor light emitting device constructed by additionally mounting a submount member to an element body for performing a light emitting action and the same. It relates to a manufacturing method.

【0002】[0002]

【従来の技術】近年においては、有機金属化学気相成長
法(以下、MOCVD法という)を利用して、サファイ
ア基板上に窒化ガリウム系化合物半導体の結晶を成長さ
せることなどにより、高輝度特性を備えた青色発光用の
半導体発光素子が開発されるに至っている。
2. Description of the Related Art In recent years, high brightness characteristics have been obtained by growing a gallium nitride compound semiconductor crystal on a sapphire substrate by utilizing a metal organic chemical vapor deposition method (hereinafter referred to as MOCVD method). A blue light emitting semiconductor light emitting device has been developed.

【0003】上記高輝度の青色発光用半導体発光素子
は、図9に示すように、透明のサファイア基板70上に
GaNのバッファ層71を成長させ、このバッファ層7
1の表面上に、N型半導体層72(GaN層、AlGa
N層)、発光層73(InGaN層)、およびP型半導
体層74(AlGaN層、GaN層)を積層状に成長さ
せたものである。そして、上記N型半導体層72におけ
るGaN層と、P型半導体層74におけるGaN層と
に、N側電極75およびP側電極76がそれぞれ形成さ
れる。
In the high-brightness semiconductor light emitting device for blue light emission, as shown in FIG. 9, a GaN buffer layer 71 is grown on a transparent sapphire substrate 70, and the buffer layer 7 is formed.
N-type semiconductor layer 72 (GaN layer, AlGa
The N layer), the light emitting layer 73 (InGaN layer), and the P-type semiconductor layer 74 (AlGaN layer, GaN layer) are grown in a laminated shape. Then, an N-side electrode 75 and a P-side electrode 76 are formed on the GaN layer in the N-type semiconductor layer 72 and the GaN layer in the P-type semiconductor layer 74, respectively.

【0004】一方、被マウント部材である図示例のリー
ドフレーム77に対する上記半導体発光素子の取り付け
構造は、上記N側電極75およびP側電極76を双方共
に、ワイヤ78,79を用いてリードフレーム77のN
側端子部77aとP側端子部77bとにそれぞれボンデ
ィングされた状態にある。そして、このように取り付け
られた半導体発光素子は、同図に矢印で示すように、上
記電極76の配設側の面から光を発するように構成され
ている。
On the other hand, in the mounting structure of the semiconductor light emitting element to the lead frame 77 of the illustrated example which is a mounted member, the lead frame 77 is formed by using wires 78 and 79 for both the N side electrode 75 and the P side electrode 76. N
The side terminal portion 77a and the P side terminal portion 77b are bonded to each other. The semiconductor light emitting element thus mounted is configured to emit light from the surface on the side where the electrode 76 is disposed, as indicated by the arrow in the figure.

【0005】[0005]

【発明が解決しようとする課題】ところで、上記従来の
半導体発光素子は、リードフレーム等の被マウント部材
における2箇所に対してワイヤボンディングを施す必要
があり、その搭載作業あるいは結線作業の工程数が増加
するなどして、作業の煩雑化ならびに複雑化を余儀なく
されているのが実情であった。
By the way, in the above-mentioned conventional semiconductor light emitting device, it is necessary to perform wire bonding at two points on a mounted member such as a lead frame, and the number of steps for mounting or connecting the wires is reduced. The actual situation is that the number of operations has become complicated and complicated.

【0006】また、この種の半導体発光素子は、電極の
配設面側から光から発せられる構成であることから、図
10に示すように、発光領域A内に電極76が存在して
おり、この電極76の配設箇所は非発光部となる。した
がって、実質的発光領域は上記電極76に相当する分だ
け狭くなり、図示例のものでは、素子全体中に占める実
質的発光領域は全表面積の1/2以下になる。この結
果、上述のように高輝度特性を備えているにも拘らず、
十分な発光量を得ることができず、各種表示ボード等へ
の使用時における高い明度の要請に応じることが困難に
なるという問題を有している。
Further, since the semiconductor light emitting device of this type has a structure in which light is emitted from the side where the electrodes are disposed, as shown in FIG. 10, the electrode 76 exists in the light emitting region A, The location where the electrode 76 is provided becomes a non-light emitting portion. Therefore, the substantial light emitting region is narrowed by the amount corresponding to the electrode 76, and in the example shown in the figure, the substantial light emitting region in the entire device is ½ or less of the total surface area. As a result, despite having the high brightness characteristic as described above,
There is a problem that it is difficult to obtain a sufficient amount of light emission, and it becomes difficult to meet the demand for high brightness when used for various display boards and the like.

【0007】本願発明は、上述の事情のもとで考え出さ
れたものであって、半導体発光素子の被マウント部材に
対するワイヤボンディングの個数を削減して、その結線
作業を簡便に行えるようにするとともに、半導体発光素
子における実質的発光領域を可及的に増大させて十分な
発光量の確保および明度の向上を図ることをその課題と
する。
The present invention has been devised under the circumstances described above, and reduces the number of wire bonds to a mounted member of a semiconductor light emitting element so that the connection work can be performed easily. At the same time, it is an object to increase the substantial light emitting region of the semiconductor light emitting element as much as possible to secure a sufficient amount of light emission and improve brightness.

【0008】[0008]

【課題を解決するための手段】上記の課題を解決するた
め、本願発明では、次の技術的手段を講じている。
In order to solve the above problems, the present invention takes the following technical means.

【0009】すなわち、本願の請求項1に記載した発明
は、透明の絶縁性基板の表面上にN型半導体層、発光
層、およびP型半導体層を形成しかつ上記N型半導体層
およびP型半導体層のそれぞれの露出表面部にN側電極
およびP側電極を形成して構成される素子本体と、導電
性基板の表面に対して絶縁状態となるように形成された
補助N側電極層および導通状態となるように形成された
補助P側電極層とを有するサブマウント部材と、を備え
るとともに、上記サブマウント部材と上記素子本体との
双方の表面側を相互に対向させて配置し、かつ、上記補
助N側電極層と上記N側電極との間、および上記補助P
側電極層と上記P側電極との間がそれぞれ導通状態とな
るように、上記サブマウント部材と上記素子本体とを一
体化させたことを特徴としている。
That is, according to the invention described in claim 1 of the present application, an N-type semiconductor layer, a light emitting layer, and a P-type semiconductor layer are formed on the surface of a transparent insulating substrate, and the N-type semiconductor layer and the P-type semiconductor layer are formed. An element body formed by forming an N-side electrode and a P-side electrode on each exposed surface of the semiconductor layer, an auxiliary N-side electrode layer formed so as to be in an insulating state with respect to the surface of the conductive substrate, and A submount member having an auxiliary P-side electrode layer formed so as to be in a conductive state, and both front surface sides of the submount member and the element body are arranged to face each other, and Between the auxiliary N-side electrode layer and the N-side electrode, and the auxiliary P
The submount member and the element body are integrated so that the side electrode layer and the P-side electrode are electrically connected to each other.

【0010】また、本願の請求項2に記載した発明は、
上記サブマウント部材の補助N側電極層および補助P側
電極層の表面部分は絶縁層で覆われており、この絶縁層
には上記双方の補助電極層にそれぞれ独立して通じる各
貫通孔が穿設され、かつ上記絶縁層の表面側には各貫通
孔を介して上記双方の補助電極層にそれぞれ導通状態と
なる各付着用金属層が相互に独立して形成されていると
ともに、この各付着用金属層は、上記素子本体の双方の
電極に対して接合付着された状態となるように構成され
ていることを特徴としている。
The invention described in claim 2 of the present application is
The surface portions of the auxiliary N-side electrode layer and the auxiliary P-side electrode layer of the submount member are covered with an insulating layer, and the insulating layer is provided with through-holes that communicate with both of the auxiliary electrode layers independently. Each of the metal layers for adhesion, which are provided on the surface side of the insulating layer and are electrically connected to both of the auxiliary electrode layers through the through holes, are formed independently of each other, and The metal layer for use is characterized in that it is bonded and attached to both electrodes of the element body.

【0011】一方、本願の請求項3に記載した発明は、
上記請求項1または2に記載した半導体発光素子の製造
方法であって、上記素子本体と上記サブマウント部材と
を別々に製作した後に、上記素子本体の表面側と上記サ
ブマウント部材の表面側とを対向させた状態の下で、上
記補助N側電極層と上記N側電極、および上記補助P側
電極層と上記P側電極とをそれぞれ直接的に接着させる
ようにしたことを特徴としている。
On the other hand, the invention described in claim 3 of the present application is
The method for manufacturing a semiconductor light emitting device according to claim 1 or 2, wherein the element body and the submount member are separately manufactured, and then the surface side of the element body and the surface side of the submount member are formed. Under the condition that they are opposed to each other, the auxiliary N-side electrode layer and the N-side electrode, and the auxiliary P-side electrode layer and the P-side electrode are directly adhered to each other.

【0012】また、本願の請求項4に記載した発明は、
上記請求項3に記載した半導体発光素子の製造方法であ
って、上記素子本体を作製する第1の工程と、上記サブ
マウント部材を作製した後に、その表面部分に対して上
記絶縁層を形成し、この後、その絶縁層に上記各貫通孔
を穿設し、しかる後、その絶縁層の表面側に上記各付着
用金属層を形成する第2の工程とを別々に実行し、その
後、上記素子本体の表面側と上記サブマウント部材の表
面側とを対向させた状態の下で、上記P側電極およびN
側電極と上記各付着金属層とを直接的に接着させるよう
にしたことを特徴としている。
The invention according to claim 4 of the present application is
The method for manufacturing a semiconductor light emitting device according to claim 3, wherein the first step of manufacturing the device body and the submount member are manufactured, and then the insulating layer is formed on a surface portion thereof. After that, the through-holes are formed in the insulating layer, and then the second step of forming the adhering metal layers on the surface side of the insulating layer is separately performed. Under the condition that the surface side of the element body and the surface side of the submount member face each other, the P-side electrode and the N-side electrode
It is characterized in that the side electrode and each of the above-mentioned attached metal layers are directly adhered.

【0013】[0013]

【発明の作用および効果】上記請求項1に記載した発明
によれば、リードフレーム等のP側端子部に対して、上
記半導体発光素子のサブマウント部材をボンディングす
ることにより、素子本体のP側電極は、サブマウント部
材の補助P側電極層から導電性基板を介して上記リード
フレーム等のP側端子部に導通した状態となる。したが
って、素子本体のP側電極に対するワイヤボンディング
が不要になり、この種の半導体発光素子のマウント作業
あるいは結線作業が簡便化されるという利点が得られ
る。
According to the invention described in claim 1, by bonding the submount member of the semiconductor light emitting element to the P side terminal portion of the lead frame or the like, the P side of the element main body is bonded. The electrode is in a state of being electrically connected from the auxiliary P-side electrode layer of the submount member to the P-side terminal portion of the lead frame or the like via the conductive substrate. Therefore, there is no need for wire bonding to the P-side electrode of the element body, and there is an advantage that the mounting work or connection work of this type of semiconductor light emitting device is simplified.

【0014】さらに、上記素子本体からの発光は、両電
極の配設面とは反対側の面であるサファイア基板の裏面
からなされることになり、従来のようにP側電極が発光
を阻害することはなくなる。これにより、サファイア基
板の裏面の大半が実質的発光領域となり、十分な発光量
を確保できるとともに、この種の半導体発光素子の使用
時における高い明度の要請に応じることが可能になる。
Further, light emission from the element body is performed from the back surface of the sapphire substrate, which is the surface opposite to the surface on which both electrodes are provided, and the P-side electrode hinders light emission as in the conventional case. Things will disappear. As a result, most of the back surface of the sapphire substrate becomes a substantial light emitting region, a sufficient amount of light emission can be secured, and it is possible to meet the demand for high brightness when using this type of semiconductor light emitting device.

【0015】また、上記素子本体の発光層からサブマウ
ント部材側に発せられた光は、サブマウント部材の表面
の補助電極層等で反射することになるので、上記素子本
体におけるサファイア基板の裏面からのトータル発光量
は、上記の反射光をも含んでさらに増大し、より高い明
度を得ることが可能になる。
Further, since the light emitted from the light emitting layer of the element body to the submount member side is reflected by the auxiliary electrode layer on the surface of the submount member, etc., from the back surface of the sapphire substrate in the element body. The total amount of light emitted by is further increased including the above-mentioned reflected light, and higher brightness can be obtained.

【0016】また、上記請求項2に記載した発明によれ
ば、上記サブマウント部材の両電極の表面部分を覆って
いる絶縁層のさらに表面側に独立して形成されている各
付着用金属層を、上記素子本体の両電極に接合付着させ
るだけで、上記サブマウント部材の両補助電極を上記素
子本体の両電極に対して導通状態にできるようになる。
したがって、上記サブマウント部材と上記素子本体との
電気的接続作業が簡単に行えるとともに、その相対的位
置誤差についても厳格な制約が緩和され、位置決めある
いは位置合わせの自由度が増大する。
According to the second aspect of the invention, each metal layer for adhesion is formed independently on the surface side of the insulating layer covering the surface portions of both electrodes of the submount member. It is possible to bring both auxiliary electrodes of the submount member into conduction with both electrodes of the element body simply by bonding and attaching to both electrodes of the element body.
Therefore, the electrical connection work between the submount member and the element body can be easily performed, and the strict restriction on the relative positional error is relaxed, and the degree of freedom in positioning or alignment is increased.

【0017】一方、上記請求項3に記載した発明によれ
ば、素子本体とサブマウント部材とを別々に製作した後
に、この両者を表面側どうしを対向させて両補助電極と
両電極とを接着させることにより、上述の請求項1また
は2に記載した半導体発光素子が得られる。このような
手法によれば、上記両者を別々に製作する段階において
量産化が促進されるとともに、この種の半導体発光素子
に新たな構成要素であるサブマウント部材を付加したに
も拘らず、製作作業の複雑化が効果的に回避される。
On the other hand, according to the invention described in claim 3, after the element body and the submount member are separately manufactured, the both surfaces are opposed to each other and the auxiliary electrode and the electrode are bonded to each other. By doing so, the semiconductor light emitting device according to claim 1 or 2 can be obtained. According to such a method, mass production is promoted in the step of separately manufacturing the above-mentioned two, and the semiconductor light-emitting element of this type is manufactured in spite of addition of a sub-mount member which is a new component. Work complexity is effectively avoided.

【0018】また、上記請求項4に記載した発明におい
ても、同様にして、量産化の促進が図られるとともに、
製作作業の複雑化が回避される。
Further, in the invention described in claim 4, the mass production is promoted in the same manner as described above.
The complication of production work is avoided.

【0019】[0019]

【実施例の説明】以下、本願発明の好ましい実施例を、
図面を参照しつつ具体的に説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments of the present invention will be described below.
A specific description will be given with reference to the drawings.

【0020】図1は本願発明の第1実施例に係る半導体
発光素子の構成要素である素子本体を示す概略縦断正面
図、図2はその概略平面図、図3は上記半導体発光素子
の構成要素であるサブマウント部材を示す概略縦断正面
図、図4はその概略平面図、図5は上記半導体発光素子
の全体構成ならびにリードフレームへの取り付け状態を
示す概略縦断面図である。
FIG. 1 is a schematic vertical sectional front view showing an element body which is a constituent element of a semiconductor light emitting element according to a first embodiment of the present invention, FIG. 2 is a schematic plan view thereof, and FIG. 3 is a constituent element of the semiconductor light emitting element. 4 is a schematic vertical sectional front view showing the submount member, FIG. 4 is a schematic plan view thereof, and FIG. 5 is a schematic vertical sectional view showing the overall configuration of the semiconductor light emitting element and a mounting state to a lead frame.

【0021】図1に示すように、第1実施例に係る半導
体発光素子1の素子本体2は、基本的には、絶縁基板で
あるサファイア基板3上に、N型半導体層4と、発光層
5と、P型半導体層6とを備えて構成される積層部7を
形成したものである。詳細には、上記積層部7は、透明
または半透明のサファイア基板3の表面上に窒化ガリウ
ム(GaN)のバッファ層8を成長させ、その表面側
に、下層部分から順に、N型GaNの層41と、N型A
0.2 Ga0.8 Nの層42と、発光層としてのIn0.15
Ga0.85Nの層5と、P型Al0.2 Ga0.8 Nの層61
と、P型GaNの層62と、を形成したものである。そ
して、上記発光層5からは、青色に対応した波長(好ま
しくは470nm)の光が発せられるようになってい
る。
As shown in FIG. 1, the element body 2 of the semiconductor light emitting element 1 according to the first embodiment basically comprises an N-type semiconductor layer 4 and a light emitting layer on a sapphire substrate 3 which is an insulating substrate. 5 and a P-type semiconductor layer 6 are formed to form a laminated portion 7. Specifically, the laminated portion 7 has a buffer layer 8 of gallium nitride (GaN) grown on the surface of the transparent or semi-transparent sapphire substrate 3, and an N-type GaN layer is sequentially formed on the surface side from the lower layer portion. 41 and N type A
layer 42 of 0.2 Ga 0.8 N and In 0.15 as a light emitting layer.
Ga 0.85 N layer 5 and P-type Al 0.2 Ga 0.8 N layer 61
And a P-type GaN layer 62. The light emitting layer 5 emits light having a wavelength corresponding to blue (preferably 470 nm).

【0022】加えて、上記N型GaNの層41およびN
型Al0.2 Ga0.8 Nの層42には、Siが添加され、
P型Al0.2 Ga0.8 Nの層61およびP型GaNの層
62には、Mgが添加されているとともに、上記In
0.15Ga0.85Nの層5にはZnが添加されている。そし
て、上記In0.15Ga0.85Nの層5におけるInのGa
に対する組成比(混晶比)を増加させた場合には、この
層5から発せられる光の波長が長くなるとともに、上記
Znの添加量を増加させた場合には、上記組成比を増加
させた場合よりもさらに光の波長が長くなるという特性
を備えている。なお、上記各層の厚みは、下層側から各
層41、42、5、61、62のそれぞれの順に、たと
えば3μm、300nm、50nm、300nm、15
0nmに設定されている。
In addition, the N-type GaN layer 41 and N
Si is added to the layer 42 of the type Al 0.2 Ga 0.8 N,
Mg is added to the P-type Al 0.2 Ga 0.8 N layer 61 and the P-type GaN layer 62.
Zn is added to the layer 5 of 0.15 Ga 0.85 N. Then, the Ga of In in the layer 5 of In 0.15 Ga 0.85 N is
When the composition ratio (mixed crystal ratio) is increased, the wavelength of light emitted from the layer 5 becomes longer, and when the addition amount of Zn is increased, the composition ratio is increased. It has the characteristic that the wavelength of light becomes longer than in the case. The thickness of each layer is, for example, 3 μm, 300 nm, 50 nm, 300 nm, 15 in the order of the layers 41, 42, 5, 61, 62 from the lower layer side.
It is set to 0 nm.

【0023】上記図示例の素子本体2は、最終的に単一
のチップとして得られるたとえば平面視が一辺0.5m
mの正方形状のものであるが、実際の製造に際しては、
MOCVD法により上記図示例の構造のものを所定面積
のウエハとして一括して形成した後、ダイシングにより
上記単一のチップに分割することにより得られる。
The element body 2 of the illustrated example is finally obtained as a single chip, for example, 0.5 m on a side in plan view.
Although it is a square shape of m, in the actual manufacturing,
It is obtained by collectively forming a wafer having a predetermined area as a wafer having a predetermined area by the MOCVD method and then dividing the wafer into the single chips by dicing.

【0024】そして、上記N型半導体層4におけるGa
N層41のエッチングにより除去した露出表面部にN側
電極9が形成され、P型半導体層6におけるGaN層の
表面部にP側電極10が形成されている。なお、このN
側電極9とP側電極10とは、概略的には、図2に示す
ような平面視形状とされた上で配設されている。
Then, Ga in the N-type semiconductor layer 4 is
The N-side electrode 9 is formed on the exposed surface portion of the N layer 41 removed by etching, and the P-side electrode 10 is formed on the surface portion of the GaN layer in the P-type semiconductor layer 6. In addition, this N
The side electrode 9 and the P-side electrode 10 are roughly arranged in a plan view shape as shown in FIG.

【0025】一方、図3に示すように、この第1実施例
に係る半導体発光素子1のサブマウント部材11は、不
透明の導電性を有するシリコン基板12の表面にSiO
2 でなる絶縁酸化皮膜13を形成し、その中央部をエッ
チングで除去して補助P側電極層14を形成し、かつそ
の外周側における上記酸化皮膜13の表面部に補助N側
電極層15を形成したものである。この双方の補助電極
層14,15は、AuとSnとの合金あるいはインジウ
ム系の合金を使用して蒸着により形成したものであり、
後述するように電極とハンダ用メタルとを兼用するもの
である。
On the other hand, as shown in FIG. 3, the submount member 11 of the semiconductor light emitting device 1 according to the first embodiment has SiO 2 on the surface of an opaque conductive silicon substrate 12.
The insulating oxide film 13 of 2 is formed, the central portion thereof is removed by etching to form the auxiliary P-side electrode layer 14, and the auxiliary N-side electrode layer 15 is formed on the outer peripheral surface of the oxide film 13. It was formed. Both auxiliary electrode layers 14 and 15 are formed by vapor deposition using an alloy of Au and Sn or an indium alloy.
As will be described later, the electrode also serves as a solder metal.

【0026】そして、上記補助P側電極層14と補助N
側電極層15とは、概略的には、図4に示すような平面
視形状とされた上で配設されている。加えて、同図に示
すように、シリコン基板12の一側部には、2箇所の補
助N側電極層15に導通される帯状の補助N側電極層1
5aが、上記絶縁酸化皮膜13の表面部に形成されてい
る。
Then, the auxiliary P-side electrode layer 14 and the auxiliary N side
The side electrode layer 15 is generally arranged in a plan view shape as shown in FIG. In addition, as shown in the same figure, on one side of the silicon substrate 12, a strip-shaped auxiliary N-side electrode layer 1 that is electrically connected to the auxiliary N-side electrode layers 15 at two locations.
5a is formed on the surface of the insulating oxide film 13.

【0027】次に、上記の構成を備えた素子本体2とサ
ブマウント部材11とを接合一体化させて半導体発光素
子1を製造する方法、ならびにこれによって得られる半
導体発光素子1の構成について説明する。
Next, a method for manufacturing the semiconductor light emitting device 1 by joining and integrating the device body 2 and the submount member 11 having the above-described structure, and the structure of the semiconductor light emitting device 1 obtained thereby will be described. .

【0028】まず、上記素子本体2とサブマウント部材
11とを別々に製作した後に、この両者の表面側どうし
を対向させて配置し、素子本体2のN側電極9およびP
側電極10に対してそれぞれ、サブマウント部材11の
補助N側電極層15および補助P側電極層14をハンダ
付けする。このはんだ付け作業は、上記サブマウント部
材11の双方の補助電極層15,14がハンダ用メタル
を兼用していることから、これらの補助電極層15,1
4を適宜溶融固化させることにより行われる。
First, the element body 2 and the submount member 11 are separately manufactured, and then the surface sides of the element body 2 and the submount member 11 are opposed to each other, and the N-side electrodes 9 and P of the element body 2 are arranged.
The auxiliary N-side electrode layer 15 and the auxiliary P-side electrode layer 14 of the submount member 11 are soldered to the side electrodes 10, respectively. In this soldering work, since both auxiliary electrode layers 15 and 14 of the submount member 11 also serve as soldering metal, these auxiliary electrode layers 15 and 1 are used.
4 is melted and solidified appropriately.

【0029】この結果、図5に示すように、素子本体2
のサファイア基板3の裏面3aから矢印で示すように光
が発せられる状態になる。加えて、上記素子本体の2の
P側電極10はサブマウント部材11のシリコン基板1
2に導通状態となる一方、素子本体2のN側電極9は上
記シリコン基板12に対して絶縁状態となる。なお、図
1に示す素子本体2の積層部7の高さ寸法は、図5に示
す積層部7の高さ寸法と比較して、説明の便宜上、長尺
になっている。
As a result, as shown in FIG.
Light is emitted from the back surface 3a of the sapphire substrate 3 as indicated by an arrow. In addition, the second P-side electrode 10 of the element body is the silicon substrate 1 of the submount member 11.
2, the N-side electrode 9 of the element body 2 is insulated from the silicon substrate 12. The height dimension of the laminated portion 7 of the element body 2 shown in FIG. 1 is longer than the height dimension of the laminated portion 7 shown in FIG. 5 for convenience of description.

【0030】そして、上記のようにして得られた半導体
発光素子1をリードフレーム17上に搭載するには、同
図に示すように、リードフレーム16のP側端子部16
aの上面部に上記サブマウント部材11の下面が導通状
態になるようにボンディングされるとともに、サブマウ
ント部材11の上記帯状の補助N側電極層15aとリー
ドフレーム16のN側端子部16bとの間にワイヤボン
ディング17が施される。
To mount the semiconductor light emitting device 1 obtained as described above on the lead frame 17, as shown in FIG.
The upper surface of a is bonded so that the lower surface of the submount member 11 is conductive, and the strip-shaped auxiliary N-side electrode layer 15a of the submount member 11 and the N-side terminal portion 16b of the lead frame 16 are connected. Wire bonding 17 is applied between them.

【0031】これにより、上記素子本体2のP側電極1
0は、導電性シリコン基板12を通じてリードフレーム
16のP側端子部16aに導通状態とされ、かつ上記素
子本体2のN側電極9は、ワイヤ17を通じてリードフ
レーム16のN側端子部16bに導通状態とされる。こ
の後は、上記半導体発光素子1の外周部を樹脂封止する
ことなどによって、青色発光用のLEDランプが得られ
る。
As a result, the P-side electrode 1 of the element body 2 is
0 is electrically connected to the P-side terminal portion 16a of the lead frame 16 through the conductive silicon substrate 12, and the N-side electrode 9 of the element body 2 is electrically connected to the N-side terminal portion 16b of the lead frame 16 through the wire 17. To be in a state. After that, by sealing the outer peripheral portion of the semiconductor light emitting element 1 with a resin or the like, an LED lamp for blue light emission is obtained.

【0032】このような構成とすることにより、素子本
体2の透明サファイア基板3の裏面3aにおけるN側電
極9の形成箇所以外の領域が発光領域となり、上記裏面
3aの全面積の約75%が発光領域として利用される。
したがって、従来のように電極による発光阻害が激減さ
れ、十分な発光量および高い明度を有する発光デバイス
が得られることになる。
With such a structure, a region other than the location where the N-side electrode 9 is formed on the back surface 3a of the transparent sapphire substrate 3 of the element body 2 becomes a light emitting region, and about 75% of the total area of the back surface 3a is formed. It is used as a light emitting area.
Therefore, the light emission inhibition due to the electrodes is drastically reduced as in the conventional case, and a light emitting device having a sufficient light emission amount and high brightness can be obtained.

【0033】加えて、上記素子本体2の発光層5から下
方に向かって発せられた光は、不透明のサブマウント部
材11(補助電極層14,15)で反射された後、サフ
ァイア基板3の裏面3aから外方に向かって照射される
ことになるので、光き利用効率が向上するという利点も
得られる。
In addition, the light emitted downward from the light emitting layer 5 of the element body 2 is reflected by the opaque submount member 11 (auxiliary electrode layers 14 and 15) and then the back surface of the sapphire substrate 3. Since the light is radiated outward from 3a, there is an advantage that the light utilization efficiency is improved.

【0034】さらに、上記サブマウント部材11を使用
したことにより、P側電極10に対するワイヤボンディ
ングが不要になり、結線作業の簡便化ならびに製作容易
化が図られることになる。
Further, since the submount member 11 is used, wire bonding to the P-side electrode 10 is not required, so that the connection work can be simplified and the production can be facilitated.

【0035】次に、本願発明に係る半導体発光素子1の
第2実施例を、図6、7、8を参照しつつ説明する。な
お、以下の第2実施例の説明に際して、上述の第1実施
例と共通の構成要件については同一符号を付してその説
明を省略する。
Next, a second embodiment of the semiconductor light emitting device 1 according to the present invention will be described with reference to FIGS. In the following description of the second embodiment, constituent elements common to those of the above-described first embodiment are designated by the same reference numerals and the description thereof will be omitted.

【0036】この第2実施例に係る半導体発光素子1が
上述の第1実施例と異なる点は、図6および図7に示す
ように、素子本体2の表面全域をCVD法を用いてSi
2やSi3 4 等からなる絶縁層18で覆うととも
に、この絶縁層18にN側電極9およびP側電極10に
それぞれ通じる貫通孔19,20を穿設し、かつ上記絶
縁層18の表面部にAuとSnとの合金あるいはインジ
ウム系の合金等でなる金属層21,22を相互に独立し
て形成した点にある。この場合、上記各貫通孔19,2
0には、上記各金属層21,22が埋設されることにな
るので、上記一方の金属層21は上記N側電極9に導通
した状態になり、他方の金属層22は上記P側電極10
に導通した状態になる。
The semiconductor light emitting device 1 according to the second embodiment is different from the first embodiment described above in that, as shown in FIGS. 6 and 7, the entire surface of the device body 2 is made of Si by the CVD method.
The insulating layer 18 made of O 2 , Si 3 N 4 or the like is covered, and the insulating layer 18 is provided with through holes 19 and 20 communicating with the N-side electrode 9 and the P-side electrode 10, respectively. The point is that the metal layers 21 and 22 made of an alloy of Au and Sn or an indium alloy are independently formed on the surface portion. In this case, the through holes 19 and 2
Since the respective metal layers 21 and 22 are embedded in 0, the one metal layer 21 is brought into conduction with the N-side electrode 9 and the other metal layer 22 is connected to the P-side electrode 10.
It will be in the state of conducting to.

【0037】なお、サブマウント部材11の構成は、図
7に示す各金属層21,22の平面視における形状およ
び配設状態に対応して補助N側電極層15と補助P側電
極層14とが形成されており、その他の部分、たとえば
補助N側電極層15がSiO 2 等の絶縁性皮膜13を介
して形成されている点などについては上述の第1実施例
と同一の構成である。
The structure of the submount member 11 is as shown in FIG.
7 and the shape of each metal layer 21 and 22 in plan view
And the auxiliary N-side electrode layer 15 and the auxiliary P-side electrode according to the arrangement state.
The polar layer 14 is formed, and other portions, for example,
The auxiliary N-side electrode layer 15 is SiO 2Insulating film 13 such as
Regarding the points which are formed by
It has the same configuration as.

【0038】そして、上記素子本体2とサブマウント部
材11とは、両者の表面側どうしが対向配置された状態
で、図8に示すように各金属層21,22と各補助電極
層15,14とが接合一体化されることにより、半導体
発光素子1が得られる。また、図示の構成によっても、
上記素子本体2のP側電極10はリードフレーム16の
P側端子部16aに導電性シリコン基板12を介して導
通状態とされ、かつ上記素子本体2のN側電極9はリー
ドフレーム16のN側端子部16bにワイヤ17を介し
て導通状態とされる。
As shown in FIG. 8, the element body 2 and the submount member 11 are arranged so that their front surface sides face each other, and the metal layers 21 and 22 and the auxiliary electrode layers 15 and 14 are arranged as shown in FIG. The semiconductor light emitting device 1 is obtained by joining and integrating and. In addition, according to the illustrated configuration,
The P-side electrode 10 of the element body 2 is electrically connected to the P-side terminal portion 16a of the lead frame 16 via the conductive silicon substrate 12, and the N-side electrode 9 of the element body 2 is on the N side of the lead frame 16. The terminal portion 16b is electrically connected via the wire 17.

【0039】そして、この場合には、各金属層21,2
2と各補助電極層15,14との位置合わせが容易に行
えることから、これらの両層の接合作業(ハンダ付け作
業)、ひいては素子本体2とサブマウント部材11との
接合作業が極めて簡便に行えることになる。
In this case, the metal layers 21 and 2 are
Since the position of 2 and each auxiliary electrode layer 15 and 14 can be easily aligned, the joining work (soldering work) of these two layers, and by extension, the joining work of the element main body 2 and the submount member 11, is extremely simple. You can do it.

【0040】また、この第2実施例によっても、上記第
1実施例と同様に、十分な発光量を確保できることは言
うまでもない。
It is needless to say that the second embodiment can secure a sufficient amount of light emission as in the first embodiment.

【図面の簡単な説明】[Brief description of drawings]

【図1】本願発明の第1実施例に係る半導体発光素子の
構成要素である素子本体を示す概略縦断正面図である。
FIG. 1 is a schematic vertical sectional front view showing an element body which is a constituent element of a semiconductor light emitting element according to a first embodiment of the present invention.

【図2】上記第1実施例に係る素子本体の概略平面図で
ある。
FIG. 2 is a schematic plan view of the element body according to the first embodiment.

【図3】上記第1実施例に係る半導体発光素子の構成要
素であるサブマウント部材の概略縦断正面図である。
FIG. 3 is a schematic vertical sectional front view of a submount member which is a constituent element of the semiconductor light emitting device according to the first embodiment.

【図4】上記第1実施例に係るサブマウント部材の概略
平面図である。
FIG. 4 is a schematic plan view of a submount member according to the first embodiment.

【図5】上記第1実施例に係る半導体発光素子の全体構
成ならびにその被マウント部材への取り付け状態を示す
概略縦断側面図である。
FIG. 5 is a schematic vertical cross-sectional side view showing an overall configuration of the semiconductor light emitting device according to the first embodiment and a mounting state thereof to a mounted member.

【図6】本願発明の第2実施例に係る半導体発光素子の
構成要素である素子本体を示す概略縦断正面図である。
FIG. 6 is a schematic vertical sectional front view showing an element body which is a constituent element of a semiconductor light emitting element according to a second embodiment of the present invention.

【図7】上記第2実施例に係る素子本体の概略平面図で
ある。
FIG. 7 is a schematic plan view of an element body according to the second embodiment.

【図8】上記第2実施例に係る半導体発光素子の全体構
成ならびにその被マウント部材への取り付け状態を示す
概略縦断側面図である。
FIG. 8 is a schematic vertical cross-sectional side view showing the overall configuration of the semiconductor light emitting device according to the second embodiment and its attachment state to a mounted member.

【図9】従来の半導体発光素子の全体構成ならびにその
被マウント部材への取り付け状態を示す概略縦断側面図
である。
FIG. 9 is a schematic vertical cross-sectional side view showing an entire configuration of a conventional semiconductor light emitting element and a mounting state of the semiconductor light emitting element on a mounted member.

【図10】従来の半導体発光素子の概略平面図である。FIG. 10 is a schematic plan view of a conventional semiconductor light emitting device.

【符号の説明】[Explanation of symbols]

1 半導体発光素子 2 素子本体 3 透明絶縁性基板(サファイア基板) 4 N型半導体層 5 発光層 6 P型半導体層 9 N側電極 10 P側電極 11 サブマウント部材 12 導電性基板(シリコン基板) 14 補助P側電極層 15 補助N側電極層 1 Semiconductor Light-Emitting Element 2 Element Body 3 Transparent Insulating Substrate (Sapphire Substrate) 4 N-Type Semiconductor Layer 5 Light-Emitting Layer 6 P-Type Semiconductor Layer 9 N-Side Electrode 10 P-Side Electrode 11 Submount Member 12 Conductive Substrate (Silicon Substrate) 14 Auxiliary P-side electrode layer 15 Auxiliary N-side electrode layer

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 透明の絶縁性基板の表面上にN型半導体
層、発光層、およびP型半導体層を形成しかつ上記N型
半導体層およびP型半導体層のそれぞれの露出表面部に
N側電極およびP側電極を形成して構成される素子本体
と、 導電性基板の表面に対して絶縁状態となるように形成さ
れた補助N側電極層および導通状態となるように形成さ
れた補助P側電極層を有するサブマウント部材と、を備
えるとともに、 上記サブマウント部材と上記素子本体との双方の表面側
を相互に対向させて配置し、かつ、上記補助N側電極層
と上記N側電極との間、および上記補助P側電極層と上
記P側電極との間がそれぞれ導通状態となるように、上
記サブマウント部材と上記素子本体とを一体化させたこ
とを特徴とする、半導体発光素子。
1. An N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer are formed on the surface of a transparent insulating substrate, and the N-side is formed on each exposed surface portion of the N-type semiconductor layer and the P-type semiconductor layer. An element body formed by forming an electrode and a P-side electrode, an auxiliary N-side electrode layer formed so as to be insulated from the surface of the conductive substrate, and an auxiliary P formed so as to be in a conductive state. A submount member having a side electrode layer, and both front surface sides of the submount member and the element body are arranged to face each other, and the auxiliary N-side electrode layer and the N-side electrode are provided. And the auxiliary P-side electrode layer and the P-side electrode are electrically connected to each other so that the submount member and the element body are integrated with each other. element.
【請求項2】 上記サブマウント部材の補助N側電極層
および補助P側電極層の表面部分は絶縁層で覆われてお
り、この絶縁層には上記双方の補助電極層にそれぞれ独
立して通じる各貫通孔が穿設され、かつ上記絶縁層の表
面側には各貫通孔を介して上記双方の補助電極層にそれ
ぞれ導通状態となる各付着用金属層が相互に独立して形
成されているとともに、この各付着用金属層は、上記素
子本体の双方の電極に対して接合付着された状態となる
ように構成されている、請求項1に記載の半導体発光素
子。
2. The surface portions of the auxiliary N-side electrode layer and the auxiliary P-side electrode layer of the submount member are covered with an insulating layer, and the insulating layer communicates with both of the auxiliary electrode layers independently. Each through hole is bored, and each of the metal layers for attachment, which are in a conductive state with the both auxiliary electrode layers, are independently formed on the surface side of the insulating layer through the through hole. The semiconductor light emitting device according to claim 1, wherein each of the metal layers for adhesion is configured so as to be bonded and adhered to both electrodes of the device body.
【請求項3】 上記請求項1に記載した半導体発光素子
の製造方法であって、 上記素子本体と上記サブマウント部材とを別々に製作し
た後に、上記素子本体の表面側と上記サブマウント部材
の表面側とを対向させた状態の下で、上記補助N側電極
層と上記N側電極、および上記補助P側電極層と上記P
側電極とをそれぞれ直接的に接着させるようにしたこと
を特徴とする、半導体発光素子の製造方法。
3. The method for manufacturing a semiconductor light emitting device according to claim 1, wherein after the element body and the submount member are separately manufactured, the surface side of the element body and the submount member are manufactured. Under the condition that the surface side is opposed, the auxiliary N-side electrode layer and the N-side electrode, and the auxiliary P-side electrode layer and the P-side.
A method for manufacturing a semiconductor light emitting device, characterized in that the side electrodes are directly adhered to each other.
【請求項4】 上記請求項2に記載した半導体発光素子
の製造方法であって、 上記素子本体を作製する第1の工程と、上記サブマウン
ト部材を作製した後に、その表面部分に対して上記絶縁
層を形成し、この後、その絶縁層に上記各貫通孔を穿設
し、しかる後、その絶縁層の表面側に上記各付着用金属
層を形成する第2の工程とを別々に実行し、 その後、上記素子本体の表面側と上記サブマウント部材
の表面側とを対向させた状態の下で、上記P側電極およ
びN側電極と上記各付着金属層とを直接的に接着させる
ようにしたことを特徴とする、半導体発光素子の製造方
法。
4. The method of manufacturing a semiconductor light emitting device according to claim 2, wherein the first step of manufacturing the device body and the submount member are manufactured, and then the surface portion is subjected to the above step. A second step of forming an insulating layer, then forming the through holes in the insulating layer, and then forming the attaching metal layers on the surface side of the insulating layer is separately performed. Then, the P-side electrode and the N-side electrode are directly adhered to the respective adhering metal layers under the state where the surface side of the element body and the surface side of the submount member are opposed to each other. A method for manufacturing a semiconductor light emitting device, comprising:
JP19422494A 1994-08-11 1994-08-18 Semiconductor light emitting device and manufacturing method thereof Expired - Fee Related JP3627822B2 (en)

Priority Applications (2)

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JP19422494A JP3627822B2 (en) 1994-08-18 1994-08-18 Semiconductor light emitting device and manufacturing method thereof
US08/513,624 US5557115A (en) 1994-08-11 1995-08-10 Light emitting semiconductor device with sub-mount

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JP19422494A JP3627822B2 (en) 1994-08-18 1994-08-18 Semiconductor light emitting device and manufacturing method thereof

Related Child Applications (3)

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JP2002192699A Division JP3938337B2 (en) 2002-07-01 2002-07-01 Semiconductor light emitting device and manufacturing method thereof
JP2002192700A Division JP2003031852A (en) 2002-07-01 2002-07-01 Semiconductor light emitting device and its manufacturing method
JP2002293997A Division JP3938350B2 (en) 2002-10-07 2002-10-07 Mounting method of semiconductor light emitting device

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JPH0864872A true JPH0864872A (en) 1996-03-08
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