JP2000174348A - Semiconductor light-emitting device - Google Patents

Semiconductor light-emitting device

Info

Publication number
JP2000174348A
JP2000174348A JP35007798A JP35007798A JP2000174348A JP 2000174348 A JP2000174348 A JP 2000174348A JP 35007798 A JP35007798 A JP 35007798A JP 35007798 A JP35007798 A JP 35007798A JP 2000174348 A JP2000174348 A JP 2000174348A
Authority
JP
Japan
Prior art keywords
electrode
light emitting
emitting element
submount
light
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP35007798A
Other languages
Japanese (ja)
Inventor
Yuji Kobayashi
祐二 小林
Makoto Nozoe
誠 野添
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP35007798A priority Critical patent/JP2000174348A/en
Publication of JP2000174348A publication Critical patent/JP2000174348A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor light-emitting device wherein a light- emitting element can be stably mounted on a submount without inclination, and excellent light emission luminance and high reliability can be maintained. SOLUTION: This light-emitting device is provided with a light-emitting element 1, wherein a P electrode 4 and N electrodes 3a, 3b are formed on the surface of compound semiconductor laminated on an insulating and light transmitting substrate 1a, and a submount 2 electrically continuously mounting the light-emitting element 1 in the attitude that the substrate 1a faces toward the light-emitting direction and the compound semiconductor surface faces toward the mounting surface side. The total number of the P electrode 4 and the N electrodes 3a, 3b is made at least three. A base bottom of a polygon surrounded by segments connecting the electrodes is formed, and the light- emitting element 1 is mounted stably on the submount 2.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、たとえば発光ダイ
オードやレーザダイオード等の光デバイスに利用される
半導体発光装置に係り、特に発光素子をその電極形成面
を下向きにしてサブマウントの上に実装する半導体発光
装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light-emitting device used for an optical device such as a light-emitting diode or a laser diode, and more particularly, to mounting a light-emitting element on a submount with its electrode forming surface facing down. The present invention relates to a semiconductor light emitting device.

【0002】[0002]

【従来の技術】化合物半導体を基板に積層した半導体発
光素子はその高輝度化が急速に進み、特にGaN系化合
物半導体を利用した青色及び緑色の発光ダイオードや青
紫色レーザダイオード等の分野での展開が顕著である。
2. Description of the Related Art Semiconductor light-emitting devices in which compound semiconductors are stacked on a substrate are rapidly increasing in luminance, and are particularly developed in fields such as blue and green light-emitting diodes and blue-violet laser diodes using GaN-based compound semiconductors. Is remarkable.

【0003】GaN系化合物半導体を利用する青色発光
の青色ダイオードの製造では、化合物半導体薄膜層を成
長させるための基板として、光透過性であって絶縁性の
サファイアが現在のところ最も好適な材料として一般に
利用されている。このサファイアを基板として用いる場
合では、その絶縁性のために基板側から電極を取り出せ
ない。したがって、GaN系化合物半導体以外のたとえ
ばGaAsやGaP等の化合物半導体を利用する発光素
子とは異なって、積層した化合物半導体層の表面側にp
とnの電極が形成されることになる。たとえば、サファ
イアの基板にGaNのn型層を積層してその上にGaN
のp型層を積層形成し、両層の境界のp−n接合域の活
性層より深くp型層をエッチングによって除去し、これ
によって露出したn型層の表面にn側電極を及びp型層
の表面にp側電極をそれぞれ金属蒸着法によって形成す
るというのが一つの製造方法として確立されている。
[0003] In the manufacture of a blue light-emitting blue diode using a GaN-based compound semiconductor, a light-transmissive and insulating sapphire is currently the most suitable material as a substrate for growing a compound semiconductor thin film layer. It is commonly used. When this sapphire is used as a substrate, the electrode cannot be taken out from the substrate side due to its insulating property. Therefore, unlike a light emitting element using a compound semiconductor such as GaAs or GaP other than a GaN-based compound semiconductor, p
And n electrodes are formed. For example, an n-type layer of GaN is laminated on a sapphire substrate, and GaN is
Of the p-type layer, and the p-type layer is removed by etching deeper than the active layer in the pn junction region at the boundary between the two layers, whereby an n-side electrode and a p-type electrode are formed on the exposed surface of the n-type layer. It has been established as one manufacturing method that a p-side electrode is formed on the surface of each layer by a metal vapor deposition method.

【0004】このような絶縁性のサファイアを基板とす
る発光素子でも、GaAsやGaP等の化合物半導体発
光素子と同様にリードフレームの搭載面に基板を載せて
実装することができる。すなわち、化合物半導体層の表
面すなわちp側及びn側の電極を形成した側を発光面と
して基板を搭載面にマウントし、導通を取るために発光
面側のp側及びn側の電極をワイヤによってボンディン
グすればよい。
A light emitting device using such an insulating sapphire substrate can be mounted on a lead frame mounting surface, similarly to a compound semiconductor light emitting device such as GaAs or GaP. In other words, the surface of the compound semiconductor layer, that is, the side on which the p-side and n-side electrodes are formed is used as a light-emitting surface, and the substrate is mounted on the mounting surface. What is necessary is just to bond.

【0005】ところが、ワイヤボンディングによって導
通させる場合、断線の防止や電極及びリード側とのボン
ディング強度を維持するため、ワイヤにはある程度のル
ープを張らせる必要がある。このため、ループの嵩の分
に相当して嵩が大きくなり最終的に樹脂封止してパッケ
ージ化される製品の薄型化に影響する。
However, when conducting by wire bonding, it is necessary to form a certain amount of loop on the wire in order to prevent disconnection and maintain the bonding strength between the electrode and the lead. For this reason, the bulk becomes large corresponding to the bulk of the loop, which ultimately affects the thickness reduction of a product to be packaged by resin sealing.

【0006】これに対し、電極を基板側に持たせること
ができないGaN系化合物半導体とサファイア基板とに
よる発光素子において、サブマウントを有効に利用する
ことで、発光輝度の低下がなく薄型化も可能なアセンブ
リも既に提案されている。これは、ウエハー状態にある
発光素子のパターンに電極パターンを形成したものをダ
イシングしてチップ化し、このチップをサブマウントの
ウエハーに実装搭載した後にダイシングすることによっ
てサブマウントと発光素子との複合素子とするというも
のである。
On the other hand, in a light emitting device using a GaN-based compound semiconductor and a sapphire substrate, in which electrodes cannot be provided on the substrate side, by using a submount effectively, a reduction in light emission luminance and a reduction in thickness can be achieved. Various assemblies have already been proposed. This is a composite element of a sub-mount and a light-emitting element by dicing a chip formed by forming an electrode pattern on a pattern of a light-emitting element in a wafer state, mounting the chip on a sub-mount wafer, and then dicing. It is said that.

【0007】このように複合素子化すれば、ワイヤボン
ディングを含まないので特に厚さ方向を小型化できるほ
か、サブマウントをたとえば静電気保護用の素子として
多機能化したり、発光面側を向いた基板の表面からの発
光に加えてサブマウント側に臨んでいる電極を反射面と
して活性層からの光を発光面側に反射させて輝度を上げ
ることもできる。
[0007] If a composite element is formed in this manner, the thickness can be reduced particularly in the thickness direction because wire bonding is not included. In addition, the submount can be multifunctional as an element for protecting static electricity, or a substrate facing the light emitting surface side. In addition to the light emission from the surface, the electrode facing the submount can be used as a reflection surface to reflect light from the active layer to the light emission surface side to increase the brightness.

【0008】以上のことから、サブマウントとともに発
光素子を複合化したアセンブリであれば、チップの小型
化から発光効率の向上までが改善される。したがって、
現在のところ主流となっている基板側を搭載面にマウン
トするいわゆるフェイスアップ式の実装と比較しても、
その機能や発光性能は同等のものが得られる。
As described above, in the case of an assembly in which a light emitting element is combined with a submount, improvement in chip size and improvement in luminous efficiency can be improved. Therefore,
Compared to the so-called face-up type mounting where the board side, which is currently the mainstream, is mounted on the mounting surface,
The same function and light emission performance can be obtained.

【0009】[0009]

【発明が解決しようとする課題】しかしながら、サブマ
ウントとの複合素子とする場合では、半導体層の表面に
はp側とn側の2個の電極しか形成されていないので、
発光素子の搭載安定性に問題がある。すなわち、サブマ
ウント側の電極との間をバンプ電極によって導通させる
にしても、サブマウントに対して発光素子は2点支持さ
れるだけであり、搭載後の安定性や接合強度に乏しい。
However, in the case of a composite device with a submount, only two electrodes, p-side and n-side, are formed on the surface of the semiconductor layer.
There is a problem in mounting stability of the light emitting element. In other words, even if the electrodes are electrically connected to the electrodes on the submount by the bump electrodes, the light emitting elements are only supported at two points with respect to the submount, and the stability and the bonding strength after mounting are poor.

【0010】このようにサブマウントに対する発光素子
の搭載安定性が不良であると、発光素子がサブマウント
上で傾いてしまう恐れがある。このような発光素子の傾
きが発生すると、発光方向の指向性が不良となり、大幅
な輝度低下が避けられない。また、発光素子の傾きが大
きいと、たとえば発光素子側の半導体層とサブマウント
側の電極とが直に接触して短絡することにもなり、製品
の信頼性に大きく影響する。
If the mounting stability of the light emitting element with respect to the submount is poor, the light emitting element may be inclined on the submount. When such inclination of the light emitting element occurs, the directivity in the light emitting direction becomes poor, and a significant decrease in luminance is inevitable. Further, if the inclination of the light emitting element is large, for example, the semiconductor layer on the light emitting element side and the electrode on the submount side are in direct contact and short-circuited, which greatly affects the reliability of the product.

【0011】このようにサブマウントを用いて発光素子
とともに複合素子化するとワイヤボンディングしない分
だけ嵩を小さくできるものの、サブマウントへの発光素
子の搭載安定性が十分とはいえないため、製品の信頼性
の低下を招きやすい。
As described above, when a composite device is formed together with the light emitting device using the submount, the bulk can be reduced by the amount of wire bonding, but the mounting stability of the light emitting device on the submount is not sufficient. It is easy to cause the deterioration of the property.

【0012】本発明において解決すべき課題は、発光素
子が傾いたりせずにサブマウントに安定搭載でき良好な
発光輝度及び高い信頼性が維持できる半導体発光装置を
提供することにある。
An object of the present invention is to provide a semiconductor light emitting device which can be stably mounted on a submount without tilting a light emitting element and can maintain good light emission luminance and high reliability.

【0013】[0013]

【課題を解決するための手段】本発明の半導体発光装置
は、絶縁性であって光透過性の基板に積層した化合物半
導体の表面にp電極及びn電極をそれぞれ形成した発光
素子と、前記発光素子を、前記基板が発光方向を向き且
つ前記化合物半導体の表面側が搭載面側を向く姿勢とし
て導通搭載するサブマウントとを備え、前記発光素子の
p電極及びn電極の総数を少なくとも3個以上とし、こ
れらのp電極及びn電極を結ぶ線分によって包囲される
多角形の基底を形成可能としてなることを特徴とする。
According to the present invention, there is provided a semiconductor light emitting device comprising: a light emitting element having a compound semiconductor laminated on an insulating and light transmissive substrate; A submount for conducting and mounting the device in such a manner that the substrate faces the light emitting direction and the surface side of the compound semiconductor faces the mounting surface side, and the total number of the p electrode and the n electrode of the light emitting device is at least three or more. And a polygonal base surrounded by a line segment connecting the p-electrode and the n-electrode.

【0014】[0014]

【発明の実施の形態】請求項1に記載の発明は、絶縁性
であって光透過性の基板に積層した化合物半導体の表面
にp電極及びn電極をそれぞれ形成した発光素子と、前
記発光素子を、前記基板が発光方向を向き且つ前記化合
物半導体の表面側が搭載面側を向く姿勢として導通搭載
するサブマウントとを備え、前記発光素子のp電極及び
n電極の総数を少なくとも3個以上とし、これらのp電
極及びn電極を結ぶ線分によって包囲される多角形の基
底を形成可能としてなる半導体発光装置であり、サブマ
ウントの上に3点以上の支持点で発光素子を搭載するの
で搭載安定性が向上するとともに、三角形以上の形状の
基底を持つように発光素子を搭載することでその接合強
度を向上させるという作用を有する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 is a light emitting device in which a p-electrode and an n-electrode are respectively formed on a surface of a compound semiconductor laminated on an insulating and light-transmitting substrate, and the light-emitting device. A submount that conducts and mounts the substrate such that the substrate faces the light emitting direction and the surface side of the compound semiconductor faces the mounting surface side, and the total number of the p electrode and the n electrode of the light emitting element is at least three or more, A semiconductor light-emitting device capable of forming a polygonal base surrounded by a line segment connecting these p-electrodes and n-electrodes. Since the light-emitting elements are mounted on three or more support points on the submount, the mounting is stable. This has the effect of improving the bonding property and improving the bonding strength by mounting the light emitting element so as to have a base having a shape of a triangle or more.

【0015】請求項2に記載の発明は、前記サブマウン
トは、前記発光素子のp電極及びn電極を正極性または
逆極性で導通させる電極パターンを表面に形成し、前記
発光素子の少なくとも3個以上のp電極及びn電極の配
列パターンと、前記サブマウントの前記電極パターンと
の間に、前記サブマウントに対する前記発光素子の搭載
位置に自由度を与える関係を持たせてなる請求項1記載
の半導体発光装置であり、サブマウントの上に発光素子
を搭載するときに発光素子の搭載位置が設定位置から多
少ずれた場合でもアセンブリできるという作用を有す
る。
According to a second aspect of the present invention, in the submount, an electrode pattern for conducting the p-electrode and the n-electrode of the light emitting element with a positive polarity or a reverse polarity is formed on the surface, and at least three of the light emitting elements are formed. 2. The arrangement according to claim 1, wherein a relationship is provided between the arrangement pattern of the p-electrodes and the n-electrodes and the electrode pattern of the sub-mount to give a degree of freedom in a mounting position of the light-emitting element with respect to the sub-mount. This is a semiconductor light emitting device, and has an effect that when a light emitting element is mounted on a submount, assembly can be performed even when a mounting position of the light emitting element is slightly shifted from a set position.

【0016】請求項3に記載の発明は、前記発光素子の
p電極及びn電極と、前記サブマウントの電極パターン
とを、前記発光素子側またはサブマウント側のいずれか
一方に形成したバンプ電極によって導通接続してなる請
求項2記載の半導体発光装置であり、バンプ電極を超音
波振動の負荷によって接合するときバンプ電極にほぼ均
等に荷重を加えながら偏り負荷を伴うことのない実装が
得られるという作用を有する。
According to a third aspect of the present invention, the p-electrode and the n-electrode of the light-emitting element and the electrode pattern of the submount are formed by bump electrodes formed on either the light-emitting element side or the submount side. 3. The semiconductor light emitting device according to claim 2, wherein the semiconductor light emitting device is connected in a conductive manner, and when the bump electrodes are joined by a load of ultrasonic vibration, the bump electrodes can be mounted almost uniformly and without a bias load. Has an action.

【0017】図1は本発明の一実施の形態による半導体
発光装置の概略平面図、図2は発光素子の底面図、図3
の(a)及び(b)はそれぞれ図1のA−A線及びB−
B線矢視による縦断面図である。
FIG. 1 is a schematic plan view of a semiconductor light emitting device according to an embodiment of the present invention, FIG. 2 is a bottom view of a light emitting element, and FIG.
(A) and (b) of FIG.
It is a longitudinal cross-sectional view by the arrow B.

【0018】図1〜図4において、半導体発光装置は、
GaN系化合物半導体を利用した青色発光の発光素子1
とこれを搭載支持するサブマウント2とから構成された
ものである。
In FIGS. 1 to 4, the semiconductor light emitting device comprises:
Light-emitting element 1 emitting blue light using GaN-based compound semiconductor
And a submount 2 for mounting and supporting the same.

【0019】発光素子1は従来例でも説明したように、
光透過性であって絶縁性のサファイアを利用した基板1
aと、その表面に成長させたGaNのn型層1b及びG
aNのp型層1cとの積層体であり、その平面形状はほ
ぼ正方形である。そして、図2において左辺の上下両端
の角には、エッチングによってp型層1cを部分的に除
去してn型層1bを露出させ、この露出した2箇所のn
型層1bの表面にそれぞれ第1n電極3aと第2n電極
3bをそれぞれ形成している。また、右辺側のほぼ中央
にはp型層1cの表面にp電極4を設けている。これら
の第1,第2n電極3a,3b及びp電極4はたとえば
Auを素材として金属蒸着法によって形成されたもので
ある。
As described in the conventional example, the light emitting element 1
Substrate 1 using light-transmissive and insulating sapphire
a and n-type layers 1b and G of GaN grown on the surface thereof
It is a laminate with the aN p-type layer 1c and has a substantially square planar shape. Then, in FIG. 2, the p-type layer 1c is partially removed by etching to expose the n-type layer 1b at the upper and lower corners on the left side.
A first n-electrode 3a and a second n-electrode 3b are respectively formed on the surface of the mold layer 1b. Further, a p-electrode 4 is provided on the surface of the p-type layer 1c substantially at the center on the right side. The first and second n-electrodes 3a and 3b and the p-electrode 4 are formed, for example, using Au as a material by a metal vapor deposition method.

【0020】サブマウント2は、たとえば鉄または銅等
の金属を利用した基材2aとその表面に積層した絶縁膜
2bとを備え、更にこの絶縁膜2bの表面に電極パター
ンを形成したものである。サブマウント2は長方形の平
面形状を持ち、その大きさは長辺が発光素子1の1辺の
長さの1.5〜1.8倍程度であり、短辺は発光素子1
よりも少し長い。そして、絶縁膜2bの表面の電極パタ
ーンは、絶縁膜2bの表面にAl等の金属膜層を積層し
たものをU字状にエッチング処理して形成されたもの
で、p側電極5とn側電極6とから構成されている。
The submount 2 has a base material 2a made of a metal such as iron or copper and an insulating film 2b laminated on the surface thereof, and further has an electrode pattern formed on the surface of the insulating film 2b. . The submount 2 has a rectangular planar shape, and the size of the long side is about 1.5 to 1.8 times the length of one side of the light emitting element 1 and the short side is the light emitting element 1
A little longer than. The electrode pattern on the surface of the insulating film 2b is formed by laminating a metal film layer of Al or the like on the surface of the insulating film 2b and etching the U-shaped electrode. And an electrode 6.

【0021】p側電極5は、図1に示すように、サブマ
ウント2の右辺の中央から左側に直線状に延びる範囲に
形成され、右端の上面にはワイヤボンディングのための
ボンディングパッド5aを積層している。また、n側電
極6は、p側電極5の周りの全体に展開してほぼU字状
の領域を占め、上半分の領域の右端にワイヤボンディン
グ用のボンディングパッド6aを形成している。
As shown in FIG. 1, the p-side electrode 5 is formed in a range extending linearly from the center of the right side of the submount 2 to the left, and a bonding pad 5a for wire bonding is laminated on the upper surface at the right end. are doing. The n-side electrode 6 extends around the p-side electrode 5 and occupies a substantially U-shaped region. A bonding pad 6a for wire bonding is formed at the right end of the upper half region.

【0022】発光素子1及びサブマウント2との複合体
から構成される半導体発光装置の製造において、発光素
子1は従来と同様にサファイアを基材とするウエハー上
にGaNの化合物半導体の薄膜層を形成して基板1aと
n型及びp型層1b,1cを得た後、第1,第2n電極
3a,3bとp電極4を金属蒸着法によって形成する。
そして、これらの電極3a,3b,4のそれぞれにバン
プ電極7a,7b,7cをメッキまたはスタッドバンプ
によって形成した後、ウエハーをダイシングすることに
よってチップ化することで、図示の発光素子1の単体を
得る。一方、サブマウント2は基材2aの表面に絶縁膜
2bを形成したものをシート材として準備しておき、金
属膜を積層した後にエッチングすることによって、p側
及びn側の電極5,6を形成する。
In the manufacture of a semiconductor light emitting device composed of a composite of the light emitting element 1 and the submount 2, the light emitting element 1 is formed by forming a thin film layer of a GaN compound semiconductor on a sapphire-based wafer as in the prior art. After forming the substrate 1a and the n-type and p-type layers 1b and 1c, the first and second n-electrodes 3a and 3b and the p-electrode 4 are formed by a metal deposition method.
Then, after bump electrodes 7a, 7b, 7c are formed on each of these electrodes 3a, 3b, 4 by plating or stud bumps, the wafer is diced into chips to form a single light emitting element 1 shown in the figure. obtain. On the other hand, the submount 2 prepares a sheet material in which an insulating film 2b is formed on the surface of a base material 2a, and after laminating a metal film, etches the p-side and n-side electrodes 5, 6 to form a sheet. Form.

【0023】これらの発光素子1のチップ単体及び表面
にp側及びn側の電極5,6を形成したサブマウントの
素材となるシート材について、シート材を実装テーブル
に搭載し、発光素子1をシート材のp側及びn側の電極
5,6のパターンに合わせて実装する。この実装工程で
は、図1から明らかなように、第1,第2n電極3a,
3bがシート材のn側電極6の上に、及びp電極4がp
側電極5にそれぞれ対応するように位置決めする。この
とき、発光素子1側の各電極3a,3b,4のそれぞれ
のバンプ電極7a,7b,7cが接合されるように、超
音波振動を加えてシート材側のp側及びn側の電極5,
6に溶着する。そして、シート材をダイシングすること
で、図1及び図3に示す発光素子1とサブマウント2と
の複合体による半導体発光装置が得られる。
With respect to a single chip of the light emitting element 1 and a sheet material serving as a submount material in which p-side and n-side electrodes 5 and 6 are formed on the surface, the sheet material is mounted on a mounting table, and the light emitting element 1 is mounted. It is mounted according to the patterns of the p-side and n-side electrodes 5 and 6 of the sheet material. In this mounting process, as is clear from FIG. 1, the first and second n-electrodes 3a,
3b is on the n-side electrode 6 of the sheet material, and
Positioning is performed so as to correspond to each of the side electrodes 5. At this time, ultrasonic vibration is applied so that the bump electrodes 7a, 7b, 7c of the respective electrodes 3a, 3b, 4 of the light emitting element 1 are joined, and the p-side and n-side electrodes 5 of the sheet material side are applied. ,
Weld to 6. Then, by dicing the sheet material, a semiconductor light emitting device using a composite of the light emitting element 1 and the submount 2 shown in FIGS. 1 and 3 can be obtained.

【0024】なお、サブマウント2のシート材への実装
の前に発光素子1を単体チップにダイシングするのに代
えて、複数の発光素子1を含むパターン形状にダイシン
グしておき、シート材に実装した後に発光素子1が1個
ずつ含まれるようにシート材をダイシングしても同様の
半導体発光装置が得られる。
Note that, before mounting the submount 2 on the sheet material, instead of dicing the light emitting element 1 into a single chip, the light emitting element 1 is diced into a pattern shape including a plurality of light emitting elements 1 and mounted on the sheet material. After that, a similar semiconductor light emitting device can be obtained by dicing the sheet material so that the light emitting elements 1 are included one by one.

【0025】製造された半導体発光素子は、リードフレ
ームやプリント配線基板(いずれも図示せず)に搭載実
装された後、図1及び図3に示すように、サブマウント
2のp側及びn側の電極5,6のボンディングパッド5
a,6aにそれぞれワイヤ8a,8bをボンディング
し、リードフレームまたはプリント配線基板側の回路に
導通させる。
After the manufactured semiconductor light emitting device is mounted on a lead frame or a printed wiring board (both not shown), as shown in FIGS. 1 and 3, the p-side and n-side of the submount 2 are mounted. Bonding pads 5 for electrodes 5 and 6
The wires 8a and 8b are bonded to the wires a and 6a, respectively, so that the wires 8a and 8b are electrically connected to a circuit on a lead frame or a printed wiring board.

【0026】以上の構成において、発光素子1は第1,
第2n電極3a,3bとp電極4の3個の電極によって
サブマウント2側に搭載され、3点支持によって保持さ
れる。そして、これらの電極3a,3b,4は図2に示
すように発光素子1の外郭縁に近い位置に形成されてい
て電極3a,3b,4及びバンプ電極7a,7b,7c
が造る三角形によって形成される基底の大きさは、発光
素子1の全体のほぼ半分程度を占める。したがって、サ
ブマウント2の上に発光素子1は安定固定され、姿勢が
傾くことのない実装が可能となる。また、従来の2個の
電極による接合に比べると、3点支持によって接合強度
も大きくなるので安定した支持構造が維持され、製品の
信頼度も大幅に向上する。
In the above configuration, the light-emitting element 1 has the first
It is mounted on the submount 2 side by three electrodes of the second n-electrodes 3a and 3b and the p-electrode 4, and is held by three-point support. These electrodes 3a, 3b, 4 are formed at positions near the outer edge of the light emitting element 1 as shown in FIG. 2, and the electrodes 3a, 3b, 4 and the bump electrodes 7a, 7b, 7c are formed.
The size of the base formed by the triangle formed by the light-emitting element 1 occupies approximately half of the entire light-emitting element 1. Therefore, the light emitting element 1 is stably fixed on the submount 2, and mounting without inclination of the posture becomes possible. Further, as compared with the conventional connection using two electrodes, the bonding strength is increased by the three-point support, so that a stable support structure is maintained and the reliability of the product is greatly improved.

【0027】また、図1から明らかなように、サブマウ
ント2のp側電極5もn側電極6もこれらに対応するp
電極4及び第1,第2n電極3a,3bが左右方向に位
置ずれしても導通搭載が可能である。すなわち、図1の
状態では、第1,第2n電極3a,3bがn側電極6の
左端部分に位置しているが、もしサブマウント2に対す
る発光素子1の実装位置が右側にずれても、これらの第
1,第2n電極3a,3bのバンプ電極7a,7bはn
側電極6の上に載ったままである。そして、p電極4の
バンプ電極7cもp側電極5が右側へ向けて延びている
ので、同様にp側電極5への導通搭載が保たれる。した
がって、図1において、たとえば発光素子1のサブマウ
ント2への実装位置をその左右方向の中央位置に設定し
ておけば、実装時に発光素子1が左または右に位置ずれ
しても、導通のとれた実装が可能である。このため、図
1において、上下方向についてだけ発光素子1の実装の
位置決め精度を厳しく管理すればよく、実装のハンドリ
ングのための制御も簡単になり、製品の信頼性も向上す
る。
As is apparent from FIG. 1, both the p-side electrode 5 and the n-side electrode 6 of the submount 2
Even if the electrode 4 and the first and second n-electrodes 3a, 3b are displaced in the left-right direction, the conductive mounting is possible. That is, in the state of FIG. 1, the first and second n-electrodes 3a and 3b are located at the left end of the n-side electrode 6, but if the mounting position of the light emitting element 1 with respect to the submount 2 is shifted to the right, The bump electrodes 7a, 7b of these first and second n-electrodes 3a, 3b are n
It remains on the side electrode 6. Since the p-side electrode 5 of the bump electrode 7c of the p-side electrode 4 extends rightward, the conductive mounting on the p-side electrode 5 is similarly maintained. Therefore, in FIG. 1, for example, if the mounting position of the light emitting element 1 on the submount 2 is set at the center position in the left-right direction, even if the light emitting element 1 is displaced to the left or right during mounting, the conduction is maintained. A good implementation is possible. For this reason, in FIG. 1, the positioning accuracy of the mounting of the light emitting element 1 only needs to be strictly controlled in the vertical direction, the control for the mounting handling is simplified, and the reliability of the product is improved.

【0028】図4は発光素子1とサブマウント2に設け
る電極のパターンの別の例を示す概略であって、発光素
子1の底面形状の中にサブマウント2に設ける電極も含
めて示す。
FIG. 4 is a schematic diagram showing another example of the pattern of the electrodes provided on the light emitting element 1 and the submount 2, and shows the shape of the bottom surface of the light emitting element 1 including the electrodes provided on the submount 2.

【0029】図4の(a)は、発光素子1の底面には先
の例で示した第1,第2n電極3a,3bに加えて第3
n電極3c及び第4n電極3dを角部に設けるととも
に、p電極4を中央に配置したものである。すなわち、
第1,第3n電極3a,3cが図1においてサブマウン
ト2のn側電極6の上半分の領域に、及び第2,第4n
の電極3b,3dが下半分の領域に対応し、p電極4は
サブマウント2のp側電極5に含まれている。この例で
は、電極の数が5個となるので発光素子1のサブマウン
ト2に対する搭載安定性が更に向上するとともに、先の
例と同様にサブマウント2への発光素子1の実装位置決
めの自由度も持たせることができる。
FIG. 4A shows that the light emitting element 1 has a third bottom surface in addition to the first and second n-electrodes 3a and 3b shown in the previous example.
The n-electrode 3c and the fourth n-electrode 3d are provided at corners, and the p-electrode 4 is arranged at the center. That is,
The first and third n-electrodes 3a and 3c are located in the upper half region of the n-side electrode 6 of the submount 2 in FIG.
The electrodes 3b and 3d correspond to the lower half region, and the p-electrode 4 is included in the p-side electrode 5 of the submount 2. In this example, since the number of electrodes is five, the mounting stability of the light emitting element 1 on the submount 2 is further improved, and the degree of freedom in positioning the mounting of the light emitting element 1 on the submount 2 as in the previous example. Can also have.

【0030】図4の(b)は同図4の(a)の例におけ
る第4n電極3dがなく、発光素子1の右端側を2点支
持するためp電極4は図2の例と同様の配置としたもの
である。この例では、4個の電極による発光素子1の支
持となり、同図(a)の場合よりも支持点が1個少ない
が、第1,第2n電極3a,3bと第3n電極3c及び
p電極4が造る台形による基底を広くとれるので、サブ
マウント2への安定搭載が同様に可能である。
FIG. 4B does not include the fourth n-electrode 3d in the example of FIG. 4A and supports two points on the right end of the light emitting element 1, so that the p-electrode 4 is the same as the example of FIG. It is an arrangement. In this example, the light-emitting element 1 is supported by four electrodes, and the number of support points is smaller by one than in the case of FIG. 3A, but the first and second n-electrodes 3a and 3b, the third n-electrode 3c, and the p-electrode Since the base of the trapezoid formed by 4 can be widened, stable mounting on the submount 2 is also possible.

【0031】図4の(c)は第1,第2n電極3a,3
bは同図(a)及び(b)のパターンと同様であるが、
p電極4はエッチング面を除くp型層1cの全面に形成
されている。この例では、第1,第2n電極3a,3b
には図3の例と同様にバンプ電極7a,7bを形成して
サブマウント2側のn側電極6に接合するが、p電極4
は全面電極となっているので、サブマウント2側のp側
電極5にバンプ電極(図示せず)を形成することが好ま
しい。そして、サブマウント2への発光素子1の実装で
は、p電極4の領域が広いのでサブマウント2のp側電
極5のバンプ電極の接合の自由度が拡大し、実装のハン
ドリングがより一層簡単になる。
FIG. 4C shows the first and second n-electrodes 3a, 3a.
b is the same as the pattern shown in FIGS.
The p-electrode 4 is formed on the entire surface of the p-type layer 1c except for the etching surface. In this example, the first and second n-electrodes 3a, 3b
3, the bump electrodes 7a and 7b are formed and joined to the n-side electrode 6 on the submount 2 side.
Is a whole surface electrode, it is preferable to form a bump electrode (not shown) on the p-side electrode 5 on the submount 2 side. When the light emitting element 1 is mounted on the submount 2, the area of the p-electrode 4 is wide, so that the degree of freedom in joining the bump electrode of the p-side electrode 5 of the submount 2 is increased, and the handling of mounting is further simplified. Become.

【0032】[0032]

【発明の効果】本発明では、発光素子が3個以上の電極
を備え、しかもこれらの電極がたとえば発光素子の半分
以上の面積割合となる基底を持つようにすることで、サ
ブマウントに対して安定搭載でき、発光素子のサブマウ
ントへの実装のときに発光素子が傾いたり電極どうしの
短絡がなく、発光輝度が高く信頼度も高い製品が得られ
る。また、発光素子の電極とサブマウント側の電極パタ
ーンとを発光素子の搭載位置の自由度を持つような関係
とすることによって、発光素子のサブマウントへの実装
のハンドリングが容易になり、製造歩留りも向上する。
According to the present invention, the light emitting element has three or more electrodes, and these electrodes have a base having an area ratio of, for example, half or more of the light emitting element, so that The product can be mounted stably, and when the light emitting element is mounted on the submount, there is no inclination of the light emitting element or short circuit between electrodes, and a product having high emission luminance and high reliability can be obtained. Also, by setting the electrode of the light emitting element and the electrode pattern on the submount side to have a degree of freedom of the mounting position of the light emitting element, the handling of mounting the light emitting element on the submount is facilitated, and the manufacturing yield is increased. Also improve.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施の形態における半導体発光装置
の平面図
FIG. 1 is a plan view of a semiconductor light emitting device according to an embodiment of the present invention.

【図2】図1の半導体発光装置の発光素子の底面図FIG. 2 is a bottom view of a light emitting element of the semiconductor light emitting device of FIG. 1;

【図3】図1の半導体発光装置の発光素子とサブマウン
トの導通構造を示す図であって、(a)は図1のA−A
線矢視による縦断面図 (b)は図1のB−B線矢視による縦断面図
3A and 3B are diagrams showing a conduction structure between a light emitting element and a submount of the semiconductor light emitting device of FIG. 1, wherein FIG.
FIG. 1B is a longitudinal sectional view taken along line BB of FIG. 1.

【図4】発光素子の底面に設けるp電極及びn電極の配
置パターンの例を示す概略図
FIG. 4 is a schematic view showing an example of an arrangement pattern of a p-electrode and an n-electrode provided on the bottom surface of a light-emitting element.

【符号の説明】[Explanation of symbols]

1 発光素子 1a 基板 1b n型層 1c p型層 2 サブマウント 2a 基材 2b 絶縁膜 3a 第1n電極 3b 第2n電極 3c 第3n電極 3d 第4n電極 4 p電極 5 p側電極 5a ボンディングパッド 6 n側電極 6a ボンディングパッド 7a,7b,7c バンプ電極 8a,8b ワイヤ Reference Signs List 1 light emitting element 1a substrate 1b n-type layer 1c p-type layer 2 submount 2a base material 2b insulating film 3a first n-electrode 3b second n-electrode 3c third n-electrode 3d fourth n-electrode 4 p-electrode 5 p-side electrode 5a bonding pad 6n Side electrode 6a Bonding pad 7a, 7b, 7c Bump electrode 8a, 8b Wire

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性であって光透過性の基板に積層し
た化合物半導体の表面にp電極及びn電極をそれぞれ形
成した発光素子と、前記発光素子を、前記基板が発光方
向を向き且つ前記化合物半導体の表面側が搭載面側を向
く姿勢として導通搭載するサブマウントとを備え、前記
発光素子のp電極及びn電極の総数を少なくとも3個以
上とし、これらのp電極及びn電極を結ぶ線分によって
包囲される多角形の基底を形成可能としてなる半導体発
光装置。
1. A light-emitting element in which a p-electrode and an n-electrode are respectively formed on a surface of a compound semiconductor laminated on an insulative and light-transmitting substrate; A submount for conducting and mounting the compound semiconductor such that the surface side of the compound semiconductor faces the mounting surface side, wherein the total number of the p-electrode and the n-electrode of the light-emitting element is at least three or more, and a line segment connecting the p-electrode and the n-electrode is provided. Semiconductor light emitting device capable of forming a polygonal base surrounded by
【請求項2】 前記サブマウントは、前記発光素子のp
電極及びn電極を正極性または逆極性で導通させる電極
パターンを表面に形成し、前記発光素子の少なくとも3
個以上のp電極及びn電極の配列パターンと、前記サブ
マウントの前記電極パターンとの間に、前記サブマウン
トに対する前記発光素子の搭載位置に自由度を与える関
係を持たせてなる請求項1記載の半導体発光装置。
2. The light emitting device according to claim 1, wherein the submount is a light emitting element.
Forming an electrode pattern on the surface for conducting the electrode and the n-electrode with a positive polarity or a reverse polarity;
2. The arrangement that gives a degree of freedom to a mounting position of the light emitting element with respect to the submount, between an arrangement pattern of at least one p electrode and n electrode and the electrode pattern of the submount. 3. Semiconductor light emitting device.
【請求項3】 前記発光素子のp電極及びn電極と、前
記サブマウントの電極パターンとを、前記発光素子側ま
たはサブマウント側のいずれか一方に形成したバンプ電
極によって導通接続してなる請求項2記載の半導体発光
装置。
3. The p-electrode and the n-electrode of the light-emitting element and the electrode pattern of the submount are electrically connected by a bump electrode formed on one of the light-emitting element side and the submount side. 3. The semiconductor light emitting device according to 2.
JP35007798A 1998-12-09 1998-12-09 Semiconductor light-emitting device Pending JP2000174348A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP35007798A JP2000174348A (en) 1998-12-09 1998-12-09 Semiconductor light-emitting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP35007798A JP2000174348A (en) 1998-12-09 1998-12-09 Semiconductor light-emitting device

Publications (1)

Publication Number Publication Date
JP2000174348A true JP2000174348A (en) 2000-06-23

Family

ID=18408084

Family Applications (1)

Application Number Title Priority Date Filing Date
JP35007798A Pending JP2000174348A (en) 1998-12-09 1998-12-09 Semiconductor light-emitting device

Country Status (1)

Country Link
JP (1) JP2000174348A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009302542A (en) * 2008-06-13 2009-12-24 Samsung Electronics Co Ltd Light emitting element, light emitting device including light emitting element, method for manufacturing light emitting element, and method for manufacturing light emitting device including light emitting element
US7939836B2 (en) 2007-07-18 2011-05-10 Nichia Corporation Semiconductor light emitting element
EP3078899A1 (en) * 2001-08-09 2016-10-12 Everlight Electronics Co., Ltd Led illuminator and card type led illuminating light source
JP2021010022A (en) * 2020-10-13 2021-01-28 日亜化学工業株式会社 Method of manufacturing light-emitting device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3078899A1 (en) * 2001-08-09 2016-10-12 Everlight Electronics Co., Ltd Led illuminator and card type led illuminating light source
US7939836B2 (en) 2007-07-18 2011-05-10 Nichia Corporation Semiconductor light emitting element
JP2009302542A (en) * 2008-06-13 2009-12-24 Samsung Electronics Co Ltd Light emitting element, light emitting device including light emitting element, method for manufacturing light emitting element, and method for manufacturing light emitting device including light emitting element
US8975656B2 (en) 2008-06-13 2015-03-10 Samsung Electronics Co., Ltd. Light emitting elements, light emitting devices including light emitting elements and methods of manufacturing such light emitting elements and/or device
DE102009025185B4 (en) * 2008-06-13 2016-05-25 Samsung Electronics Co., Ltd. Light emitting device, light emitting device and method for producing and operating such a light device
JP2021010022A (en) * 2020-10-13 2021-01-28 日亜化学工業株式会社 Method of manufacturing light-emitting device
JP7078868B2 (en) 2020-10-13 2022-06-01 日亜化学工業株式会社 Manufacturing method of light emitting device

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