JP3454097B2 - 電子部品および電子部品の製造方法 - Google Patents
電子部品および電子部品の製造方法Info
- Publication number
- JP3454097B2 JP3454097B2 JP22219697A JP22219697A JP3454097B2 JP 3454097 B2 JP3454097 B2 JP 3454097B2 JP 22219697 A JP22219697 A JP 22219697A JP 22219697 A JP22219697 A JP 22219697A JP 3454097 B2 JP3454097 B2 JP 3454097B2
- Authority
- JP
- Japan
- Prior art keywords
- gold
- substrate
- electrode
- gold film
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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Description
子部品の製造方法に関するものである。
面の電極上に基板と半導体素子を接続するためのワイヤ
をボンディングするとともに、他の電極上に突出電極で
あるバンプを形成するものが知られている。このような
電子部品としては、BGA(Ball Grid Ar
ray)パッケージが知られている。ワイヤとしては金
ワイヤが多用されており、またバンプとしては半田が多
用されている。
中、1はガラエポ基板などの基板であり、その上側と下
側の表面には回路パターンの銅電極2、3が形成されて
いる。また銅電極2、3上にはニッケル膜4、5が形成
されており、ニッケル膜4、5上には金膜6、7が形成
されている。そして上面側の銅電極2と下面側の銅電極
3は内部配線8で接続されている。一方の銅電極2の金
膜6上に基板1に搭載されたチップ(図外)を接続する
ための金ワイヤ9の先端をボンディングし、他方の銅電
極3の金膜7上に半田バンプ10を形成して電子部品を
組み立てる。
ッキ法により形成される。金膜6、7は金ワイヤ9のボ
ンディング性を向上させるためのに形成されている。従
来、金膜6、7の厚さは0.2〜1ミクロン程度であっ
てかなり厚いものである。ニッケル膜4、5は銅電極
2、3の素材である銅が金膜6、7中へ拡散し、空気に
触れて酸化膜を生じるのを防ぐためのバリヤメタルとし
て形成されている。なお金膜6の表面に酸化膜が生じれ
ば、金ワイヤ9のボンディングが不良になる。
を電解メッキするときにバリアメタルであるニッケル膜
4,5の成分のニッケルがメッキ液に溶け込みこのニッ
ケルが金メッキに混入する。混入したニッケルのうち金
膜6、7の表面に位置するものは、チップを固定する工
程で加熱により酸化膜を形成する。この酸化膜は金ワイ
ヤ9のボンディングを阻害する。金膜が厚くなるほどそ
の表面のニッケルは少なくなるので、できるだけこの酸
化膜が形成されないように金膜6,7の厚さはある程度
以上に厚くする必要がある。
バンプ10のボンディング力を低下させる。何故なら
ば、半田バンプ10を形成する際には、金膜7中の金は
半田バンプ10中へ溶解して半田中のスズと脆い化合物
を形成するからである。このように金ワイヤ9のボンデ
ィングのためには一方の金膜6は厚い方がよく、これに
対し半田バンプ10の形成などの半田付けに際しては他
方の金膜7は薄い方がよく、すなわち両者を同時に満足
することができず背反関係にあるという問題点があっ
た。
ヤを良好にボンディングできるとともに、半田付けを良
好に行える電子部品の製造方法を提供することを目的と
する。
は、銅電極の表面に少なくともニッケルを含むバリヤメ
タルを形成して成る電極が形成された基板と、前記バリ
ヤメタル上に形成された金膜と、前記基板上に搭載され
た半導体素子と、この半導体素子と前記金膜を接続する
接続手段と、ドライエッチングにより薄膜化した金膜状
に形成された半田付け部とを有する。
板に形成された銅電極の表面に少なくともニッケルを含
むバリヤメタルを形成する工程と、このバリヤメタル上
に金膜を形成する工程と、半導体素子を前記基板上に搭
載する工程と、この半導体素子を前記金膜に接続する工
程と、前記半導体素子を樹脂封止する工程と、樹脂封止
後に前記金膜をドライエッチングにより薄膜化する工程
と、前記金膜を薄膜化した電極上に半田付けを行う工程
とを含む。
の電極上に金膜を形成した後に半田の接合性を阻害する
金膜をプラズマクリーニングにより除去して薄くした後
に半田バンプの形成を行うことにより、ワイヤボンディ
ングなどによる金膜と半導体素子との接続が良好に行え
るとともに、半田バンプを良好に形成できる。
て説明する。図1は本発明の一実施の形態の電子部品の
組立構造図、図2、図3は同基板の断面図、図4は同基
板の部分断面図、図5、図6は同基板の断面図、図7は
同ドライエッチング装置の断面図、図8、図9は同基板
の断面図である。
図1において、11は基板であり、基板11の上面には
チップ12が熱硬化型接着剤31でボンディングされて
いる。チップ12の表面の電極13と基板上面の電極1
4とは金ワイヤ15で電気的に接続されている。15’
は金ワイヤの先端部に形成された金ボールであり、この
金ボール15’が電極13にボンディングされている。
ている。電極16上には半田バンプ17が形成されてい
る。電極14と電極16は内部配線18で接続されてい
る。基板11の上面はチップ12や金ワイヤ15を封止
するため樹脂モールド19が形成されている。
部品の製造方法を説明する。なお図2〜図8は製造工程
順に示している。まず、図2に示すように、基板11の
上面側に電極14が形成される。電極14は銅電極21
上にバリアメタル層としてニッケル膜22をコーティン
グして形成し、更にニッケル膜22の上に金膜23が金
属接合性が十分な厚み、すなわち金属とのボンディング
を阻害しないために十分な厚み(0.2〜1ミクロン程
度)を以て形成されたものである。銅電極21は基板1
1の表面に銅箔を貼り付け、不要な部分をエッチングに
より除去して形成される。また、ニッケル膜22および
金膜23はメッキによって形成される。また下面側にも
電極16が同様に形成される。電極16は銅電極24上
にニッケル膜25をコーティングし、更にニッケル膜2
5の上に金膜26が上面側の電極14と同様に形成され
る。
半導体素子であるチップ12が搭載される。チップ12
は基板11の上面に予め塗布された熱硬化型接着剤31
によって接着され、その後基板11は熱処理される。熱
硬化型接着剤31が硬化することによりチップ12は基
板11に固定される。図4はこの熱処理後の基板11の
電極14、16付近の断面図である。ここで金膜23,
26は金属接合性に十分な厚みを有しているため、金ワ
イヤのボンディング性を阻害するニッケルの酸化膜は金
膜23,26の表面には生じない。
により金ワイヤ15を上面側の電極14の金膜23上に
ボンディングする。これにより、チップ12は金膜23
に接続される。したがって、金ワイヤ15はチップ12
と金膜23とを接続する接続手段となっている。このと
き金膜23の表面には金ワイヤのボンディング性を阻害
するニッケルの酸化膜がほとんどないため、良好なボン
ディングを行うことができる。この後、図6に示すよう
に樹脂モールド19によるチップ12および金ワイヤ1
5の封止が行われる。
ドライエッチングが行われる。以下図7を参照してこの
ドライエッチングに用いられるドライエッチング装置4
0の構造を説明する。図7において、41は上部ケーシ
ングである。上部ケーシング41は下部ケーシング42
とともに開閉可能な真空容器43を形成する。下部ケー
シング42の底部には電極44が配設されている。電極
44には高周波電源装置45が接続されている。下部ケ
ーシング42の底面にはパイプ46,47,48が設け
られている。パイプ46には真空源49が接続されてい
る。またパイプ47にはアルゴンガスなどのプラズマエ
ッチング用のガスを供給するガス供給部50が接続され
ている。またパイプ48には真空破壊用の弁51が接続
されている。
52が装着されている。アース電極52は接地部53に
接地され、電極44と対置されている。電極44上には
基板11が載置される。
ような構成より成り、以下その動作を説明する。図7に
示すように、基板11を反転し電極16側を上向きにし
て電極44上に載置した状態で上部ケーシング41が閉
じられる。次に真空源49が真空吸引を開始し、真空容
器43内部が所定の真空度に到達する。次にガス供給装
置50よりアルゴンガスが真空容器43内部に供給され
るとともに、電極44には高周波電源装置45により高
周波電圧が印加される。真空容器43内部のアルゴンガ
スはプラズマ状態のアルゴンイオンとなり、図7におい
て破線矢印で示すように電極44上に載置された基板1
1の上面に衝突してエッチングする。このようにして電
極16表面の金膜26が除去され、金膜26は厚さ0.
01〜0.2ミクロン程度に薄膜化される。金膜26を
完全に除去しないのは、溶融した半田と電極16とのぬ
れ性を良好に保つためである。
26上に半田ボール17が搭載される。このとき、半田
ボール17と金膜26の間にはフラックス20が塗布さ
れる。この後基板11はリフロー工程に送られ、半田ボ
ール17は電極16面に半田付けされ、半田付け部とし
ての半田バンプ17となって図1に示す電子部品Aは完
成する。このとき金膜26は半田バンプ17中に溶解す
るが、金膜26はドライエッチングにより薄膜化されて
いるため半田バンプ17中に溶解する金の量はきわめて
少量である。したがって半田バンプ17のボンディング
性を悪化させる金とスズの化合物の形成はわずかであ
り、信頼性の高い半田バンプ17が形成される。また、
金膜26の表面はエッチング処理されるため、半田のぬ
れ性を阻害するニッケルや汚染物等もきれいに取り除か
れている。したがって半田を電極にぬれ性よく接合させ
ることができる。
であって、上記実施の形態ではワイヤボンディングによ
り半導体素子を電極14の金膜23に接続する例を示し
ているが、接続の方法はこれに限定されず、リボンボン
ディング、TABボンディング、フリップチップボンデ
ィングなどによるものであってもよい。
側に半導体素子が搭載され、他方の側に半田バンプが形
成される例を示しているが、要はボンディングと半田付
けが同一の基板内に混在する形態であればよい。例えば
図9(a)に示すように、基板41に半導体素子42を
搭載してワイヤボンディングにより基板41の電極と接
続し、この同一面に形成された電極44上の金膜を薄膜
化した後に電子部品45を半田付けにより実装する形態
であってもよく、更に図9(b)に示すように基板46
の電極47に半導体素子48をワイヤボンディングによ
り接続し、同一面に形成された電極49上の金膜を薄膜
化した後に半田バンプ50を形成する形態であってもよ
い。
た後に半田の接合性を阻害する金膜をドライエッチング
により除去して薄くした後に半田バンプなどの半田付け
を行うようにしているので、ワイヤボンディングなどに
よる金膜と半導体素子との接続に対してはボンディング
を妨げるニッケルの酸化膜がなく良好なボンディングを
行えるとともに、半田付けに対してはスズと金の脆弱な
化合物の生成がなく良好な半田付けを行うことができ、
したがって信頼性の高い電子部品を得ることができる。
の断面図
Claims (2)
- 【請求項1】銅電極の表面に少なくともニッケルを含む
バリヤメタルを形成して成る電極が形成された基板と、
前記バリヤメタル上に形成された金膜と、前記基板上に
搭載された半導体素子と、この半導体素子と前記金膜を
接続する接続手段と、ドライエッチングにより薄膜化し
た金膜状に形成された半田付け部とを有することを特徴
とする電子部品。 - 【請求項2】基板に形成された銅電極の表面に少なくと
もニッケルを含むバリヤメタルを形成する工程と、この
バリヤメタル上に金膜を形成する工程と、半導体素子を
前記基板上に搭載する工程と、この半導体素子を前記金
膜に接続する工程と、前記半導体素子を樹脂封止する工
程と、樹脂封止後に前記金膜をドライエッチングにより
薄膜化する工程と、前記金膜を薄膜化した電極上に半田
付けを行う工程とを含むことを特徴とする電子部品の製
造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22219697A JP3454097B2 (ja) | 1997-08-19 | 1997-08-19 | 電子部品および電子部品の製造方法 |
US08/979,694 US5909633A (en) | 1996-11-29 | 1997-11-26 | Method of manufacturing an electronic component |
KR1019970064578A KR100272399B1 (ko) | 1996-11-29 | 1997-11-29 | 전자부품의 제조방법 및 이에 의해 제조된 전자부품 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22219697A JP3454097B2 (ja) | 1997-08-19 | 1997-08-19 | 電子部品および電子部品の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH1167957A JPH1167957A (ja) | 1999-03-09 |
JP3454097B2 true JP3454097B2 (ja) | 2003-10-06 |
Family
ID=16778658
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22219697A Expired - Fee Related JP3454097B2 (ja) | 1996-11-29 | 1997-08-19 | 電子部品および電子部品の製造方法 |
Country Status (1)
Country | Link |
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JP (1) | JP3454097B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6403457B2 (en) | 1999-08-25 | 2002-06-11 | Micron Technology, Inc. | Selectively coating bond pads |
US6420207B1 (en) * | 2000-01-04 | 2002-07-16 | Multek Hong Kong Limited | Semiconductor package and enhanced FBG manufacturing |
-
1997
- 1997-08-19 JP JP22219697A patent/JP3454097B2/ja not_active Expired - Fee Related
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