JP3294084B2 - Device mounting structure and mounting method - Google Patents
Device mounting structure and mounting methodInfo
- Publication number
- JP3294084B2 JP3294084B2 JP28350295A JP28350295A JP3294084B2 JP 3294084 B2 JP3294084 B2 JP 3294084B2 JP 28350295 A JP28350295 A JP 28350295A JP 28350295 A JP28350295 A JP 28350295A JP 3294084 B2 JP3294084 B2 JP 3294084B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- current film
- wiring board
- upper electrode
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Landscapes
- Wire Bonding (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、素子の実装構造及
びその実装方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device mounting structure and a mounting method thereof.
【０００２】[0002]
【従来の技術】従来、このような分野の技術としては、
例えば、本多 進編、“最適ＳＭＴ実装技術ハンドブッ
ク”、ＳＣＩＥＮＣＥ ＦＯＲＵＭ，１９９０，Ｐ．３
４５〜３４６に開示されるものがあった。2. Description of the Related Art Conventionally, techniques in such a field include:
See, for example, Susumu Honda, “Optimal SMT Packaging Technology Handbook”, SCIENCE FORUM, 1990, p. 3
45-346.
【０００３】図４はかかる従来の素子の実装構造を示す
図である。FIG. 4 shows a mounting structure of such a conventional device.
【０００４】この図において、１は配線基板、２はその
配線基板１上に形成される基板電極、３は電気的接続体
（例えば、半田バンプ）であり、この電気的接続体３を
介して素子（例えば、半導体素子）５が実装される。In this figure, 1 is a wiring board, 2 is a substrate electrode formed on the wiring board 1, and 3 is an electrical connection (for example, a solder bump). An element (for example, a semiconductor element) 5 is mounted.
【０００５】このように、配線基板１上に形成された基
板電極２と素子５上の電極４とを、電気的接続体３とし
ての、例えば半田バンプなどにより接合し、配線基板１
と素子５との電気的接続を行うようにしていた。[0005] As described above, the substrate electrode 2 formed on the wiring board 1 and the electrode 4 on the element 5 are joined by, for example, a solder bump or the like as the electrical connection body 3, and the wiring board 1
And the element 5 is electrically connected.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、上記し
たように、従来の方法では、電気的接続部（例えば、半
田バンプ）の形状が球形であるために、接続部周囲が強
度的に弱い。そして、素子が実装された配線基板の使用
環境下における温度変化や素子の発熱による温度変化が
起こり、素子と配線基板の熱膨張係数が異なるため、両
者の変形によって電気的接続部にひずみが集中し、過度
の場合には電気的接続部にクラックを生じるなどして、
接続不良を引き起こすことがあった。また、電気的接続
部を強固なものとするために接続部形状を柱状とする場
合では、その形成方法が複雑なものとなり、技術的に問
題があった。However, as described above, in the conventional method, since the shape of the electrical connection portion (for example, solder bump) is spherical, the periphery of the connection portion is weak in strength. Then, a temperature change occurs in the use environment of the wiring board on which the element is mounted and a temperature change due to heat generation of the element, and the thermal expansion coefficients of the element and the wiring board are different. And, if excessive, crack the electrical connection, etc.
In some cases, poor connection was caused. Further, in the case where the shape of the connection portion is columnar in order to strengthen the electrical connection portion, the forming method becomes complicated, and there is a technical problem.
【０００７】本発明は、上記問題点を除去し、電気的接
続部におけるクラックを防止することができ、接続不良
を低減し、接続信頼性の向上を図り得る素子の実装構造
及びその実装方法を提供することを目的とする。SUMMARY OF THE INVENTION The present invention provides an element mounting structure and a mounting method capable of eliminating the above problems, preventing cracks in an electrical connection portion, reducing connection failures, and improving connection reliability. The purpose is to provide.
【０００８】[0008]
【課題を解決するための手段】本発明は、上記目的を達
成するために、 （１）素子の実装構造において、前記素子の周辺に形成
された複数の電極と、前記素子を搭載する素子搭載領域
を有する配線基板と、この配線基板の前記素子搭載領域
上に設けられた複数の下部接続部と、前記素子の前記複
数の電極に対応する前記素子搭載領域上に、前記複数の
下部接続部に接続されるように設けられた複数の上部電
極部と、前記素子の前記複数の電極と前記複数の上部電
極部とをそれぞれ接続する複数の電気的接続体とを有し
ており、前記複数の下部接続部の各々は、前記複数の上
部電極部が設けられた領域よりも、前記素子搭載領域の
略中央側に設けられており、前記複数の上部電極部の各
々は、前記下部接続部の下端と１２μｍ以下の間隔を有
して設けられていることを特徴とする。In order to achieve the above object, the present invention provides: (1) a device mounting structure, comprising: a plurality of electrodes formed around the device; and a device mounting device for mounting the device. A wiring board having a region, a plurality of lower connection portions provided on the element mounting region of the wiring substrate, and the plurality of lower connection portions on the element mounting region corresponding to the plurality of electrodes of the element. A plurality of upper electrode portions provided so as to be connected to the plurality of electrodes, and a plurality of electrical connectors for respectively connecting the plurality of electrodes and the plurality of upper electrode portions of the element, each lower connecting portion, than the plurality of upper electrode portions are provided regions, wherein provided in a substantially central portion of the element mounting area, each of the plurality of upper electrode portion, the lower connecting portion have a lower end and an interval less than 12μm
And characterized in that provided.
【０００９】（２）上記（１）記載の素子の実装構造に
おいて、前記複数の上部電極部の各々は、前記素子搭載
領域の周辺から、前記略中央側に向かって延在している
ことを特徴とする。 (2) The mounting structure of the element described in (1) above
Wherein each of the plurality of upper electrode portions is mounted with the element.
Extending from the periphery of the region toward the substantially center side
It is characterized by the following.
【００１０】（３）上記（１）又は（２）記載の素子の
実装構造において、前記配線基板と前記複数の下部接続
部との間にはカレントフィルムが設けられていることを
特徴とする。 (3) The device according to the above (1) or (2)
In the mounting structure, the wiring board and the plurality of lower connections
That there is a current film between
Features.
【００１１】（４）素子の実装方法において、配線基板
上に電極を形成するためのカレントフィルムを形成する
工程と、このカレントフィルムと同種の金属により、こ
のカレントフィルムの部位上にダミー電極を形成する工
程と、前記カレントフィルムの部位と、前記ダミー電極
上に跨がり、オフセット形状になるように形成される基
板電極と、前記カレントフィルムの部位以外の部分と、
前記ダミー電極のみを同時に除去する工程と、前記カレ
ントフィルムに接続される下部接続部とオフセット形状
に形成され、前記配線基板間に空隙を有する上部電極部
とを有する基板電極を形成する工程と、前記基板電極の
少なくとも前記上部電極部の一部に接続体を介して素子
を接続する工程とを施すことを特徴とする。 (4) In the element mounting method, a step of forming a current film for forming an electrode on a wiring board, and forming a dummy electrode on a portion of the current film using the same kind of metal as the current film Step, the portion of the current film, the substrate electrode straddling over the dummy electrode, formed to have an offset shape, and a portion other than the portion of the current film,
A step of simultaneously removing only the dummy electrode, and a step of forming a substrate electrode having a lower connection portion connected to the current film and an upper electrode portion formed in an offset shape and having a gap between the wiring substrates, Connecting an element to at least a part of the upper electrode portion of the substrate electrode via a connector.
【００１２】[0012]
【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照しながら説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１３】図１は本発明の実施例を示す素子の実装構
造図である。FIG. 1 is a mounting structure diagram of an element showing an embodiment of the present invention.
【００１４】従来の方法により製造された配線基板１１
の素子実装面側に、下部接続部１６−１が配線基板１１
上に接続され、他端はオフセット形状をなし、配線基板
１１の素子実装面側には接していない、即ち、基板電極
１６は空隙１９を有する上部電極部１６−２と下部接続
部１６−１から形成されている。さらに、配線基板１１
から離れた基板電極１６の上部電極部１６−２上には電
気的接続体１８により接合された素子（例えば、半導体
素子）１７が実装されている。なお、図１において、１
２はカレントフィルムである。Wiring board 11 manufactured by a conventional method
Is connected to the wiring board 11 on the element mounting surface side.
The substrate electrode 16 is connected to the upper electrode portion 16-2 having the gap 19 and the lower connection portion 16-1. Is formed from. Further, the wiring board 11
An element (for example, a semiconductor element) 17 joined by an electrical connector 18 is mounted on the upper electrode portion 16-2 of the substrate electrode 16 away from the substrate electrode 16. In FIG. 1, 1
2 is a current film.
【００１５】図２は本発明の実施例を示す素子の実装工
程断面図（その１）、図３はその素子の実装工程断面図
（その２）である。FIG. 2 is a sectional view (part 1) of an element mounting process showing an embodiment of the present invention, and FIG. 3 is a sectional view (part 2) of an element mounting step.
【００１６】（１）まず、図２（ａ）に示すように、従
来の工法により製造された配線基板１１上に、後工程の
電解めっき時の給電膜として、無電解銅めっきプロセス
により、カレントフィルム１２を１μｍ以下の厚みに形
成する。(1) First, as shown in FIG. 2A, a current is supplied to a wiring board 11 manufactured by a conventional method by an electroless copper plating process as a power supply film in a later step of electrolytic plating. The film 12 is formed to a thickness of 1 μm or less.
【００１７】（２）次に、図２（ｂ）に示すように、ド
ライフィルムレジスト（以下ＤＦＲと略す）１３をラミ
ネートする。(2) Next, as shown in FIG. 2B, a dry film resist (hereinafter abbreviated as DFR) 13 is laminated.
【００１８】（３）次いで、図２（ｃ）に示すように、
電極を形成する部分のみマスクしたダミー電極用マスク
１４ａをＤＦＲ１３上に合わせ露光を行う。(3) Next, as shown in FIG.
Exposure is performed by aligning a dummy electrode mask 14a masking only a portion where an electrode is to be formed on the DFR 13.
【００１９】（４）次に、図２（ｄ）に示すように、１
％−Ｎａ2 ＣＯ3 水溶液で現像処理を行い、めっきレジ
ストとしてダミー電極用レジスト開口部１４ｃを形成す
る。(4) Next, as shown in FIG.
% -Na 2 CO 3 aqueous solution followed by development, to form the dummy electrodes resist opening 14c as a plating resist.
【００２０】（５）次に、図２（ｅ）に示すように、電
解銅めっきによりダミー電極用レジスト開口部１４ｃ内
に露出しているカレントフィルム１２表面のみに、ダミ
ー電極１４を１２μｍ以下の任意の厚さで形成する。(5) Next, as shown in FIG. 2 (e), the dummy electrode 14 having a size of 12 μm or less is formed only on the surface of the current film 12 exposed in the dummy electrode resist opening 14c by electrolytic copper plating. It is formed with an arbitrary thickness.
【００２１】（６）次いで、図２（ｆ）に示すように、
ＤＦＲ１３を３％−ＮａＯＨ水溶液で膨潤剥離する。(6) Next, as shown in FIG.
The DFR 13 is swelled and peeled with a 3% -NaOH aqueous solution.
【００２２】（７）次いで、図２（ｇ）に示すように、
再びダミー電極１４を含む配線基板１１表面にＤＦＲ１
５をラミネートする。(7) Next, as shown in FIG.
Again, the DFR1 is placed on the surface of the wiring board 11 including the dummy electrodes 14.
5 is laminated.
【００２３】（８）次に、図３（ａ）に示すように、基
板電極を形成する部分のみマスクした基板電極用マスク
１６ａをＤＦＲ１５上に合わせて露光を行う。(8) Next, as shown in FIG. 3A, exposure is performed by aligning the substrate electrode mask 16a masking only the portion where the substrate electrode is to be formed on the DFR 15.
【００２４】（９）次に、図３（ｂ）に示すように、１
％−ＮａＣＯ3 水溶液で現像処理をし、めっきレジスト
として基板電極用レジスト開口部１６ｃを形成する。(9) Next, as shown in FIG.
Then, a developing treatment is performed with a% -NaCO 3 aqueous solution to form a resist opening 16c for a substrate electrode as a plating resist.
【００２５】（１０）次に、図３（ｃ）に示すように、
電解ニッケルめっきにより基板電極用レジスト開口部１
６ｃ内に露出したダミー電極１４を含むカレントフィル
ム１２上にオフセット形状に基板電極１６を２０μｍ以
上の任意の厚さで形成する。つまり、この基板電極１６
は下部接続部１６−１と、これに接続されオフセット形
状を有する上部電極部１６−２からなる。(10) Next, as shown in FIG.
Resist opening for substrate electrode 1 by electrolytic nickel plating
The substrate electrode 16 is formed in an offset shape on the current film 12 including the dummy electrode 14 exposed in 6c in an arbitrary thickness of 20 μm or more. That is, this substrate electrode 16
Is composed of a lower connection portion 16-1 and an upper electrode portion 16-2 connected to the lower connection portion 16-1 and having an offset shape.
【００２６】（１１）次に、図３（ｄ）に示すように、
ＤＦＲ１５を３％−ＮａＯＨ水溶液で膨潤剥離する。(11) Next, as shown in FIG.
DFR15 is swelled and peeled with a 3% -NaOH aqueous solution.
【００２７】（１２）次に、図３（ｅ）に示すように、
素子（例えば、半導体素子）１７を基板電極１６の上部
電極部１６−２上に電気的接続体１８を介して接合す
る。(12) Next, as shown in FIG.
An element (for example, a semiconductor element) 17 is joined to the upper electrode portion 16-2 of the substrate electrode 16 via an electrical connector 18.
【００２８】（１３）次に、図３（ｆ）に示すように、
基板電極１６と接触している部分以外のカレントフィル
ム１２及び、ダミー電極１４を銅アンモニウム錯イオン
を主成分とするアルカリエッチング液で溶解除去し、配
線基板１１上への素子１７の実装が完了する。(13) Next, as shown in FIG.
The current film 12 other than the portion in contact with the substrate electrode 16 and the dummy electrode 14 are dissolved and removed with an alkali etching solution containing copper ammonium complex ions as a main component, and the mounting of the element 17 on the wiring substrate 11 is completed. .
【００２９】上記のように構成したので、配線基板１１
の素子実装面側には、配線基板１１上に一部分のみ接し
ていない、即ち、空隙１９を有する上部電極部１６−２
を具えた基板電極１６が形成されており、この空隙１９
を有する上部電極部１６−２上に電気的接続体１８で接
合された素子１７が実装される構造としたので、配線基
板１１や素子１７が熱などにより変形し、電気的接続体
にひずみが集中するような状態においても、基板電極１
６の上部電極部１６−２が配線基板１１上に固定されて
いないので、上部電極部１６−２が柔軟に変形すること
で電気的接続体１８のひずみを分散、吸収することがで
き、電気的接続体１８におけるクラックを防止すること
ができ、接続不良を低減することができる。With the above configuration, the wiring board 11
Is not in contact with only a part of the wiring board 11 on the element mounting surface side, that is, the upper electrode portion 16-2 having the gap 19
A substrate electrode 16 having a gap 19 is formed.
Since the element 17 joined by the electrical connection body 18 is mounted on the upper electrode portion 16-2 having the following structure, the wiring board 11 and the element 17 are deformed by heat or the like, and the electrical connection body is distorted. Even in a state of concentration, the substrate electrode 1
6, the upper electrode portion 16-2 is not fixed on the wiring board 11, so that the upper electrode portion 16-2 can be flexibly deformed, thereby dispersing and absorbing the strain of the electrical connection body 18, and It is possible to prevent cracks in the dynamic connector 18 and reduce connection failures.
【００３０】また、本発明の素子の実装構造を得るため
配線基板上の基板電極として、カレントフィルムと同種
の金属でダミー電極を形成し、このダミー電極と異なる
金属で、基板電極を形成するようにしているため、最終
的な基板電極構造形成時のカレントフィルムとダミー電
極の除去を基板電極が影響を受けることなく選択的に、
精度良く実施することができる。In order to obtain the mounting structure of the device of the present invention, a dummy electrode is formed of the same kind of metal as the current film as a substrate electrode on the wiring board, and the substrate electrode is formed of a metal different from the dummy electrode. Therefore, the removal of the current film and the dummy electrode during the final formation of the substrate electrode structure can be selectively performed without affecting the substrate electrode.
It can be performed with high accuracy.
【００３１】更に、本発明は、以下のような利用形態を
有する。Further, the present invention has the following utilization modes.
【００３２】本発明の素子の実装構造においては、素子
が、基板電極の空隙を有する上部電極部上に電気的接続
体をもって実装されている構造について説明したが、必
ずしもこれに限定されるものではなく、電気的接続体の
一部分が基板電極の空隙を有する上部電極部の上に接合
しており、その他の電気的接続体は配線基板上に接続さ
れている下部接続部上に接合している構造とすることも
できる。また、基板電極の空隙を有する上部電極部は、
配線基板上に接続されている他端側のみに限定されるも
のではない。In the device mounting structure of the present invention, a structure in which the device is mounted on the upper electrode portion having the gap of the substrate electrode with an electrical connection member has been described, but the present invention is not necessarily limited to this. Instead, a portion of the electrical connection is bonded on the upper electrode portion having a gap of the substrate electrode, and the other electrical connection is bonded on the lower connection portion connected on the wiring board. It can also be structured. In addition, the upper electrode portion having the gap of the substrate electrode,
It is not limited to only the other end connected to the wiring board.
【００３３】本発明の素子の実装方法においては、カレ
ントフィルム及び、ダミー電極として、銅、基板電極と
してニッケルを用いて説明したが、カレントフィルム及
びダミー電極としてニッケル、基板電極として銅を用い
ることもでき、この場合、カレントフィルム及びダミー
電極のエッチング液として、硫酸：硝酸＝２：１の混合
液を使用する。In the device mounting method of the present invention , the current film and the dummy electrode have been described using copper and the substrate electrode has been described as nickel. However, nickel may be used as the current film and the dummy electrode and copper may be used as the substrate electrode. In this case, a mixed solution of sulfuric acid: nitric acid = 2: 1 is used as an etching solution for the current film and the dummy electrode.
【００３４】また、カレントフィルム及びダミー電極を
銅で形成し、基板電極として半田や金などを使用するこ
ともできる。Alternatively, the current film and the dummy electrode may be formed of copper, and solder or gold may be used as the substrate electrode.
【００３５】更に、カレントフィルム及びダミー電極の
エッチング液としては、アルカリエッチング液の他、過
硫酸アンモニウム、過硫酸ナトリウム、過硫酸カリウム
などの過硫酸塩類を主成分とする水溶液からなるエッチ
ング液、または過酸化水素／硫酸エッチング液などを選
択することができる。Further, as an etching solution for the current film and the dummy electrode, an etching solution containing an aqueous solution mainly containing persulfates such as ammonium persulfate, sodium persulfate and potassium persulfate, or an alkali etching solution, or A hydrogen oxide / sulfuric acid etching solution or the like can be selected.
【００３６】また、ダミー電極又は基板電極形成のため
ＤＦＲを用いた例について説明したが、必ずしもこれに
限定されるのではなく、液状レジストや電着レジストな
どレジストパターンが形成可能なものであればいずれも
使用することができる。Also, an example in which a DFR is used to form a dummy electrode or a substrate electrode has been described. However, the present invention is not limited to this, and any liquid resist or electrodeposition resist can be used as long as a resist pattern can be formed. Either can be used.
【００３７】なお、本発明は上記実施例に限定されるも
のではなく、本発明の趣旨に基づいて種々の変形が可能
であり、これらを本発明の範囲から排除するものではな
い。It should be noted that the present invention is not limited to the above-described embodiment, and various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.
【００３８】[0038]
【発明の効果】以上、詳細に説明したように、本発明に
よれば、以下のような効果を奏することができる。As described above, according to the present invention, the following effects can be obtained.
【００３９】（Ａ）素子の実装構造によれば、配線基板
の素子実装面側には、配線基板上に一部分のみ接してい
ない、即ち、空隙を有する上部電極部を具えた基板電極
が形成されており、この空隙を有する上部電極部上に電
気的接続体で接合された素子が実装される構造としたの
で、配線基板や素子が熱などにより変形し、電気的接続
体にひずみが集中するような状態においても、基板電極
の上部電極部が配線基板上に固定されていないので、そ
の上部電極部が柔軟に変形することで電気的接続体のひ
ずみを分散、吸収することができ、電気的接続部におけ
るクラックを防止することができ、接続不良を低減し、
接続信頼性の向上を図ることができる。 (A) According to the device mounting structure , a substrate electrode having an upper electrode portion which is not in contact with only a part of the wiring substrate, that is, has an air gap, is formed on the device mounting surface side of the wiring substrate. Since the element joined by the electrical connection body is mounted on the upper electrode portion having the gap, the wiring board and the element are deformed by heat and the like, and the strain is concentrated on the electrical connection body. Even in such a state, since the upper electrode portion of the substrate electrode is not fixed on the wiring board, the upper electrode portion can be flexibly deformed to disperse and absorb the strain of the electrical connection body, and Cracks at the joints can be prevented, reducing connection failures,
Connection reliability can be improved.
【００４０】（Ｂ）素子の実装方法によれば、配線基板
上に、カレントフィルムと同種の金属でダミー電極を形
成し、このダミー電極と異なる金属で、基板電極を形成
するようにしているため、最終的な基板電極構造形成時
のカレントフィルムとダミー電極の除去を、基板電極が
影響を受けることなく選択的に、精度良く実施すること
ができる。 (B) According to the element mounting method , a dummy electrode is formed on the wiring substrate with the same kind of metal as the current film, and the substrate electrode is formed with a metal different from the dummy electrode. In addition, the removal of the current film and the dummy electrode at the time of final formation of the substrate electrode structure can be selectively and accurately performed without being affected by the substrate electrode.
【００４１】したがって、本発明の素子の実装構造を歩
留まり良く得ることができる。Therefore, the mounting structure of the device of the present invention can be obtained with high yield.
【図１】本発明の実施例を示す素子の実装構造図であ
る。FIG. 1 is a mounting structure diagram of an element showing an embodiment of the present invention.
【図２】本発明の実施例を示す素子の実装工程断面図
（その１）である。FIG. 2 is a cross-sectional view (part 1) of an element mounting process showing an example of the present invention.
【図３】本発明の実施例を示す素子の実装工程断面図
（その２）である。FIG. 3 is a sectional view (part 2) of a device mounting process showing an example of the present invention.
【図４】従来の素子の実装構造を示す図である。FIG. 4 is a view showing a mounting structure of a conventional element.
１１ 配線基板 １２ カレントフィルム １３，１５ ドライフィルムレジスト（ＤＦＲ） １４ ダミー電極 １４ａ ダミー電極用マスク １４ｃ ダミー電極用レジスト開口部 １６ 基板電極 １６ａ 基板電極用マスク １６ｃ 基板電極用レジスト開口部 １６−１ 下部接続部 １６−２ 上部電極部 １７ 素子 １８ 電気的接続体 １９ 空隙 DESCRIPTION OF SYMBOLS 11 Wiring board 12 Current film 13, 15 Dry film resist (DFR) 14 Dummy electrode 14a Dummy electrode mask 14c Dummy electrode resist opening 16 Substrate electrode 16a Substrate electrode mask 16c Substrate electrode resist opening 16-1 Lower connection Part 16-2 Upper electrode part 17 Element 18 Electrical connection 19 Void
───────────────────────────────────────────────────── フロントページの続き (72)発明者 烏野 ゆたか 東京都港区虎ノ門１丁目７番12号 沖電 気工業株式会社内 (72)発明者 板谷 哲 新潟県上越市福田町１番地 沖プリンテ ッドサーキット株式会社内 (56)参考文献 特開 平６−37233（ＪＰ，Ａ) 特開 平５−29389（ＪＰ，Ａ) 特開 平４−72690（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yutaka Karasuno 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (56) References JP-A-6-37233 (JP, A) JP-A-5-29389 (JP, A) JP-A-4-72690 (JP, A) (58) Fields investigated (Int .Cl. 7 , DB name) H01L 21/60
Claims (4)
部接続部と、 前記素子の前記複数の電極に対応する前記素子搭載領域
上に、前記複数の下部接続部に接続されるように設けら
れた複数の上部電極部と、 前記素子の前記複数の電極と前記複数の上部電極部とを
それぞれ接続する複数の電気的接続体とを有しており、 前記複数の下部接続部の各々は、前記複数の上部電極部
が設けられた領域よりも、前記素子搭載領域の略中央側
に設けられており、 前記複数の上部電極部の各々は、前記下部接続部の下端
と１２μｍ以下の間隔を有して設けられていることを特
徴とする素子の実装構造。1. An element mounting structure, comprising: a plurality of electrodes formed around the element; a wiring board having an element mounting area for mounting the element; and a wiring board provided on the element mounting area of the wiring board. A plurality of lower connection portions, a plurality of upper electrode portions provided on the element mounting region corresponding to the plurality of electrodes of the element so as to be connected to the plurality of lower connection portions, A plurality of electrical connection bodies respectively connecting the plurality of electrodes and the plurality of upper electrode portions, and each of the plurality of lower connection portions is a region where the plurality of upper electrode portions are provided. And each of the plurality of upper electrode portions is provided at a lower end of the lower connection portion.
Mounting structure of the element, characterized in that are provided have the following intervals 12μm and.
て、 前記複数の上部電極部の各々は、前記素子搭載領域の周
辺から、前記略中央側に向かって延在していることを特
徴とする素子の実装構造。2. The device mounting structure according to claim 1, wherein each of the plurality of upper electrode portions extends from a periphery of the device mounting region toward the substantially central side. Device mounting structure.
おいて、 前記配線基板と前記複数の下部接続部との間にはカレン
トフィルムが設けられていることを特徴とする素子の実
装構造。3. The device mounting structure according to claim 1, wherein a current film is provided between the wiring board and the plurality of lower connection portions.
ルムを形成する工程と、 （ｂ）該カレントフィルムと同種の金属により、該カレ
ントフィルムの部位上にダミー電極を形成する工程と、 （ｃ）前記カレントフィルムの部位と、前記ダミー電極
上に跨がり、オフセット形状になるように形成される基
板電極と、 （ｄ）前記カレントフィルムの部位以外の部分と、前記
ダミー電極のみを同時に除去する工程と、 （ｅ）前記カレントフィルムに接続される下部接続部と
オフセット形状に形成され、前記配線基板間に空隙を有
する上部電極部とを有する基板電極を形成する工程と、 （ｆ）前記基板電極の少なくとも前記上部電極部の一部
に接続体を介して素子を接続する工程とを施すことを特
徴とする素子の実装方法。4. A method for mounting an element, comprising: (a) forming a current film for forming an electrode on a wiring board; and (b) forming a current film on a portion of the current film by using a metal of the same kind as the current film. (C) a portion of the current film, a substrate electrode that straddles the dummy electrode and is formed to have an offset shape, and (d) a portion other than the portion of the current film. (E) a substrate electrode having a lower connection portion connected to the current film and an upper electrode portion formed in an offset shape and having a gap between the wiring substrates. And (f) connecting an element to at least a part of the upper electrode portion of the substrate electrode via a connector. The method of mounting the element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28350295A JP3294084B2 (en) | 1995-10-31 | 1995-10-31 | Device mounting structure and mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28350295A JP3294084B2 (en) | 1995-10-31 | 1995-10-31 | Device mounting structure and mounting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09129675A JPH09129675A (en) | 1997-05-16 |
| JP3294084B2 true JP3294084B2 (en) | 2002-06-17 |
Family
ID=17666385
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28350295A Expired - Fee Related JP3294084B2 (en) | 1995-10-31 | 1995-10-31 | Device mounting structure and mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3294084B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100807426B1 (en) * | 1999-07-30 | 2008-02-25 | 폼팩터, 인크. | Interconnect assemblies and methods |
| JP2001094227A (en) * | 1999-09-20 | 2001-04-06 | Shinko Electric Ind Co Ltd | Semiconductor chip mounting wiring board and semiconductor chip mounting method using the board |
| JP2007250712A (en) * | 2006-03-15 | 2007-09-27 | Nec Corp | Semiconductor device and method of manufacturing same |
| US7858512B2 (en) | 2008-06-26 | 2010-12-28 | Wafer-Level Packaging Portfolio Llc | Semiconductor with bottom-side wrap-around flange contact |
| US20090324906A1 (en) * | 2008-06-26 | 2009-12-31 | Marcoux Phil P | Semiconductor with top-side wrap-around flange contact |
-
1995
- 1995-10-31 JP JP28350295A patent/JP3294084B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09129675A (en) | 1997-05-16 |
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