JP3276254B2 - 水平同期パルス分離回路 - Google Patents

水平同期パルス分離回路

Info

Publication number
JP3276254B2
JP3276254B2 JP28847594A JP28847594A JP3276254B2 JP 3276254 B2 JP3276254 B2 JP 3276254B2 JP 28847594 A JP28847594 A JP 28847594A JP 28847594 A JP28847594 A JP 28847594A JP 3276254 B2 JP3276254 B2 JP 3276254B2
Authority
JP
Japan
Prior art keywords
pulse
signal
synchronizing signal
horizontal
horizontal synchronizing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP28847594A
Other languages
English (en)
Japanese (ja)
Other versions
JPH08149334A (ja
Inventor
幸光 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alps Alpine Co Ltd
Original Assignee
Alps Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alps Electric Co Ltd filed Critical Alps Electric Co Ltd
Priority to JP28847594A priority Critical patent/JP3276254B2/ja
Priority to KR1019950042707A priority patent/KR0175969B1/ko
Publication of JPH08149334A publication Critical patent/JPH08149334A/ja
Application granted granted Critical
Publication of JP3276254B2 publication Critical patent/JP3276254B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/08—Separation of synchronising signals from picture signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Synchronizing For Television (AREA)
JP28847594A 1994-11-22 1994-11-22 水平同期パルス分離回路 Expired - Fee Related JP3276254B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP28847594A JP3276254B2 (ja) 1994-11-22 1994-11-22 水平同期パルス分離回路
KR1019950042707A KR0175969B1 (ko) 1994-11-22 1995-11-22 수평동기 펄스 분리회로

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28847594A JP3276254B2 (ja) 1994-11-22 1994-11-22 水平同期パルス分離回路

Publications (2)

Publication Number Publication Date
JPH08149334A JPH08149334A (ja) 1996-06-07
JP3276254B2 true JP3276254B2 (ja) 2002-04-22

Family

ID=17730694

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28847594A Expired - Fee Related JP3276254B2 (ja) 1994-11-22 1994-11-22 水平同期パルス分離回路

Country Status (2)

Country Link
JP (1) JP3276254B2 (ko)
KR (1) KR0175969B1 (ko)

Also Published As

Publication number Publication date
KR0175969B1 (ko) 1999-05-01
JPH08149334A (ja) 1996-06-07
KR960020350A (ko) 1996-06-17

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Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20020122

LAPS Cancellation because of no payment of annual fees