JP3199061B2 - Layout method of semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a layout method for a semiconductor integrated circuit, and more particularly to a layout method for a semiconductor integrated circuit including unnecessary pins.

[0002]

2. Description of the Related Art Conventionally, in this type of layout method, as shown in FIG. 10, even if there is an unnecessary pin 31 in a macro block 30 in a chip 3, the layout is not deleted without deleting the unnecessary pin 31. Is going.

[0003] Alternatively, as shown in FIG.
If there is an unnecessary pin 31 in the macro block 30 in the macro block 30, the unnecessary pin 31 is deleted in order to relax the arrangement restriction of the internal block 40 in the macro block 30 and shorten the wiring length.
The layout is going on. In FIGS. 10 and 11, 32 to 38 indicate pins, and 39 indicates wiring.

[0004]

In the above-mentioned conventional layout method, extra wiring to the unnecessary pins is always taken into consideration in consideration of the connection to the unnecessary pins, so that the wiring length of the net and the wiring delay increase. This also leads to an increase in the wiring density of the net.

Further, since unnecessary pins are deleted from circuit data by reducing wiring length by deleting redundant wiring to unnecessary pins, redundant wiring to unnecessary pins is eliminated, thereby reducing wiring delay and the like. However, by removing unnecessary pins, compatibility with the original circuit data is lost.

Accordingly, it is an object of the present invention to solve the above-mentioned problems, eliminate redundant wiring, reduce wiring length and wiring delay, and maintain compatibility with original circuit data. An object of the present invention is to provide a layout method for a semiconductor integrated circuit that can be used.

[0007]

A layout method of a semiconductor integrated circuit according to the present invention is a layout method of a semiconductor integrated circuit for performing a layout process based on circuit data including unnecessary pins in a macro block. The information of the unnecessary pins in the circuit data is temporarily excluded from the processing target, a layout is performed based on the circuit data, and after the layout, the unnecessary pins are arranged based on the information of the unnecessary pins. .

Another layout method for a semiconductor integrated circuit according to the present invention is a layout method for a semiconductor integrated circuit that performs a layout process based on circuit data including unnecessary pins in a macro block. And temporarily laying out the unnecessary pin information based on the circuit data, and arranging the unnecessary pins based on the unnecessary pin information after the layout. .

That is, according to the layout method of the semiconductor integrated circuit of the present invention, unnecessary pins of a macro block are not deleted, but are removed (ignored) from circuit data at the time of layout such as necessary pins, that is, unnecessary pins are eliminated. Is temporarily excluded from the processing target, and the layout of the unnecessary pins and the nets connected thereto is performed after the layout is completed. This makes it possible to reduce the wiring length and the wiring delay (signal propagation delay) while maintaining the compatibility of the circuit data, and it is expected that the wiring property will be improved.

More specifically, in the layout method of the semiconductor integrated circuit according to the present invention, when there is an unnecessary pin among the pins prepared for each macro block in the hierarchical layout, the unnecessary pin and the net connected thereto are Is removed from the circuit data (ignored), that is, the unnecessary pins and the nets connected to the unnecessary pins are temporarily excluded from the processing target, and the layout is performed. To maintain the compatibility of circuit data. Therefore, it is possible to reduce the wiring length, reduce the wiring density, and reduce the wiring delay, and maintain the compatibility of the original circuit data.

At this time, by removing unnecessary pins from the circuit data, that is, by temporarily removing the unnecessary pins from the processing target, it is possible to eliminate the excess wiring up to that point, and the block layout restriction due to this is also reduced. As a result, the wiring length is shortened, and the wiring delay and the wiring density are also reduced. Furthermore, since layout can be performed without deleting pins and net information, compatibility with the original circuit data can be maintained.

[0012]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a flowchart showing the processing operation of the layout method according to one embodiment of the present invention. The processing operation of the layout method according to one embodiment of the present invention will be described with reference to FIG. The layout method according to the embodiment of the present invention is configured so that each process is performed by executing a program (software).

In the layout method according to one embodiment of the present invention, when there is an unnecessary pin among the pins prepared for each macro in the hierarchical layout (step S1 in FIG. 1).
The information on the unnecessary pins and the nets connected thereto is excluded from the circuit data (ignored), that is, the information on the unnecessary pins and the nets connected thereto is temporarily excluded from the processing target (step S2 in FIG. 1).

When the unnecessary pin and the net connected to it are removed from the circuit data (ignored), that is, the unnecessary pin and the net connected to it are temporarily excluded from the processing target (step S3 in FIG. 1). A layout is performed based on the circuit data from which the unnecessary pins have been removed (step S4 in FIG. 1).
However, when there is no unnecessary pin among the pins prepared for each macro block (step S1 in FIG. 1), the layout is performed based on the original circuit data (step S1 in FIG. 1).
4).

When the layout based on the circuit data is completed (step S5 in FIG. 1), the layout is performed based on the information on the unnecessary pins and the nets connected to the unnecessary pins which have been removed from the circuit data (step S6 in FIG. 1). When all the layouts are completed (step S7 in FIG. 1), the processing operation of the layout method according to the embodiment of the present invention ends.

FIG. 2 is a view showing an example in which unnecessary pins according to an embodiment of the present invention are laid out without being removed (not ignored), and FIG. 3 is a diagram in which unnecessary pins according to an embodiment of the present invention are laid out later. It is a figure showing an example. A layout process according to an embodiment of the present invention will be described with reference to FIGS.

The layout shown in FIG. 2 is based on the netlist of the macro block EX10 shown below. This netlist is indicated by MACRO EX EXTERNAL PIN OUT1 NET N1 COMPONENT BLK_A BLK_A NET N1 COMPONENT BLK_B BLK_B NET N1.

As shown in FIG. 2, this netlist has a macroblock EX10 in the chip 1, and an OUT pin 11 as an external PIN of the macroblock EX10. A NET (wiring) N1 is connected to the OUT pin 11 of the macro block EX1.
In block 0, blocks 19 called BLK_A and BLK_B,
20 and its blocks 19 and 20 have NET N1
Is connected.

When the placement and routing are performed on the netlist in consideration of the wiring length and the wiring delay, the layout shown in FIG. 2 is performed. At this time, since the OUT pin 11 is an unnecessary pin, the wiring from the point A to the OUT pin 11 becomes unnecessary.

As described above, the NET N1 connected to the outside of the macro block EX10 has an unconnected OUT pin 11, and the macro block E is connected to the OUT pin 11.
If there is no need to connect to the NET N1 in X10, the above-described layout method according to the present embodiment is applied to shorten the wiring length.

As can be seen from FIG. 2, since the OUT pin 11 has no wiring outside the macro block EX10, NE
To shorten the wiring length of T N1, the wiring from OUT pin 11 to point A is deleted, and OUT pin 11 is moved to NET N1 as shown in FIG. At this time, it is not necessary to delete blocks and pins, change connections, and the like in the netlist, and it is possible to reduce the wiring length of the NET N1 while maintaining information compatibility of the netlist.

When these FIGS. 2 and 3 are compared, OUT
By moving the pin 11, the wiring length of the NET N1 can be shortened, and the degree of wiring congestion in the portion occupied by the wiring is reduced.

Further, as the wiring length of the NET N1 becomes shorter, the wiring delay is reduced, and the chip 1 can operate at high speed. Furthermore, it is important that the netlist does not delete pins, blocks, nets, and the like, and that the information compatibility of the netlist is maintained even after the execution of the layout method according to the present embodiment.

In FIGS. 2 and 3, reference numerals 12 to 18 denote pins of the macro block EX10. The above processing is performed based on the processing operations of steps S1 to S7 shown in FIG.

FIG. 4 is a diagram showing an example in which unnecessary pins according to another embodiment of the present invention are laid out without removing (not neglecting) unnecessary pins, and FIG. 5 shows unnecessary pins according to another embodiment of the present invention. It is a figure showing the example which laid out. These FIGS. 4 and 5
A layout process according to another embodiment of the present invention will be described with reference to FIG.

The layout shown in FIG. 4 is based on the netlist of the macro block EX21 shown below. This netlist is represented by MACRO EX2 EXTERNAL PIN OUT1 NET N1 EXTERNAL PIN OUT2 NET N1 COMPONENT BLK_A BLK_A NET N1.

When placement and routing is performed on this netlist in consideration of the wiring length and the wiring delay, as shown in FIG.
Unnecessary pins from LK_A block 19 (EXTERNA
LPK_A block 19 so that the distance from either of the OUT pins 11 and 22 (LPIN) does not increase.
Is located near the center of the macro block EX21.

Although this is the optimum solution in consideration of the wiring length and the wiring delay, there is an OUT pin 11 that is not connected to the NET with the outside of the macro block EX21, such as the OUT pin 11, and the OUT pin 11 When it is not necessary to connect NETN1 in the macro block EX21 to the OUT11, the OUT pin 11 is moved to the vicinity of the OUT pin 22 in advance, and the wiring is performed.

At this time, there is no need to delete blocks or pins or change connections in the netlist, and the compatibility with the original circuit data is maintained. When the placement and routing is performed in this state, as shown in FIG.
Are arranged close to the OUT pins 11 and 22 and NET
N1 is also wired short.

When FIG. 4 is compared with FIG.
1 is moved before the placement and routing of the block 19 of the BLK_A, and then the placement and routing is performed, so that the wiring length of the NET N1 can be shortened, and the degree of wiring congestion of the portion occupied by the wiring can be reduced. Can be.

Further, since the wiring length of the NET N1 is reduced, the wiring delay is reduced, and the chip 1 can operate at high speed. Furthermore, since there is no deletion of pins, blocks, nets, and the like in the netlist, compatibility with the information of the netlist (original circuit data) is maintained even after the layout method according to the present embodiment is executed.

In FIGS. 4 and 5, reference numerals 12 to 18 denote pins of the macro block EX10. Further, the above processing is performed based on the processing operations of steps S1 to S7 shown in FIG. 1, and in particular, the processing operation of step S6 is different from that of the embodiment of the present invention.

FIG. 6 is a view showing an example in which unnecessary pins according to another embodiment of the present invention are laid out without removing (not neglecting) unnecessary pins. FIG. 7 shows unnecessary pins according to another embodiment of the present invention added later. It is a figure showing the example which laid out. These FIGS. 6 and 7
A layout process according to another embodiment of the present invention will be described with reference to FIG.

In FIG. 6, block 20 of BLK_B
And the NETN2 connecting the PIN A23 and the NETN2 bypassing the PIN A23 are largely detoured due to the obstacle 24. Therefore, when the wiring length of the NET N2 is long and the wiring delay is large, the OUT pin 11 which is an unnecessary pin of the macro block 26 is used. Is moved into the macro block 26, and the arrangement and wiring are performed.

Then, as shown in FIG.
The area where the T pin 11 is located can be used as a wiring area, and the wiring length of the NET N2 is shortened by wiring the NET N2 through the area, and the wiring delay can be reduced. Become.

As described above, in addition to the purpose of reducing the wiring length of the NET N1 connected to the OUT pin 11, which is an unnecessary pin, the present embodiment is also used to reduce the wiring length and the wiring delay of the other NET N2. Can be used. At this time, there is no deletion of blocks or pins on the netlist, and compatibility with the original circuit data is maintained.

In FIGS. 6 and 7, reference numerals 12 to 18 denote pins of the macro block 26, and reference numeral 25 denotes an obstacle. Further, the above processing is performed in steps S1 to S7 shown in FIG.
The processing operation of step S6 is different from that of the embodiment of the present invention.

FIG. 8 is a diagram showing an example in which unnecessary pins according to still another embodiment of the present invention are laid out without removing (not neglecting) unnecessary pins. FIG. 9 shows unnecessary pins according to still another embodiment of the present invention. It is a figure showing the example which laid out later. A layout process according to still another embodiment of the present invention will be described with reference to FIGS.

In FIG. 8, OUT is an unnecessary pin.
If there is a partial circuit 29 connected to the pins 11 and 22, and the area (block A27) on which the partial circuit 29 is mounted is very crowded with other blocks and wirings (not shown),
As shown in FIG. 9, the unnecessary partial circuit 29 is moved to an uncongested area (block B28) together with the OUT pins 11 and 22, which are unnecessary pins, to perform arrangement and wiring.

As a result, excess wiring from the OUT pins 11 and 22 can be minimized, and the congestion area 27 can be reduced.
Congestion can be alleviated. Therefore, the degree of wiring congestion is alleviated, and it is possible to eliminate the detour of other wiring. At this time, no pin or block is deleted from the net list, and the compatibility with the net list (original circuit data) can be maintained even after the layout method according to the present embodiment is applied.

In FIGS. 8 and 9, reference numerals 12 to 18 denote pins of the macro block 26. Further, the above processing is performed based on the processing operations of steps S1 to S7 shown in FIG. 1, and in particular, the processing operation of step S6 is different from that of the embodiment of the present invention.

As described above, at the time of the hierarchical layout, each macro (the macro blocks EX10 and 21 and the macro block 2
When unnecessary pins (OUT pins 11 and 22) exist among the pins prepared in 6), the unnecessary pins and the nets (NET N1 and N2) connected to the unnecessary pins are removed from circuit data (ignored). In other words, the layout is performed by temporarily omitting the unnecessary pins and the nets connected to the unnecessary pins, and arranging the unnecessary pins and the nets on the laid-out nets after completion of the layout, so that the compatibility of the circuit data is improved. The wiring length and wiring delay (signal propagation delay) can be reduced while maintaining the wiring density, and the wiring density can be reduced, so that the wiring properties can be improved.

At this time, by removing unnecessary pins from the circuit data, that is, by temporarily removing the unnecessary pins from the processing target, it is possible to eliminate the excess wiring up to that point, and the block arrangement restriction due to this is eliminated. As a result, the wiring length is shortened, and the wiring delay and the wiring density are also reduced. Further, since the layout can be performed without deleting the pin and the net information, compatibility with the original circuit data can be maintained.

[0044]

As described above, according to the present invention, in a layout method of a semiconductor integrated circuit for performing a layout process based on circuit data including unnecessary pins in a macro block by executing a program, an unnecessary pin is not included in the layout process. By laying out the information temporarily out of the processing target and executing a program to arrange the unnecessary pins after the layout, excess wiring can be eliminated, and the wiring length and wiring delay can be reduced. This has the effect that compatibility with the original circuit data can be maintained.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a processing operation of a layout method according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a layout without removing unnecessary pins according to an embodiment of the present invention.

FIG. 3 is a diagram showing an example in which unnecessary pins are laid out later according to an embodiment of the present invention.

FIG. 4 is a diagram showing an example of a layout without removing unnecessary pins according to another embodiment of the present invention.

FIG. 5 is a diagram showing an example in which unnecessary pins are laid out later according to another embodiment of the present invention.

FIG. 6 is a diagram showing an example of a layout without removing unnecessary pins according to another embodiment of the present invention.

FIG. 7 is a diagram showing an example in which unnecessary pins according to another embodiment of the present invention are laid out later.

FIG. 8 is a diagram showing an example of a layout without removing unnecessary pins according to still another embodiment of the present invention.

FIG. 9 is a diagram showing an example in which unnecessary pins are laid out later according to still another embodiment of the present invention.

FIG. 10 is a diagram showing an example of a layout in which unnecessary pins are not deleted according to a conventional example.

FIG. 11 is a diagram showing an example of a layout in which unnecessary pins are deleted according to a conventional example.

[Explanation of symbols]

 1 chip 10, 21 macro block EX 11, 22 OUT pin 12 to 18 pin 19 block of BLK_A 20 block of BLK_B 23 PINA 24, 25 obstacle 26 macro block 27 area block where wiring is congested 28 wiring is congested Not area block

Claims (8)

(57) [Claims] 1. A layout method for a semiconductor integrated circuit that performs a layout process based on circuit data including unnecessary pins in a macro block, wherein information on the unnecessary pins in the circuit data is temporarily processed in the layout process. A layout method wherein a layout based on the circuit data is performed as a non-target, and after the layout, the unnecessary pins are arranged based on the information on the unnecessary pins. 2. The layout method according to claim 1, wherein another wiring is arranged in a region vacated by the arrangement of the unnecessary pins. 3. When the information of the unnecessary pin is temporarily excluded from the processing target, the information of the wiring and the circuit connected to the unnecessary pin in the circuit data is temporarily excluded from the processing target. Is performed, and after the layout, the unnecessary pins and the wires and circuits connected to the unnecessary pins are arranged based on the information of the unnecessary pins and the information of the wires and circuits connected to the unnecessary pins. 3. The layout method according to claim 1, wherein 4. The layout method according to claim 3, wherein when arranging the wiring and the circuit connected to the unnecessary pins, the wiring and the circuit are arranged in an area where the wiring is not congested. 5. A layout method for a semiconductor integrated circuit that performs a layout process based on circuit data including unnecessary pins in a macro block, wherein information on the unnecessary pins in the circuit data is temporarily processed in the layout process. A layout method comprising the steps of: laying out based on the circuit data out of the object; and arranging the unnecessary pins based on the information of the unnecessary pins after the layout. 6. The layout method according to claim 5, wherein another wiring is arranged in an area vacated by the step of arranging the unnecessary pins. 7. The step of temporarily excluding the information of the unnecessary pins from being processed is a step of temporarily excluding information of wirings and circuits connected to the unnecessary pins in the circuit data from being processed. Laying out the unnecessary pins, and the step of arranging the unnecessary pins is performed based on the information on the unnecessary pins and the information on the wiring and the circuit connected to the unnecessary pins and the wiring connected to the unnecessary pins. 7. The layout method according to claim 5, wherein the layout method is arranged with a circuit. 8. The step of arranging the unnecessary pins,
8. The layout method according to claim 7, wherein when laying out the wiring and the circuit connected to the unnecessary pins, the wiring is arranged in an area where the wiring is not congested.