JP2001308188A - Method for automatic placement and routing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress increase of fringe capacity by relaxing the congested region of routing associated with non-lattice routing. SOLUTION: In a non-lattice routing region 21 after execution of a non-lattice routing step S6, a congested region of routing is extracted, a macro 22 in the vicinity of the congested region of routing is set as a designation macro of a moving object, peripheral region 24 of the designation macro 22S is divided into eight sub-regions, a decision is made for each sub-region whether a macro other than the designation macro 22S is present or not, an empty region 25 is generated in the congested region by moving the designation macro 22S to a sub-region where other macro is not present, and a modification is made to a routing having an interval sufficient for avoiding the effect of fringe capacity using the empty region 25 according to an optimization step S7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an automatic placement and routing method, and more particularly, to an automatic placement and routing method in a layout design of a semiconductor integrated circuit by computer aided design (CAD).

[0002]

2. Description of the Related Art Along with the recent miniaturization of a manufacturing process for achieving high functionality and high integration of a semiconductor integrated circuit (LSI), the problem of a reduction in speed due to the influence of wiring load capacitance has become remarkable. It is starting to appear. For example,
The rise time in the operation of the transistor, which is the main active element, becomes slower as the load capacitance is larger, which causes a decrease in speed.

Conventionally, many automatic placement and routing methods for automatically placing and routing in this type of LSI layout design by CAD have been developed. A major challenge in layout design is how to achieve a desired layout, typically an area minimization, the most important of which is to minimize the wiring area as much as possible.

The wiring methods used in the automatic placement and routing methods developed so far are roughly classified into a grid wiring method and a non-grid wiring method.

The former grid-type wiring method is disclosed in J. Sawcup, “Fast Maze Router”, Proceedings of the 15th Design Automation Conference (J. Soukup, “Fast Maz”
e Router ", Proc. 15th Design
n Automation Conference),
As disclosed in pages 100 to 102, 1978, a grid is defined in advance in a region that can be used as a wiring based on a design standard, and the grid is used as a wiring path to define a circuit to be placed and routed. This is a method of arranging wiring patterns connecting a plurality of functional blocks on the lattice.

[0006] The latter non-grid type wiring method is disclosed in W.K. Heins, W.C. Sansen, H .; Bake, "Array Extension Algorithm for General Path Problems with Guaranteed Solutions," Proceedings of the 17th Design Automation Conference (W. Heyns, W. Sanse)
n, and H .; Bake, “Fast Maze R
outer ", Proc. 17th Design A
automation Conference), 24th
As disclosed on pages 3-249, 1980,
This is a method in which a wiring path of a wiring pattern connecting a plurality of functional blocks is determined so as to satisfy a design standard without defining the grid.

The grid-type wiring method generates wiring patterns on a grid that satisfies the design criteria, so that short-circuiting of the wiring does not occur, so that the wiring design can be completed in a relatively short time even in a large-scale LSI. There is. On the other hand, in the non-lattice type wiring method, since wiring can be performed in consideration of the limit of the design standard, high-density wiring can be performed, and therefore, the wiring area can be reduced.

However, the grid-type wiring method requires a large wiring area. Therefore, when applied to a highly integrated LSI, the number of wirings, that is, a wiring area corresponding to an increase in the number of nets is insufficient. Therefore, there is a disadvantage that wiring of all nets cannot be completed. On the other hand, the non-grid type wiring method does not have a wiring reference position like a grid and has a wide search area for a wiring path, so that it is difficult to determine an optimum wiring path, and processing (wiring) time is long. Disadvantage.

[0009] Japanese Patent Laid-Open No. Hei 6-231 to solve the above disadvantages
The conventional automatic placement and routing method described in Japanese Patent Publication No. 208
Grid-type wiring is performed using a grid-type wiring method. When non-wiring occurs with the progress of placement and routing, non-grid type wiring is performed on the non-wiring using a non-grid type wiring method.

[0010] However, the result of the placement and routing according to the conventional automatic placement and routing method is that the wiring ends up in a non-lattice type wiring, so that the wiring is congested, the wiring interval is narrowed, and a large amount of data is lost in a certain area. Since these wirings are provided, the fringe capacitance, which is the capacitance between these wirings, increases. Due to the increase in the fringe capacitance, there is a problem in that the wiring delay time increases.

Referring to FIG. 6 which shows a flow chart of a conventional automatic placement and routing method, the conventional automatic placement and routing method first places a functional block of a circuit to be placed in step S1, and then in step S2. Grid wiring is performed by a grid wiring method. In the determination processing of step S3, it is determined whether or not unwired remains. If unwired remains, in step S4, the wiring is peeled off and rewired. If there is no unwired, the process ends.

As a result of the wiring stripping and rewiring in step S4, it is again determined in step S5 whether or not unwiring remains. If unwiring remains, non-grid wiring is performed by a non-grid wiring method in step P6. .

Once again, in the determination process of step P7, it is determined whether or not unwired remains. If unwired remains, the process returns to the placement step of step S1, and if there is no unwired, the automatic placement and routing ends.

Referring to FIG. 7, which is a layout diagram showing an example of a placement and routing result of the conventional automatic placement and routing method, in this prior art, the wiring is completed by non-lattice type wiring.
As shown in this figure, the wirings are congested, and the wiring distance d, which is the distance between the wirings 11 arranged so as to deviate from the lattice 10, is as narrow as the design reference distance D. Many wirings 11 are provided. As a result, the fringe capacitance, which is the capacitance between wirings, increases. The VIA 14 shown in this figure is a through connection terminal that connects the upper layer wiring and the lower layer wiring to each other.

Referring to FIG. 8, which schematically shows the fringe capacitance by comparing each of the lattice type wiring and the non-lattice type wiring, the fringe unit capacitance with the wiring thickness T and width W being Co, length L, Assuming the wiring interval d, the fringe capacitance Cf is expressed by the following equation. Cf = Co · L / d (1) As described above, when the length L is constant, the fringe capacitance Cf is a wiring interval d. And becomes larger as the wiring interval d becomes smaller. Assuming that the stray capacitance other than the fringe capacitance is Ca and the resistance of the wiring is R, the time constant τ is represented by the following equation. τ = R (Ca + Cf) (2) That is, the delay time depending on the time constant τ increases as the fringe capacitance Cf increases. This is a proportional relationship.

Substituting equation (1) into equation (2) yields a time constant τ
Is represented by the following equation. τ = R (Ca + Co · L / d) (3) That is, if the length L is constant, the delay time depending on the delay time τ is In inverse proportion to the wiring distance d, the wiring distance d increases as the wiring distance d decreases.

In the figure, if the thickness T, width W, and length L of the wiring are the same, from equation (1), the fringe capacitance Cfn of the non-lattice-type wiring is expressed as follows: Smaller than the fringe capacitance Cf
g. From the equation (3), if the wiring resistances R are the same, the delay time corresponding to the wiring interval dn of the non-lattice type wiring is larger than the delay time due to the wiring distance dg of the lattice type wiring.

[0018]

In the above-described conventional automatic placement and routing method, the wiring is completed by non-lattice type wiring, so that the wiring is congested, the wiring interval is narrowed, and more wiring is required for a certain area. In this case, since the fringe capacitance, which is the capacitance between these wirings, increases, the wiring delay time increases.

An object of the present invention is to provide an automatic placement and routing method which solves the above-mentioned drawbacks, alleviates a congested area of wiring due to the implementation of non-grid type wiring, and suppresses an increase in fringe capacitance.

[0020]

According to a first aspect of the present invention, there is provided an automatic placement and routing method, comprising the steps of arranging a plurality of functional blocks having a predetermined function and connecting the functional blocks on a predefined grid in accordance with required connection information. In the automatic placement and routing method for performing non-grid-type wiring based on only design criteria without defining the grid after the grid-type wiring for generating a wiring pattern for use in the non-grid-type wiring area after performing the non-grid-type wiring, Then, a wiring congested area where the wiring is congested and the delay time becomes extremely large due to the influence of the fringe capacitance between the wirings is found, and a first macro arranged near the wiring congested area is designated as a movement designation macro. Then, a plurality of divided regions in which peripheral regions of the first macro are predetermined are generated, and each of the plurality of divided regions is a macro other than the first macro. Determining the presence or absence of 2 macro said to divided areas having no second macro first
A free area is generated in the wiring congested area by moving the macro, and the wiring is corrected to a wiring having a sufficient wiring interval that can avoid the influence of the fringe capacitance between the wirings by using the free area. is there.

According to a second aspect of the present invention, there is provided an automatic placement and routing method for arranging a plurality of function blocks having a predetermined function and then performing wiring for connecting the plurality of function blocks according to requested connection information. Arranging functional blocks for arranging the plurality of functional blocks;
A grid-type wiring step of performing a grid-type wiring for generating a wiring pattern for connection between functional blocks on a grid that satisfies a design criterion according to the connection information; and, as a result of the grid-type wiring step, determining whether or not unwiring remains. A first wiring completion determining step, a wiring peeling rewiring step of peeling off and rewiring the wiring if no wiring remains in the first wiring completion determining step, and a wiring peeling rewiring step As a result, a second wiring completion judging step for judging whether or not unwiring remains, and a plurality of functions for satisfying design criteria without defining a grid when unwiring remains in the second wiring completion judging step A non-lattice-type wiring step of performing non-lattice-type wiring by a non-lattice-type wiring method for connecting blocks, and a non-lattice-type wiring area after the non-lattice-type wiring step is performed Then, a wiring congestion area where the wiring becomes congested and the delay time becomes large due to the fringe capacitance between the wirings is extracted, and a macro arranged near the wiring congestion area is set as a designated macro to be moved. The surrounding area is divided into a plurality of predetermined divided areas, the presence or absence of a macro other than the designated macro is determined for each of the divided areas, and the designated macro is assigned to the divided area where no other macro exists. An optimizing step of generating an empty area in the wiring congested area by moving the wiring, and correcting the wiring to a wiring having a sufficient wiring interval that can avoid the effect of fringe capacitance using the empty area. It is.

The optimizing step according to the second invention is characterized in that the non-lattice-type wiring area, which is all the non-lattice-type wiring areas in the chip, and the macro unplaced area other than the non-lattice-type wiring area A first step of calculating a sparse region area and setting a corresponding target area reduction ratio, and a largest non-lattice-type wiring region among the largest non-lattice-type wiring regions and a largest one among the sparse regions. A second step of extracting a maximum sparse area, a third step of specifying a macro closest to the extracted maximum non-lattice-type wiring area as a specified macro to be moved, and an area surrounding the specified macro. A fourth step of setting a surrounding area, a fifth step of generating a divided area by dividing the surrounding area into eight, and setting an arrangement position for moving the designated macro for each of the divided areas; A sixth step of determining whether or not another macro of the specified macro exists for each of the divided areas; a seventh step of moving the specified macro to the divided area where the other macro does not exist; Correcting the non-lattice-type wiring of the maximum non-lattice-type wiring area to the lattice-type wiring by using a free area in the vicinity of the post-movement free area generated by the movement of the specified macro. Step 8, calculating the optimized non-lattice-type wiring region area, which is the corrected total non-lattice-type wiring region area in the eighth step, and calculating the total non-lattice-type wiring calculated in the first step. A ninth step of calculating the area reduction rate after optimization as compared with the area of the region.

The sixth step may include a step of determining whether another macro exists in each of the eight divided areas, and a step of determining whether another macro exists. A step of moving the position of each of the divided areas in a predetermined manner when another macro exists in all of the eight divided areas in the determining step; It is determined whether there is an area, and if there is a divided area whose position has not moved, the process returns to the step of determining the presence of another macro. If there is no divided area that has not moved, the macro closest to the maximum sparse area extracted in the second step among the macros existing in the divided area is designated as the designated macro A fixed macro redesignating step; determining whether there is a macro that can be designated in the designated macro redesignating step; if the macro can be designated again, returning to the fourth step; If there is no designated macro in the designated macro existence determining step, the designated macro that designates the closest macro that has not been designated yet as the designated macro from the non-lattice type wiring area extracted in the second step. It is determined whether there is a macro that can be designated in the designation step and the designated macro re-designation step. If the macro can be designated again, the process returns to the fourth step. If there is no macro to be designated, the process ends. It may be characterized by having a designated macro existence determining step.

[0024] Further, the seventh step includes the step of:
As a result of the determination in step (a), if there is a divided area where no other macro exists among the eight divided areas, it is determined how many divided areas where this macro does not exist. A step of moving the designated macro to a divided area where no macro exists in the step and the step of judging the number of non-existing divided areas of the other macros in the case where there is only one divided area where no macro exists. When there are a plurality of divided regions where no macro exists in the step of determining the number of non-existent divided regions of the other macro, the closest one of the plurality of divided regions to the largest sparse region extracted in the second step A second designated macro moving step of moving the designated macro to the divided area.

Further, the ninth step is to calculate an optimized non-lattice-type wiring region area, which is the entire non-lattice-type wiring region area after the optimizing process, and calculate the non-lattice-type wiring region area calculated in the first step. The area reduction rate after optimization is obtained by comparing with the area of the non-lattice type wiring region, and it is determined whether or not the area reduction rate after optimization satisfies the target area reduction rate. The area reduction ratio after the optimization does not satisfy the target area reduction ratio.
It is determined whether or not the wiring has been corrected in accordance with the movement of the specified macro arrangement position in the step (3). If the wiring has been corrected in accordance with the movement of the specified macro arrangement position in the third step, the processing proceeds to the second step. If the return wiring correction determining step differs from the wiring correction associated with the movement of the designated macro placement position in the third step in the wiring correction determining step, the macro is a macro designated immediately before the currently moved macro. The method may further include a designated macro re-designating step before designating a macro whose arrangement position has not been moved as the designated macro and returning to the fourth step.

[0026]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

In the automatic placement and routing method according to the present embodiment, as described in the prior art, after the grid-type wiring for wiring to a predefined grid, a non-grid-type wiring based on only the design criteria without defining the above-mentioned grid is provided. In the non-lattice-type wiring area after performing the wiring, the wiring is congested, and a wiring congestion area in which the delay time is extremely delayed due to the influence of the fringe capacitance between the wirings is found, and the wiring congestion area is located near the wiring congestion area. The specified macro is set as a designated macro to be moved, and the surrounding area of the designated macro is divided into a prescribed number to generate a prescribed number of divided areas. The presence or absence of the macro is determined, and the designated macro is moved to the divided area where no other macro exists, thereby generating an empty area in the wiring congestion area. It is characterized in that to fix the wires with sufficient wiring space which can avoid.

Next, referring to FIG. 1 which shows the embodiment of the present invention in the same manner as in FIG. The automatic placement and routing method according to the embodiment includes a step S1 of arranging a plurality of functional blocks having a predetermined function common to the related art, and a step of arranging the functional blocks on a lattice satisfying a design standard in accordance with required connection information. A grid-type wiring step S2 for generating a connection wiring pattern, a wiring completion determination step S3 for determining whether or not a non-wiring remains as a result of the step S2, and if no wiring remains in the step S3, the wiring is peeled off and re-wired. Wiring peeling and rewiring step S4, a wiring completion determining step S5 for determining whether or not unwiring remains as a result of step S4, and an unwiring remaining in step S5 In addition to the non-lattice-type wiring step S6 of performing non-lattice-type wiring by a non-lattice-type wiring method for connecting a plurality of functional blocks so as to satisfy a design standard without defining a lattice, In the non-lattice type wiring area after the execution, a wiring congestion area where the wiring is congested and the delay time is increased due to the fringe capacitance between the wirings is extracted, and a macro arranged in the vicinity of the wiring congestion area is extracted as a movement target. It is set as a designated macro, and the surrounding area of the designated macro is divided into eight to generate eight divided areas. For each of the divided areas, it is determined whether or not another macro other than the designated macro exists. By moving a designated macro to a non-existing divided area, an empty area is generated in the wiring congested area, and a wiring having a sufficient wiring interval that can avoid the influence of fringe capacitance using the empty area. With optimized step S7 to correct.

The optimizing step S7 is to determine the area of the entire non-lattice-type wiring area, which is all the non-lattice-type wiring areas in the chip, and the area of the macro non-arranged area (hereinafter referred to as the sparse area) other than the non-lattice-type wiring area. Step S71 of calculating and setting the corresponding target area reduction ratio, step S72 of extracting the largest non-lattice type wiring region and the largest sparse region which is the largest sparse region, and the closest from the extracted maximum non-lattice type wiring region Step S73 of designating the macro as a designated macro to be moved, step S74 of setting a surrounding area that is a surrounding area of the designated macro, and dividing the surrounding area into eight to generate a divided area. A step S75 of setting an arrangement position at which the designated macro is moved; a step S76 of judging whether or not another designated macro exists for each of the divided areas; Step S77 of moving the designated macro to the divided area where the b does not exist, and wiring of the maximum non-lattice type wiring area using the free area near the free area after the movement caused by the movement of the designated macro. Is corrected to a grid wiring, and the total non-grid wiring area area after correction in step S78, that is, the optimized total non-grid wiring area is calculated, and the total non-grid calculated in step S71 is calculated. Calculating an area reduction ratio in comparison with the area of the pattern wiring region.

Next, the outline of the operation of the present embodiment will be described with reference to FIG. 1. First, steps S1 to S6 perform the same processing as the conventional one. That is,
In step S1, the functional blocks of the circuit to be arranged are arranged, and in step S2, lattice wiring is performed by a lattice wiring method. In the determination processing of step S3, it is determined whether or not unwired remains. If unwired remains, in step S4, the wiring is peeled off and rewired. If there is no unwired, the process ends. As a result of the wiring stripping and rewiring in step S4, it is determined again in step S5 whether or not unwiring remains. If unwiring remains, non-grid wiring is performed in step S6 by a non-grid wiring method.

In the non-lattice-type wiring generated as a result of the non-lattice-type wiring step S6, there are places where the wiring is congested, the interval between the wirings becomes short, the fringe capacitance between the wirings becomes large, and the delay time becomes extremely long. Occurs. In particular, as the process becomes finer, the effect becomes larger.

Next, an optimization step of step S7 is performed. First, in step S71, the area of all the non-lattice type wiring regions in the chip and the area of the region where no macro is arranged except the non-lattice type wiring regions, that is, the sparse region area, are calculated.
At this time, a target area reduction rate is set to determine the area of the calculated non-lattice type wiring region area.

Next, in step S72, the largest non-lattice type wiring area and the largest maximum sparse area among the sparse areas are extracted.

Next, in step S73, a macro closest to the extracted maximum non-lattice type wiring area is designated as a designated macro.

Referring to FIG. 3 showing a layout selection example of a macro selection from the maximum non-lattice type wiring area, FIG. The illustrated non-lattice type wiring area 21, the macro 22 including the designated macro 22S, the upper AL wiring layer 12 having the horizontal AL wiring disposed thereon, and the lower AL wiring layer having the vertical AL wiring disposed therein 13 and a through connection terminal (VIA) 14 for interconnecting the upper and lower wirings,
In this example, among the plurality of macros 22, the lower macro 22 of the maximum non-lattice-type wiring area 21 is designated as a designated macro 22S to be moved (details will be described later).

Next, in step S74, the designated macro 22
A surrounding area 24 around S is set. The range of the peripheral region 24 is set in advance according to the area of the designated macro 22S and the number of terminals.

Next, in step S75, the set surrounding area 24 is divided into eight as described later, and divided areas 241-2.
48 is set, and the arrangement position of the movement destination of the designated macro 22S to be moved for each of the divided areas is set.

Next, in step S76, the divided area 241
It is determined whether there is another macro in each area of .about.248.

Next, in step S77, the divided area 241
The designated macro 22S is moved to a divided area where no other macro exists among 248.

Next, in step S78, the designated macro 22
A wiring pattern is generated on the grid for the non-lattice type wiring of the maximum non-lattice type wiring area 21 by using a free area near the post-movement free area, which is a free area generated by the movement of the macro 22S, for the wiring accompanying the movement of S. Correct it to a lattice type wiring.

Thereafter, in step S79, the corrected total non-lattice type wiring area is calculated, and the total non-lattice type wiring area is compared with the total non-lattice type wiring area calculated in step S71. That is, the area reduction rate after optimization is calculated. The value of the area reduction rate after the optimization is determined in step S7.
It is determined whether it is smaller than the target area reduction rate set in step 1.
If the target area reduction rate is larger than the target area reduction rate, the process returns to step S72, and steps S72 to S79 are repeated until the optimized area reduction rate falls below the target area reduction rate. If the area reduction rate after optimization has reached the target reduction rate, the automatic placement and routing is terminated.

Referring to FIG. 2 which is a layout diagram showing an example of the automatic placement and movement of macros in a circuit to be subjected to the automatic placement and routing method of this embodiment, an example of the designation order of macros to be placed and moved. To explain more specifically,
FIG. 2A shows a layout after wiring in steps S <b> 1 to S <b> 6, and includes a non-lattice type wiring area 21, three macros 22 </ b> A, 22 </ b> B, 22 </ b> C to be arranged, and a maximum sparse area 23. Also, a surrounding area 24B of a macro 22B described later.
(Shown by a dotted line) and a free area 25 which is a free divided area.

For convenience of explanation, the target area reduction rate is:
It is assumed that the area reduction ratio is set so that all (100%) non-grid type wirings can be corrected to grid type wirings.

In step S72 described above, the non-lattice wiring area 21 is extracted as the maximum non-lattice wiring area, and the maximum sparse area 23 is extracted as the maximum sparse area.

In step S73, the macro 22A closest to the extracted maximum non-grid type wiring area 21 is designated as a designated macro to be moved (hereinafter designated macro 22A etc.).

Next, in step S74, the designated macro 22
A surrounding area 24A, which is an area surrounding A, is set. In step S75, the set surrounding area 24A is divided into eight parts. In step S76, whether another macro exists in each of the divided areas 241A to 248A. As a result of judging whether
Another macro exists in all of the divided areas 241A to 248A of the macro 22A. Therefore, the macro 22B close to the maximum sparse area 23 among the macros existing in the divided areas 241A to 248A of the macro 22A is designated again as the designated macro 22B. However, since there are other macros in all of the divided areas 241B to 248B of the designated macro 22B, the macro 22C closer to the maximum sparse area 23 among the macros existing in the divided areas 241B to 248B is designated macro 22C.
Designate as C.

As shown in FIG. 2A, there is a divided area (empty area) 25C in which no other macro exists in the peripheral area 24C of the designated macro 22C.
The location of the designated macro 22C is
Move to 5C. If the non-lattice-type wiring area still remains due to the wiring correction accompanying the movement of the placement position of the macro 22C, the macro 2C specified before the macro 22C is specified.
2B is re-designated as the designated macro 22B.

Since the position of the macro 22C has been moved,
In the surrounding area 24B of the designated macro 22B, FIG.
As shown in (B), a free area 25B, which is a divided area where no macro exists, is created. The arrangement position of the macro 22B is moved to the empty area 25B. If the non-lattice-type wiring area remains even after the wiring correction accompanying the movement of the arrangement position of the macro 22B, the macro 22A specified before the macro 22B is specified again as the specified macro 22A.

In the surrounding area 24A of the designated macro 22A, as shown in FIG. 2C, there is a free area 25A which is a divided area where no other macro exists. This free space 2
The arrangement position of the macro 22A is moved to 5A. FIG. 2 (D)
As shown in (2), all the wirings in the non-lattice type wiring area are corrected to the lattice type wiring by the wiring correction accompanying the movement of the arrangement position of the macro 22A, and the non-lattice type wiring area becomes the lattice type wiring area 26.

As described above, the designation order of the macros is as follows: macro 22A, macro 22B, macro 22C, macro 22B,
The macros 22A are specified in order. If macro 22
If the non-lattice type wiring area remains due to the movement of the arrangement position of A, the largest non-lattice type wiring area in the chip is extracted, and the macro closest to this largest non-lattice type wiring area is designated. The placement position movement is repeated. When there is no macro to be moved or no non-lattice-type wiring area, the wiring correction flow by moving the macro placement position ends.

Next, the details of the operation of this embodiment will be described with reference to FIGS. 4 and 3 which show the details of the processing of step S7 in a flowchart.
Then, the area of the entire non-lattice type wiring region, which is the area of all the non-lattice type wiring regions in the chip, and the area of the sparse region are calculated. The target area reduction rate of the non-lattice-type wiring area is set according to the size of the non-lattice-type wiring area calculated at this time.

Next, in step S72, the largest non-lattice type wiring area 21 having the largest non-lattice type wiring area, such as the non-lattice type wiring area 21, is extracted. In addition, a maximum sparse area 23 which is a non-arranged area of a macro other than the non-lattice type wiring area 21 is calculated.

Next, in step S73, step S72
The macro closest to the maximum non-lattice-type wiring area 21 extracted in the above is designated as the designated macro 22S.

Next, in step S74, a surrounding area 24S of the designated macro is set. The range of the peripheral region 24S is set in advance according to the area of the macro and the number of terminals.

Next, in step S75, the set surrounding area 24S is divided into eight, divided areas 241S to 248S are set, and the destination position of the designated macro 22S to be moved for each divided area is set.

Referring to FIG. 5, which shows a method of specifying a macro and moving the positions of a macro setting area and a macro division area, as shown in FIG. 5A, a surrounding area 24S of a specified macro 22S is divided into eight parts. Then, the divided areas 241S to 248S are set. The destination position of the designated macro 22S to be moved for each of the divided areas 241S to 248S is set.

Next, in step S761, the divided area 24
It is determined whether or not another macro exists inside each of 1S to 248S. However, the maximum non-grid type wiring region 21
Is excluded from the judgment target.

First, if another macro exists in all of the divided areas 241S to 248S, the process proceeds to step S762, as shown in FIG.
Each position of 8S is moved in a predetermined manner. In the example of this figure, the divided areas 241S to 248S are moved clockwise.

Next, in step S763, it is determined whether or not the movement of the positions of all the divided areas has been completed, that is, whether or not there is a divided area whose position has not been moved.

If the result of determination in step S763 is that there is a divided area whose position has not moved, the flow returns to step S761, and if not, the flow proceeds to step S764. The macro closest to the maximum sparse area 23 extracted in S72 is designated as the designated macro.

Next, in step S765, step S7
It is determined whether there is a macro that can be specified at 64.
If a macro has been specified in step S765, the process returns to step S74. Step S if there is no macro to be specified
Proceed to 766, and in this step S766, step S72
The macro closest to the non-lattice-type wiring area 21 extracted in step 1 and which has not been specified yet is specified as the specified macro.

Next, in step S767, step S7
At 66, it is determined whether there is a macro that can be designated.

If a macro can be specified in step S767, the process returns to step S74, and if there is no macro to be specified, the process ends.

If it is determined in step S761 that there is a divided area where no other macro exists, the flow advances to step S771 to determine how many divided areas where no macro exists.

If it is determined in step S771 that there is only one divided area in which no macro exists, the flow advances to step S772. In step S772, the designated macro is moved to a divided area in which no macro exists. If there are a plurality of divided regions where no macro exists, in step S773, the largest sparse region 23 extracted in step S72 among the plurality of divided regions.
Move the specified macro to the divided area closest to.

The wiring connected to the moved designated macro is also moved according to the processing of steps S772 and S773, and at this time, the non-lattice type wiring is corrected to the lattice type wiring (step S7).
8).

Next, in step S791, the area of all the non-lattice type wiring regions after the optimization processing, that is, the area of the non-lattice type wiring region after optimization is calculated, and the non-lattice type wiring region area obtained in step S71 is calculated. Then, the post-optimization area reduction rate is obtained by comparing with the above, and it is determined whether the post-optimization area reduction rate reaches the target area reduction rate.

If the area reduction rate after optimization does not reach the target area reduction rate, the flow advances to step S792 to determine in step S792 whether the wiring has been corrected due to the movement of the designated macro arrangement position in step S73. to decide.

As a result of the determination in step S792,
If it is different from the wiring correction associated with the movement of the specified macro arrangement position in 73, the process advances to step S793, and in this step S793, the macro designated immediately before the currently moved macro, that is, the arrangement position is moved. The macro not specified is specified as the specified macro, and the process returns to step S74.

As a result of the determination in step S792,
If it is a wiring correction associated with the movement of the specified macro arrangement position in 73, the process returns to step S72. Step S79
If the area reduction rate after optimization satisfies the target reduction rate in the comparison of 1, the wiring is terminated.

As described in the background art, in a region where wirings are congested such that non-lattice type wirings exist, fringe capacitance generated between the wirings is large. When a plurality of wiring layers are provided, a similar problem exists between the upper and lower wiring layers. With the further progress of miniaturization of the process in the future, the corresponding fringe capacitance will increase due to the reduction of the wiring interval and the interval between the upper and lower wiring layers, and the problem that the delay time will become extremely large due to the effect will occur. .

Generally, the wiring data after the completion of the placement and routing includes a region where the wiring is congested and a region where the wiring is not.
Basically, the wiring is congested near the center of the chip and a non-lattice type wiring region is easily generated, and the wiring becomes sparser as going to the outside of the chip. In particular, macros are hardly arranged at the corners of the chip, and there are many empty areas where no wiring is arranged.

In the present embodiment, by utilizing the above fact, the arrangement position of the macro in the vicinity of the non-lattice type wiring area can be moved to create an empty area in the non-lattice type wiring area, thereby alleviating the congestion of the wiring. Therefore, it is possible to prevent an increase in fringe capacitance between the wirings, and to prevent an excessive increase in delay time of the wiring portion.

Referring again to the equations (1) to (3) described in the prior art, if the fringe unit capacitance with the wiring thickness T and width W is Co, length L, and wiring interval d, the fringe capacitance Cf is represented by equation (1). Cf = Co · L / d (1) If the stray capacitance other than the fringe capacitance is Ca and the resistance of the wiring is R, the time constant is τ is expressed by equation (2). τ = R (Ca + Cf) (2) When the equation (1) is substituted into the equation (2), the time constant τ becomes the equation (3) It is represented by τ = R (Ca + Co · L / d) (3) As shown by the equation (1), the fringe capacitance Cf is a constant length L. Then, it is inversely proportional to the wiring interval d, and becomes larger as the wiring interval d becomes smaller.

As shown by the equation (2), when the resistance R and the floating capacitance Ca are constant, the delay time τ increases as the fringe capacitance Cf increases.

That is, as shown in the equation (3), when the length L is constant, the delay time dependent on the delay time τ is inversely proportional to the wiring interval d, and increases as the wiring interval d decreases. Become.

A specific example of an actual chip will be described. The fringe capacitance Cf1 when the wiring interval d is 0.8 μm is 2.3.
4e ^-16 (F / μm), the wiring interval d is 1.6 μm
In this case, the fringe capacitance Cf2 is 1.27e ^-16 (F /
μm). In this case, the fringe capacitance Cf is increased to 1.07 e ^-16 (F
/ Μm), which is reduced by a factor of about 46%, ie to about 54% of the original capacity.

Assuming that (Ca + Cf) is C, the delay time τ
Becomes smaller by (C−0.54Cf1) / C.

Further, the placement and routing method of the present embodiment can be applied to a case in which unrouted wiring remains, and placement and routing can be performed automatically without manual intervention.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made. For example, if the number of divisions around the specified macro is 8
Instead of this, the number of divisions can be set to an arbitrary number such as 6 or 12, without departing from the gist of the present invention.

[0081]

As described above, according to the automatic placement and routing method of the present invention, in the non-lattice type wiring area after the non-lattice type wiring step is performed, the wiring is congested and the delay time is increased due to the fringe capacitance between the wirings. A possible wiring congestion area is extracted, a macro arranged near the wiring congestion area is set as a designated macro to be moved, and a surrounding area of the designated macro is divided into a plurality of predetermined divided areas, Determining the presence or absence of a macro other than the specified macro for each of the divided areas, and generating an empty area in the wiring congestion area by moving the specified macro to a divided area where no other macro exists; An optimization step of using the vacant area to correct the wiring to a wiring having a sufficient wiring interval capable of avoiding the effect of the fringe capacitance. Move the location position, create an open area in the non-grid-type interconnect region, since it is possible to reduce congestion of wires, to prevent an increase in fringe capacitance between the interconnects,
There is an effect that an extreme increase in the delay time of the wiring portion can be prevented.

Further, the placement and routing method of the present embodiment can be applied to a case where unrouted portions remain, and has an effect that placement and routing can be performed automatically without manual intervention.

[Brief description of the drawings]

FIG. 1 is a flowchart showing one embodiment of the automatic placement and routing method of the present invention.

FIG. 2 is a layout diagram illustrating an example of automatic macro placement and movement in a circuit to be subjected to the automatic placement and routing method according to the embodiment;

FIG. 3 is a layout diagram showing an example of selection and designation of a macro from a maximum non-lattice type wiring area in a circuit to be subjected to the automatic placement and routing method according to the embodiment;

FIG. 4 is a flowchart showing details of an automatic placement and routing method according to the embodiment.

5 is a diagram showing a method of moving a position of a macro designation, a setting region around the macro, and a division region of the macro in FIG. 2;

FIG. 6 is a flowchart illustrating an example of a conventional automatic placement and routing method.

FIG. 7 is a layout diagram showing an example of a non-lattice type wiring in a circuit to be subjected to the automatic placement and routing method.

FIG. 8 is a schematic diagram schematically showing a comparison between fringe capacitances of a lattice type wiring and a non-lattice type wiring.

[Explanation of symbols]

10 Lattice 11 Wiring 12, 13 AL Wiring Layer 14 VIA 21 Non-Grid Wiring Area 22, 22A, 22B, 22C, 22S Macro 23 Maximum Sparse Area 24, 24A, 24B, 24C Surrounding Area 25, 25A, 25B, 25C Free Area 26 Lattice type wiring regions 241-248, 241A-248B, 241C-24
8C, 241S to 248S divided area

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B046 AA08 BA05 BA06 5F064 AA04 DD07 DD12 DD14 DD20 EE03 EE12 EE14 EE15 EE22 EE26 EE27 EE43 EE47 EE58 HH06

Claims (7)

[Claims] After arranging a plurality of functional blocks having a predetermined function, the grid is defined after grid-type wiring for generating a wiring pattern for connection between the functional blocks on a grid defined in advance according to required connection information. In the automatic placement and routing method of performing non-grid type wiring based only on the design criteria without performing, in the non-grid type wiring area after performing the non-grid type wiring,
A wiring congestion area where the wiring is congested and the delay time can be extremely large due to the influence of the fringe capacitance between the wirings is found, and a first macro arranged near the wiring congestion area is designated as a movement designation macro, Generating a plurality of divided regions in which peripheral regions of the first macro are determined in advance; and for each of the plurality of divided regions, the presence or absence of a second macro other than the first macro And generating an empty area in the wiring congested area by moving the first macro to a divided area where the second macro does not exist, and using the empty area to avoid the influence of fringe capacitance between wirings An automatic placement and routing method, wherein the wiring is corrected to a wiring having a sufficient wiring interval. 2. An automatic placement and routing method for arranging a plurality of function blocks having a predetermined function and then performing wiring for connecting the plurality of function blocks in accordance with requested connection information, wherein the plurality of function blocks are arranged. A step of arranging the function blocks; a step of performing a grid-type wiring for generating a wiring pattern for connection between the function blocks on a grid satisfying the design criteria according to the connection information; A first wiring completion determination step of determining whether or not wiring remains; a wiring peeling and rewiring step of peeling off wiring and performing rewiring if unwired remains in the first wiring completion determination step; A second wiring completion determining step of determining whether or not unwiring remains as a result of the wiring peeling and rewiring step; A non-grid type wiring step of performing a non-grid type wiring by a non-grid type wiring method for connecting between a plurality of functional blocks so as to satisfy a design standard without defining a grid when unwired remains in the line completion determination step, In the non-lattice-type wiring area after the non-lattice-type wiring step is performed, a wiring congestion area in which the wiring is congested and the delay time can be increased by the fringe capacitance between the wirings is extracted, and the wiring congestion area is arranged near the wiring congestion area. Is set as a designated macro to be moved, the surrounding area of the designated macro is divided into a plurality of predetermined divided areas, and presence / absence of a macro other than the designated macro exists for each of the divided areas. Is determined, and a designated macro is moved to a divided area where no other macro exists, thereby generating an empty area in the wiring congested area, and using the empty area to influence the fringe capacitance. An optimization step of correcting the wiring to a wiring having a sufficient wiring interval capable of avoiding the problem. 3. The automatic placement and routing method according to claim 1, wherein the plurality of divided areas are eight divided areas. 4. The method according to claim 1, wherein the optimizing step comprises: determining a non-lattice-type wiring region area which is all non-lattice-type wiring regions in the chip;
A first step of calculating a sparse region area which is an unplaced region of the macro other than the non-lattice type wiring region and setting a corresponding target area reduction rate; A second step of extracting the largest sparse area, which is the largest of the grid-type wiring area and the sparse area, and a third step of specifying a macro closest to the extracted maximum non-grid-type wiring area as a designated macro to be moved And a fourth step of setting a surrounding area that is a surrounding area of the designated macro; and dividing the surrounding area into eight to generate a divided area, and moving the designated macro for each of the divided areas. A fifth step of setting an arrangement position to be set; a sixth step of determining whether or not another macro of the designated macro exists for each of the divided areas; and a step of determining whether the other macro exists. A seventh step of moving the designated macro to the divided area, and using the empty area near the empty area after the movement caused by the movement of the designated macro, for the wiring accompanying the movement of the designated macro, An eighth step of correcting the non-lattice type wiring of the region to the lattice type wiring, and calculating an optimized total non-lattice type wiring area area which is the total non-lattice type wiring area area after the correction in the eighth step A ninth step of calculating an area reduction rate after optimization by comparing the area with the entire non-lattice type wiring region area calculated in the first step. Wiring method. 5. The method according to claim 6, wherein the sixth step is a step of determining whether another macro exists inside each of the eight divided areas, and the presence of the other macro. A step of moving the position of each of the divided areas in a predetermined manner when another macro exists in all of the eight divided areas in the determining step; It is determined whether or not there is an area, and if there is a divided area whose position has not moved, the process returns to the step of determining the presence of another macro. If there is no divided area that has not been moved, the designation of designating the macro closest to the maximum sparse area extracted in the second step among the macros existing in the divided area as the designated macro A macro re-designating step; determining whether there is a macro that can be designated in the designated macro re-designating step; and, if the macro can be designated again, returning to the fourth step; If there is no macro to be specified in the macro existence determination step, a specified macro re-designated as the specified macro, which is the closest macro that has not yet been specified from the non-lattice-type wiring area extracted in the second step Determining whether there is a macro that can be designated in the designated macro re-designating step, returning to the fourth step if the macro can be designated again, and terminating if there is no designated macro 5. The automatic placement and routing method according to claim 4, further comprising a macro existence determining step. 6. The method according to claim 7, wherein, as a result of the determination in the sixth step, if there is a divided area in which no other macro exists among the eight divided areas, the number of divided areas in which this macro does not exist is determined. If there is only one divided area where no macro exists in the step of determining the number of non-existent divided areas of another macro, and the step of determining the number of non-existent divided areas of another macro, the macro does not exist. In the first designated macro moving step of moving the designated macro to the divided area, and in the step of determining the number of nonexistent divided areas of the other macro, if there are a plurality of divided areas where no macro exists, among the plurality of divided areas, The method according to claim 4, further comprising a second designated macro moving step of moving the designated macro to a divided area closest to the maximum sparse area extracted in the second step. Automatic placement and routing method. 7. The ninth step is to calculate an optimized non-lattice-type wiring region area, which is an area of all non-lattice-type wiring regions after the optimization process, and to calculate the non-lattice-type wiring region area calculated in the first step. The area reduction rate after optimization is obtained by comparing with the area of the lattice wiring region, and it is determined whether or not the area reduction rate after optimization satisfies the target area reduction rate. If so, the process is terminated. An area reduction ratio determining step; and a determination result of the area reduction ratio determining step, when the optimized area reduction ratio does not satisfy the target area reduction ratio, the position of the designated macro is moved in the third step. It is determined whether the wiring correction has been made, and if the wiring correction has been made due to the movement of the arrangement position of the designated macro in the third step, the wiring correction determining step returns to the second step. In the above If it is different from the wiring correction accompanying the movement of the specified macro placement position in step 3, specify the macro that was specified immediately before the currently moved macro and whose placement position has not been moved as the specified macro. 5. The automatic placement and routing method according to claim 4, further comprising a step of re-designating the designated macro before returning to the fourth step.