JP2967762B2 - Circuit layout method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit layout method.

[0002]

2. Description of the Related Art In the design of a semiconductor integrated circuit, it is necessary to shorten the delay time of a path having the largest signal propagation delay time among signal paths. Here, the path is a signal path composed of continuous nets (wirings connecting cells).

In the conventional method, in order to reduce the delay time, first, timing analysis is performed after layout design. Next, based on the result of the timing analysis, if there is a timing error, the process returns to the logic design process to correct the circuit. Since the processes of layout design and timing analysis are repeated until the error is eliminated, there is a problem that the design time increases.

As a method of avoiding this problem, there is known a method of obtaining an arrangement result such that a delay time is shortened in an arrangement process of a layout design. FIG. 6 shows a general processing flow of this conventional method.

Referring to FIG. 6, after a logic design process 81, a layout design includes an initialization 82 of a level value L, a timing analysis 83, a tentative arrangement position determination 84, and a level value update 8.
5, including a level value determination 86, a detailed wiring, and a placement process 88, and a timing analysis 89 after the layout design process.
If there is a timing error, the flow returns to the logic design process 81 again to correct the logic.

In this conventional method, when the placement processing is performed, the placement is such that the wiring length of the net constituting the path is shortened so as to be within the delay time (timing constraint) predicted at the time of logic design. Is performed.

However, this conventional method has a problem that timing constraints become severe, and it becomes difficult to keep all timing constraints with high integration.
This is because constraints such as cell arrangement space and wiring space have a trade-off relationship with conditions for minimizing the net wiring length.

As another conventional method, for example, Japanese Patent Laying-Open No. 4-287793 has proposed a method as shown in the flowchart of FIG.

First, a rough arrangement is performed without considering the delay time (step 92).

Next, the delay time is predicted from the arrangement result, and if the required delay time (timing constraint) is not satisfied, the cell is replaced (called "gate replacement") (step 93).

Subsequently, a timing analysis is performed to check for a timing error (step 94).

If the timing error disappears, the detailed arrangement is executed (step 96).

As a result of the timing analysis, if there is an error,
At that time, a process for returning to the logic design is performed.

However, according to this method, in the cell on the path that does not satisfy the timing constraint, the cell replacement processing is improved even if the timing constraint is satisfied by improving the cell arrangement position. The number of cells to be performed is likely to increase, and the degree of integration may deteriorate.

[0015]

As described above,
In the conventional method that considers the delay time due to the restriction on the wiring length of the net, there is a trade-off between the constraints such as the cell layout space and the wiring space and the conditions for minimizing the net wiring length. In addition, there is a problem that it becomes more difficult to comply with all timing constraints as the timing constraints become stricter and the degree of integration becomes higher.

In the conventional method in which the cell replacement is performed after the approximate placement, there is a case where the timing constraint can be satisfied by improving the placement. (Replacement is performed), the cell size tends to be large, the wiring space is reduced, and the wiring performance may be affected.

Accordingly, an object of the present invention is to provide a layout method that solves the above-mentioned problems and reduces the processing time of the entire layout by reducing the number of times of returning to the logical design.

[0018]

In order to achieve the above object, the present invention provides a semiconductor device in which cells of a logic function unit composed of a plurality of transistors are arranged on a base substrate, and the cells are connected by signal wiring. When laying out integrated circuits,
In the arrangement processing, for cells constituting a signal path sequence having no or little delay time margin for a given request of the maximum delay time, the degree to which the delay time margin becomes large and the density increase are taken into consideration. And has a function of automatically selecting a wiring improvement process and a cell replacement process for replacing cells with cells having logically equivalent and different driving capacities.

[0019]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a flowchart showing an outline of the processing according to the embodiment of the present invention. 2 and 3 are flowcharts showing details of the processing procedure shown in FIG.

Referring to FIG. 1, in the layout method according to the embodiment of the present invention, step 2 for initializing level (L) (L = 1), step 3 for timing analysis,
Step 4 for determining the temporary placement position, step 5 for determining whether to perform the placement improvement / cell replacement processing, step 6 for performing the placement improvement / cell replacement processing, step 7 for raising the level by one, It has a step 8 for determining whether or not the maximum value has been reached, a step 9 for performing detailed arrangement, and a step 10 for performing wiring.

Further, as shown in FIGS. 2 and 3, the placement improvement / cell replacement processing 6 mainly includes (a) a step 21 for calculating a virtual wiring length, and (b) a step 22 for performing timing analysis. (C) Step 23 for extracting a critical path (path that does not satisfy timing constraints), and (d) Decrease time T of delay time when moving to all cells on the path.
Step 25 for calculating d, (e) Step 27 for determining whether the maximum value of Td is 0 or more, and (f) Whether a critical path is formed by moving another path passing through the cell g1 having the maximum T. Step 28 of determining whether
(g) a step 30 for determining the gain G for all cells in the destination area; (h) a step 32 for determining whether the maximum gain G is greater than a certain constant C; and (i) a cell having a maximum G. Step 33 of determining whether another path passing through g2 does not become a critical path due to movement;
(j) Means 35 for moving cell g1 and cell g2 and cell g1
Step 36 of updating Td of a cell on a path passing through the cell g2, (k) Step 37 of determining whether a path of interest satisfies a timing constraint, and (l) Processing of all critical paths (M) a step 41 of taking out cells on the path one by one, and (n) a step 43 of calculating a delay time reduction value when converted to a cell having a high driving capability. (o)
Step 44 of performing cell replacement, (p) Step 45 of determining whether the path of interest satisfies the timing constraint, and (q) Step 46 of determining whether all cells on the path have been extracted. Have.

The operation of the embodiment of the present invention will be described with reference to the drawings.

After the completion of the logical design 1, the information is input and the layout is designed.

In step 2, the level L is set to 1.

In step 3, a timing analysis is performed to predict a path delay time.

In step 4, a provisional arrangement position is determined. At this time, either the placement processing considering the timing constraint or the placement processing not considering the timing constraint may be performed. However, from the viewpoint of obtaining an arrangement result that satisfies the timing constraint, which is the main purpose of the layout design in the present invention, it is preferable to perform the placement processing in consideration of the timing constraint.

In step 5, it is determined whether or not to execute the placement improvement / cell replacement. The judgment condition is whether or not the level L is larger than the level L_MOD to be executed. The level L_MOD to be executed is determined either by designation by a designer or automatic determination.

At a low level of the level L, since the provisional arrangement position is rough, there is a large difference between the result of the timing analysis and the timing analysis in the arrangement result when all the levels are executed. For this reason, in the embodiment of the present invention, in order to avoid unnecessary placement improvement or cell replacement, placement improvement / cell replacement is not performed at all levels. However,
It is possible to run at all levels.

If it is determined that the execution has not been performed, the process of step 7 is performed. If it is determined that the execution has been performed (see the YES branch of step 5), in step 6, the placement improvement / cell replacement process is performed.

In step 7, the level L is updated to L + 1.

In step 8, the level L is compared with the designated level L_MMAX. If L is equal to or less than L_MAX, the process returns to step S3.

When the designated level L_MAX is reached (see the YES branch of step 8), the detailed arrangement of step 9 and the wiring processing of step 10 are performed, and the layout design is completed.

Next, a detailed processing flow of the placement improvement / cell replacement processing in step 6 will be described with reference to FIGS.

In step 21, first, virtual wiring lengths of all paths are calculated based on the determined provisional arrangement position.

In step 22, timing analysis is performed to calculate the delay time of each path.

In step 23, a constraint path (critical path) that does not satisfy the timing constraint is extracted. The placement improvement processing and the cell replacement processing are performed on the critical path.

In step 24, one critical path is taken out.

In step 25, for all cells on the critical path, a decrease time Td of the delay time when moving to another placement area is determined. At this time, the arrangement area that can be moved is limited to a minimum rectangular area where another cell connected to the cell is placed. The destination of the cell is within the arrangement area where the delay time is minimized. Sorting is performed in the descending order of the obtained reduction time Td, and the information is stored in the list S1 together with the moving arrangement area information.

At step 26, the cell g1 (the first cell of the list S1) having the largest decreasing time Td is extracted and the list S1 is extracted.
Delete from 1.

In step 27, the reduction time Td of the cell g1 is checked. If Td is 0 or negative (that is, the delay time does not decrease), it is determined that the delay time cannot be reduced by improving the arrangement. Perform replacement processing. If Td is a positive value, step 28 is performed.

In step 28, it is checked whether another path passing through the cell g1 becomes a critical path when the cell g1 is moved to another placement area. If it does not become a critical path, step 30 is performed. If another path becomes a critical path, step 29 is performed.

In step 29, the first cell g1 'in the list S1 is taken out, g1' is deleted from the list S1, and thereafter, the flow proceeds to the judgment processing in step 27.

In step 30, a gain G is obtained for all cells in which the cell g1 is located in the destination area. The gain G is an evaluation function indicating the degree of improvement in the degree of integration caused by moving the cell g1. For example,
A function represented by the following equation (1) can be considered.

G = αgn + βgs + γgp (1)

Here, gn is the number of cuts reduced by the movement of the cell, gs is the cost of the sum of the sizes of the cells in the arrangement area approaching a desired ratio, and gp is the desired ratio of the sum of the number of terminals of the cells in the arrangement area. , Β, γ are constants.

The larger the gain G is, the better the index (ie, the higher the degree of integration) is as a guideline (index).

In step 30, the gains G are sorted in descending order and stored in the list S2.

At step 31, the cell g2 having the maximum gain G is extracted from the list S2 and deleted from the list S2.

In the next step 32, the maximum gain G
And the value of the constant C. The constant C is a numerical value determined by a designer or automatic setting.

If the result of the comparison in step 32 is that the gain G of the cell g2 is larger than the constant C, the cell g2 is selected as the cell to be moved, and the determination processing in step 33 is performed.

On the other hand, when the gain G is equal to or smaller than the constant C (no branch of step 32), the process proceeds to step 34 without improving the arrangement. This is to prevent the result of the provisional arrangement position obtained by the arrangement up to this point from being deteriorated.

In step 33, the selected cell g
2 is moved, it is determined whether another path passing through the cell g2 becomes a critical path. If another path passing through the cell g2 becomes a critical path (no branch in step 33), the maximum gain is determined in step 34. The cell g2 'having G is taken out, and the judgment processing of step 32 is performed. On the other hand, if another path passing through the cell g2 does not become a critical path in step 33, the cells g1 and g2 are moved in step 35. Cell g2 is cell g1
Move to the placement area where was located. In this process, only the cell g1 can be moved if the above-mentioned movement condition is satisfied.

In step 36, the delay time reduction time Td is recalculated and updated for each path passing through the cells g1 and g2.

If it is determined in step 37 that the path of interest is no longer a critical path (that is, the timing constraint is satisfied), step 38 is performed; otherwise, step 25 is performed.

In step 38, it is determined whether or not the above-described processing has been completed for all the critical paths. If the processing has been completed, the process proceeds to step 7 in FIG. Return to

Next, the cell replacement process in steps 41 to 46 will be described.

In step 41, in the cell replacement process, each cell on the path of interest is moved one by one in the signal propagation direction.
Take out one by one.

In step 42, the reduction time of the delay time when the cell taken out in step 41 is replaced with a cell having a high driving capability is obtained.

If it is determined in step 43 that the delay time is reduced, the processing in step 44 is performed.
Step 5 is performed.

In step 44, the cell replacement assumed in step 42 is performed.

In step 45, if the delay time of the path satisfies the timing constraint, the cell replacement processing is terminated and step 24 is performed. Otherwise, the processing of step 46 is performed.

In step 46, it is determined whether or not the above processing has been completed for all cells on the path. If it has been completed, step 24 is performed, and if not, the processing of step 41 is performed.

[0064]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention; The processing of one embodiment of the present invention is the same as that of the embodiment described with reference to FIGS.

FIG. 4 is a diagram for explaining one embodiment of the present invention, and is a diagram showing an example of a placement improvement / cell replacement process.

As described in the above embodiment with reference to FIG. 1, after the logical design 1 is completed, the information is input and the layout is designed. In step 3, a timing analysis is performed to predict a path delay time. In step 4, a provisional arrangement position is determined. In step 5, it is determined whether or not to execute the placement improvement / cell replacement. If it is determined that the process has not been executed, the process proceeds to step 7;

FIG. 4 shows a state where the provisional arrangement positions of the cells 52 to 59 of a certain level L are determined. A broken line 51 indicates an area dividing line, which separates the arrangement area.
A section separated by a vertical line is denoted by Xi, and a section separated by a horizontal line is denoted by Yj. In FIG. 4, X1 to X3,
And sections Y1 to Y4. The arrangement area is represented by a section X and a section Y. For example, the arrangement area where the cells 53 and 54 are located is represented as (X2, Y3).

The critical path extracted in step 24 of FIG. 2 is indicated by a thick line 60 in FIG.

In step 25, a decrease time Td of the delay time when the cell 52, the cell 53, the cell 58, and the cell 59 on the critical path 60 are moved to another arrangement area is obtained. The movable placement area of each cell is the placement area within the minimum rectangle surrounding the placement area where the cell to which the cell is connected is located. Cell 53 is composed of cell 52, cell 5
4. Since the cell 53 is connected to the cell 58, the movable arrangement area of the cell 53 is the smallest rectangular area surrounding the arrangement area where the cell 52, the cell 54, and the cell 58 are located, such as a rectangle 61 shown in FIG. become.

The cell 53 has the placement areas (X1, Y2), (X
1, Y3), (X1, Y4), (X2, Y2), (X
2, Y3) and (X2, Y4). Similarly, Td is obtained for the cells 52, 58, and 59. Although a detailed calculation method of the delay time is omitted here, it is assumed that the maximum Td (> 0) is obtained when the cell 53 is moved to the arrangement area (X1, Y3).

In step 26, the cell 5 having the maximum Td
Remove 3.

At step 27, it is determined that Td is positive.

At step 28, the cell 5
It is determined whether or not another path passing through No. 3 becomes a critical path. If there is a path that becomes a critical path, this movement is not performed, and step 29 is performed.
Step 30 is performed.

In step 30, the gain G of all the cells (only the cell 56 in FIG. 4) in the placement area of the movement destination is obtained. When the gain G of the cell 53 and the gain G of the cell 56 when the cell 53 moves to the arrangement area (X1, Y3) are larger than the constant C, the cell 53 is placed in the arrangement area (X2, Y3).
The cell 56 moves from the arrangement area (X1, Y3) to the arrangement area (X2, Y3), respectively.

The delay time of the critical path 60 can be reduced without deteriorating the arrangement result due to this movement.

In step 36, Td of each cell is updated.

In step 37, if the delay time of the path 60 satisfies the timing constraint, the means 38 is performed. If not, step 25 is performed.

At step 38, it is determined whether or not the processing has been completed for all the critical paths. If the processing has been completed, step 7 is performed, and if not completed, the processing returns to step 24.

In step 25, all cells 5 on the path
Td is calculated for 2,53,58,59.

In step 26, the cell having the maximum Td is extracted, and in step 27, it is determined whether Td is positive. If it is determined to be positive, the same processing as described above is repeated.

When there is a path that cannot satisfy the restriction of the delay time by the arrangement improvement processing so far, the cell replacement processing is performed.

Referring to FIG. 1, a second embodiment of the present invention will be described.

The process is the same as that of the above-described embodiment until the provisional placement position is determined in the provisional placement position determination step 4 and it is determined in step 5 whether to perform the placement improvement / cell replacement. Here, by setting L_MOD = (L_MAX−1), it is possible to perform the same processing as that of executing the layout improvement / cell replacement processing after performing the general layout according to the related art. The arrangement improvement / cell replacement processing is the same processing as in the above embodiment.

The difference between this embodiment and the prior art shown in FIG. 7 is that, in the prior art, only the cell replacement process is performed after the general arrangement, whereas in this embodiment, the arrangement improvement and The point is that the cell replacement processing is performed.

FIG. 5 shows an embodiment of a system configuration for implementing the layout method of the present invention.

In FIG. 5, reference numeral 71 denotes a system bus to which a central processing unit (CPU) 72, a memory 73, a keyboard 74, a printer 75, and a display 76 such as a display are connected. The CPU 72
It has a function of laying out a gate array on a chip based on a program for executing the above steps. The memory 73 stores in advance a program that defines the processing to be performed by the CPU 72 and information necessary to execute the processing, and temporarily stores necessary information during the processing, and stores a layout result. It is stored. The keyboard 74 allows the designer to input the program described above and information necessary for the processing thereof,
This is for instructing the CPU 72 to start execution of the program, or for outputting the layout result to the printer 75 or the display 76.

[0087]

As described above, according to the present invention,
In a timing driven (timing driven) arrangement,
Since the placement improvement process or cell replacement process is automatically selected and placed to reduce the signal delay time, the number of design corrections that have been repeated due to timing errors in the conventional method can be reduced, and the design time can be reduced. It has the effect of being able to.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a process according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating an example of a placement improvement / cell replacement process according to the embodiment of the present invention.

FIG. 3 is a flowchart showing an example of a placement improvement / cell replacement process according to the embodiment of the present invention.

FIG. 4 is a diagram for explaining an arrangement improvement / cell replacement process according to one embodiment of the present invention;

FIG. 5 is a diagram showing a system configuration to which an embodiment of the present invention is applied.

FIG. 6 is a diagram showing a layout process (1) according to the related art.

FIG. 7 is a diagram showing a layout process (2) according to the related art.

[Explanation of symbols]

1, 81, 91 Logic design means 2, 82 Level initialization means 3, 11, 22, 83, 89, 94, 98 Timing analysis means 4, 84 Temporary placement position determination means 5 Placement improvement / cell replacement execution determination means 6 Placement Improvement / cell replacement executing means 7, 85 level adding means 8, 86 level determining means 9, 87, 96 detailed arranging means 10, 88, 97 wiring means 12, 90, 95, 99 timing error determining means 51 area dividing line 52, 53, 54, 55, 56, 57, 58, 59 cell 60 critical path 71 system bus 72 central processing unit (CPU) 73 memory 74 keyboard 75 printer 76 display (display) 92 schematic arrangement means

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-298394 (JP, A) JP-A-6-140514 (JP, A) JP-A-8-306788 (JP, A) JP-A-10- 284612 (JP, A) Japanese Patent Laid-Open No. Hei 10-335467 (JP, A) Toshihiro Akiyama and two others, "High-performance ASIC layout technology", Toshiba Review, Toshiba Corporation, June 1, 1995, Vol. 50, No. 6, p. 460-464 (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 17/50 H01L 21/82

Claims (4)

(57) [Claims] 1. A method of arranging cells of a logic function unit composed of a plurality of transistors on a base substrate and arranging the cells in a layout process of a semiconductor integrated circuit connecting the cells by signal wiring. No delay time margin for the requested maximum delay time requirement, or for cells constituting a signal path sequence, taking into account the degree of increase in delay time margin and the density increase, wiring improvement processing, and Automatically selecting execution of a cell replacement process for replacing a cell with a cell having a logically equivalent and different driving capability. 2. A method of arranging cells of a logic function unit comprising a plurality of transistors on a base substrate and arranging the cells in a layout process when laying out a semiconductor integrated circuit connecting the cells by signal wiring. No delay time margin for the requested maximum delay time requirement, or for cells constituting a signal path sequence, taking into account the degree of increase in delay time margin and the density increase, wiring improvement processing, and A recording medium for recording a program for realizing a function of automatically selecting execution of cell replacement processing for replacing cells with cells having logically equivalent and different driving capacities. 3. When inputting circuit information after completion of logic design and performing layout design, (a) a step of initializing a level, and (b) a step of performing a timing analysis to predict a delay time of a path. (C) a step of determining a temporary layout position; and (d) a wiring improvement process, and a cell for replacing a cell with a cell that is logically equivalent and has a different driving capability when the level value is equal to or greater than a predetermined value. Performing a replacement process; and (e) updating a level. Controlling the wiring improvement process and the cell replacement process step to be performed at a low level, and setting the level value to the specified level. Until (a)
(E) performing a detailed arrangement and a wiring after performing the processing of the steps (e). 4. A process for causing a data processing device to execute a layout design after a logical design is completed, (a) a process for initializing a level, (b) a process for performing timing analysis and predicting a delay time of a path, c) a process of determining a provisional arrangement position; and (d) a wiring improvement process, which is performed when the level value is compared with a predetermined value and the level value is equal to or greater than the predetermined value. (E) a process of updating the level, and (f) a process of updating the level, and (f) a process of the steps (a) to (e) until the value of the level reaches a specified level. A recording medium on which a program for causing the information processing apparatus to execute the above-described processes (a) to (f) of the process of controlling to perform the process is described.