JP3005530B1 - Automatic placement and routing method - Google Patents

Abstract

Abstract: PROBLEM TO BE SOLVED: To prevent wiring deterioration due to electromigration and to apply a high-density floor plan obtained by a functional block floor plan and a power supply wiring floor plan to an actual layout. SOLUTION: A limit value of power consumption in power supply wiring is added to a temporary power supply wiring network created according to a result of arranging functional blocks on a chip and a result of calculation of power consumption, and the added power consumption is reduced. Determine the arrangement of the functional blocks based on the limit value, group the unit of the functional blocks based on the added power consumption limit, subsequently determine the power supply wiring network, calculate the current value flowing through the power supply wiring, Based on the calculation result, the power supply wiring width in consideration of electmigration is determined, and the signal lines of the functional blocks are wired using the determined power supply wiring width.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic placement and routing method for efficiently executing power supply wiring in a chip internal region while suppressing wiring deterioration in an integrated circuit device having various functional blocks.

[0002]

2. Description of the Related Art As a conventional automatic placement and routing method, there is, for example, a method described in Japanese Patent Application Laid-Open No. 5-259287. This is, as shown in FIG. 5, a power consumption calculation step S1 based on a power consumption calculation test vector D2 of each functional block constituting the LSI logic, and an LSI circuit connection data D1.
Execution step S2 for executing a floor plan based on the above, and power consumption distribution data output step S3 for obtaining chip surface power consumption distribution data in which the calculated values from the power consumption calculation step S1 correspond to the functional blocks arranged in the floor plan.
A roof data extraction step S4 for extracting a roof position from the power consumption distribution data, a power supply wiring entrance determination step 35 for determining a power supply wiring entrance at an outer peripheral portion of the floor plan execution area, and a power consumption value distribution. Route determining step S6 for determining a power supply wiring route from the power supply lead-in port to the floor plan execution area based on the roof data of the power supply, a power supply wiring network creation step S7 for creating a power supply wiring network, A power supply wiring current calculating step S8 for calculating a branch current of the power supply wiring based on the power consumption value, a power supply wiring width determining step S9 for determining a power supply wiring width based on the current value, a floor plan adjusting step S10, and a power consumption distribution. Recalculation step S
11 and the wiring step S12 of the signal line of the functional block.

In this conventional example, power consumption distribution data of an image as shown in FIG. 6 is generated on a chip in step S3. In such an image of the power consumption distribution data, P1 to P5 represent the magnitude of power in the power consumption distribution, and the equal power line 11 is a boundary line. Next, after executing the power consumption distribution “roof” data extraction step S4 in FIG. 5, the internal function area 1 shown in FIG.
Power supply wiring 14 laid to connect the roof of power consumption distribution to peripheral power supply wiring 13
At the intersection of the power supply wiring entrance 15 (steps S5 and S6 in FIG. 5). Hereinafter, steps S7 to S7 in FIG.
Steps S12 to S12 are sequentially performed.

[0004]

However, in such a conventional automatic placement and routing method, the factor that determines the power supply wiring route is the roof of the power consumption distribution, and the function block of the conventional function block is not used. There has been a problem that the optimum layout concept in the floor plan and the power supply wiring floor plan is not reflected in the actual layout. In the conventional example, the power supply wiring width becomes extremely wide at only one point due to the reduction in current consumption, and there is a case where the arrangement of the functional blocks needs to be changed. In this case, steps S9 to S11 are performed. The wiring width is determined again by the loop, and therefore, there is a problem that the design time becomes longer by repeatedly executing this loop. In addition, there is a problem that the chip size becomes large because the peripheral power supply wiring is required.

The present invention has been made to solve the above-mentioned problems. In consideration of the power consumption of each functional block, it is possible to prevent wiring deterioration due to electromigration, and to obtain a high level obtained by a functional block floor plan and a power supply wiring floor plan. An object of the present invention is to provide an automatic placement and routing method that can reduce the area required for power supply wiring and shorten the design time by making it possible to apply a floor plan of density to an actual layout.

[0006]

In order to achieve the above object, an automatic placement and routing method according to the first aspect of the present invention executes a placement plan of a functional block on a chip based on LSI circuit connection data and calculates power consumption. Test vector and the L
Based on the SI circuit connection data, calculate the power consumption of each of the functional blocks and the entire chip, and create a temporary power supply wiring network in accordance with the result of arranging the functional blocks on the chip and the result of calculating the power consumption. Adding a limit value of power consumption in the power supply wiring to the temporary power supply wiring network, further determining an arrangement of functional blocks based on the added limit value of the added power consumption, and grouping the functional blocks; Grouping based on the added power consumption limitation, determine a power supply wiring network following the grouping of the functional blocks, calculate a current value flowing through the power supply wiring, and perform an electromigration based on the calculation result. In consideration of the above, the power supply line width is determined, and the signal lines of the functional blocks are wired based on the determined power supply line width.

According to a second aspect of the present invention, there is provided an automatic placement and routing method, wherein the placement of the signal lines is not performed in the floor plan step, and the placement plan is executed so that the entire chip has a high density. It is.

In the automatic placement and routing method according to a third aspect of the present invention, in the floor plan step, the functional blocks are arranged close to each other so as to reduce a bus connection wiring capacity. .

According to a fourth aspect of the present invention, there is provided the automatic placement and routing method, wherein the limit value is set to a value selected so as not to exceed a total power consumption value of a macro block or a functional block supplied from a power supply line. It was done.

According to a fifth aspect of the present invention, there is provided an automatic placement and routing method, wherein a limit value in a functional block array area is determined by a mutual relation between the functional blocks determined by a floor plan and a power consumption of the functional blocks. It is determined by the value.

[0011]

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a flowchart showing an automatic placement and routing procedure according to the present invention. In other words, the automatic placement and routing method of the present invention includes a floor plan step A1 for executing a placement plan of a functional block on a chip based on the LSI circuit connection data D1, a power consumption calculation test vector D2, and the LSI circuit connection data D1. And a function block power consumption calculating step A2 for calculating the power consumption of each of the functional blocks and the entire chip based on the above. A step A3 of creating a temporary power supply wiring network to be created; a step A4 of adding a power consumption limit value to a power supply wiring to the temporary power supply wiring network; and a limit value of the added power consumption. A function block arrangement step A5 for deciding the arrangement of the function blocks based on A function block grouping step A6 for grouping the balls based on the added power consumption restriction, a power supply wiring network determination step A7 for determining a power supply wiring network following the grouping of the functional blocks, Power supply wiring width determining step A8 for determining a power supply wiring width in consideration of electmigration based on the calculation result, and a signal line for wiring a signal line of a functional block with the determined power supply wiring width. Execute wiring step A9.

In this way, it is possible to reduce the area required for the power supply wiring, prevent wiring deterioration due to electromigration, and realize a highly reliable and area efficient layout in a short time.

Next, the operation of this embodiment will be described in more detail with reference to FIGS. This embodiment has LSI circuit connection data D1 and a power consumption calculation test vector D2. The power consumption calculation test vector D2 is a set of changes in the input signal to the LSI, which is created for the purpose of calculating the power consumption of the LSI. The time period of the considered input signal change is also taken into account. First, based on the LSI circuit connection data D1, a plan for arranging functional blocks on a chip is performed in a conventional functional block layout (floor plan) step A1. At this time, the signal lines are not wired, and the functional blocks are arranged so that the entire chip has a high density while observing the connection relation of the signal lines. In particular, the functional blocks are arranged close to each other so as to reduce the bus connection wiring capacitance.

On the other hand, in a function block power consumption calculation step A2, the power consumption is calculated by giving a power consumption calculation test vector D2 to the data D1, and the power consumption of each function block and the entire chip is obtained. Next, based on the result of the functional block arrangement step A1, a temporary power supply wiring network creation (power supply wiring floor plan) step A3 is executed, and an optimum power supply wiring plan is executed for the entire chip. FIG. 2 is a diagram showing a chip image after execution of a step A3 for creating a temporary power supply wiring network in FIG. As shown in FIG. 2, the LSI chip 1 has a functional block array area 2 and existing blocks (macro blocks) designed in advance, in this example, a ROM 3 and a RAM 4. In FIG. 2, pad regions other than the input / output buffer and the power supply pad 5 formed in the peripheral portion are omitted. In FIG. 2, the power supply network obtained as a result of the temporary power supply network creation step A3 in FIG.
There are a power supply line 6 for the OM 3, a power supply line 7 for the RAM 4, and power supply lines 8, 9 and 10 for the functional block array area 2.

Returning now to FIG. A limit value is added to the power supply wiring network obtained in the temporary power supply network creation step A3 in a power supply power consumption limit value adding step A4.
Here, the limit value is data for limiting the total power consumption value of the macro block or the functional block so as not to exceed the added value, which is supplied from the power supply wiring to which the limit value is added. Referring to FIG. 2, the power supply lines 6 and 7 are power supply lines for the macroblocks ROM3 and RAM4. Therefore, the limit value added in the power consumption limit value adding step A4 is determined by the power consumption of the ROM3 and RAM4. . The limit value of the power supply wiring in the functional block array region 2 is determined by the mutual relationship between the functional blocks determined by the floor plan and the power consumption value of the functional block obtained in the functional block power consumption calculation step A2.

In FIG. 2, the power consumption limit values added to the power supply wirings 8, 9, and 10 are equal. This is because the functional blocks are evenly arranged from the mutual relationship between the functional blocks. Therefore, in this embodiment, the power consumption limit value of the power supply wirings 8, 9, and 10 is determined based on a value obtained by dividing the power consumption of the entire functional block into three equal parts. Also,
The functional blocks are not always arranged evenly.
When the arrangement of the functional blocks is uneven, the current consumption limit value is determined to be an appropriate value according to the arrangement of the functional blocks.

Next, a function block arrangement step A5 and a function block grouping step A6 are executed. First, the function block arranging step A5, which is a conventional layout process, determines the arrangement of the functional blocks based on the limit value added in the power consumption limit value adding step A4 at that time. On the other hand, the functional block grouping step A6 is a step performed to increase the density of signal wiring between the functional blocks. Conventionally, related functional blocks have been arranged close to each other for high density, and in a functional block grouping step A6, the functional blocks are grouped together and the limit value in the power consumption limit value adding step A4 is reduced. Group into groups. FIG. 3 is a diagram showing a chip image after executing the functional block grouping step A6.
The function blocks are groups 11, 12, 13, 14, 15
Are grouped in The power consumption of the groups 11 and 12 is grouped such that a value obtained by adding both of them becomes a close value not exceeding the power consumption limit value of the power supply wiring 8. Similarly, the power consumption of the groups 13 and 14 satisfies the limit value of the power supply wiring 9, and the power consumption of the group 15 satisfies the limit value of the power supply wiring 10.

Thus, in this embodiment, the arrangement of the functional blocks and the power supply wiring network are determined. Thereafter, the current flowing through each power supply line is calculated from the impedance of the power supply line, and the current value is used to determine the power supply line width in consideration of electromigration.
Step 8 Next, the wiring step A9 of the signal line of the functional block, which has been performed conventionally, is executed, and the processing is ended. In step A4, a current limit value may be added to the power supply lines 8, 9, and 10 in the functional block area, and a resistance limit value may be added to the power supply lines 6 and 7 of the ROM 3 and the RAM 4 as macro blocks. .

Next, another embodiment of the present invention will be described with reference to FIG. This embodiment is an example of a layout in which an LSI chip is formed using macro blocks. First, using the macroblock connection data D3, a macroblock arrangement step B1 is executed, and a temporary power supply wiring network creation step B2 is executed based on this arrangement. Next, a limit value is added to the power supply wiring in the creation step B2. Since the macro block is an already designed block, various information is known. This embodiment shows a case where the power consumption value of a macroblock is known, and since the power consumption is already known, FIG.
Instead of the power consumption limit value addition step A4 of the power supply wiring, a power supply resistance limit value addition step B3 is executed. Thereafter, a macro block arranging step B4 is executed. Then, as in the case described with reference to FIG. 1, a power wiring network creating step B5, a power wiring width determining step B6, and a macro block signal line wiring step B7 are performed. Execute sequentially. Further, instead of adding the resistance limit value in step B3, a current limit value may be added. That is, when a macroblock is used, the limit value is determined based on the information of the macroblock.

[0021]

As described above, according to the present invention, LS
Executing a layout plan of the functional blocks on the chip based on the I-circuit connection data; calculating power consumption of each of the functional blocks and the entire chip based on the test vector for power consumption calculation and the LSI circuit connection data; Creating a temporary power supply wiring network according to a result of arranging the functional blocks on a chip and a result of calculating the power consumption, adding a limit value of power consumption in power supply wiring to the temporary power supply network, Determining the arrangement of the functional blocks based on the added power consumption limit value, and grouping the functional blocks together based on the added power consumption limit, and grouping the functional blocks. Subsequently, a power supply wiring network is determined, a value of a current flowing through the power supply wiring is calculated, and an electmigration is considered based on the calculation result. The power supply wiring width is determined, and the signal lines of the functional blocks are wired with the determined power supply wiring width.In consideration of the current consumption of each block, wiring deterioration due to electromigration can be prevented. The high-density floor plan obtained by the functional block floor plan and the power supply wiring floor plan can be applied to the actual layout, and as a result, the effect of reducing the area required for the power supply wiring can be obtained. In addition, the power supply wiring network created by the power supply wiring floor plan can be used in an actual layout, and there is an effect that the design can be performed in a short time because a re-floor plan is not required because some power supply wirings become very wide. Can be

[Brief description of the drawings]

FIG. 1 is a flowchart showing an automatic placement and routing method according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a chip image after a temporary power supply wiring network is created in the present invention.

FIG. 3 is an explanatory diagram showing a chip image after functional block grouping in the present invention.

FIG. 4 is a flowchart showing an automatic placement and routing method according to another embodiment of the present invention.

FIG. 5 is a flowchart showing a conventional automatic placement and routing method.

FIG. 6 is an explanatory diagram showing a chip image of a conventional power supply wiring laying route.

[Explanation of symbols]

 D1 LSI circuit connection data D2 Test vector for power consumption calculation D3 Macroblock connection data

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/82 H01L 27/04

Claims (5)

(57) [Claims] A floor plan step for executing a plan for arranging functional blocks on a chip based on LSI circuit connection data; and the functional blocks and the chip based on a power consumption calculation test vector and the LSI circuit connection data. A functional block power consumption calculating step of calculating the entire power consumption; a temporary power supply wiring network creating step of creating a temporary power supply wiring network according to a result of arranging the functional blocks on a chip and the calculation result of the power consumption; A power consumption limit value adding step of adding a power consumption limit value in the power supply wiring to the temporary power supply wiring network; and a function block arranging step of deciding an arrangement of functional blocks based on the added power consumption limit value. And grouping the functional blocks based on the added power consumption limit. A functional block grouping step, a power supply wiring network determining step of determining a power supply wiring network subsequent to the functional block grouping, calculating a current value flowing through the power supply wiring, and considering an electmigration based on the calculation result. An automatic placement and routing method, comprising: a power supply wiring width determining step of determining a power supply wiring width; and a signal line wiring step of wiring a signal line of a functional block with the determined power supply wiring width. 2. The automatic placement and routing method according to claim 1, wherein, in said floor plan step, a placement plan is executed so that signal lines are not wired and a high density of the entire chip is performed. 3. The automatic placement and routing method according to claim 1, wherein, in the floor plan step, the functional blocks are arranged close to each other so as to reduce a bus connection wiring capacity. 4. The automatic control method according to claim 1, wherein the limit value is a set value selected so as not to exceed a total power consumption value of a macro block or a function block supplied from a power supply line. Place and route method. 5. The function block arrangement area according to claim 1, wherein the limit value is determined by a mutual relationship between the function blocks determined by a floor plan and a power consumption value of the function blocks. Automatic placement and routing method described in 1.