JP3083725B2 - シリコン・オン・サファイア・ウエーハの製造方法 - Google Patents

シリコン・オン・サファイア・ウエーハの製造方法

Info

Publication number
JP3083725B2
JP3083725B2 JP07031925A JP3192595A JP3083725B2 JP 3083725 B2 JP3083725 B2 JP 3083725B2 JP 07031925 A JP07031925 A JP 07031925A JP 3192595 A JP3192595 A JP 3192595A JP 3083725 B2 JP3083725 B2 JP 3083725B2
Authority
JP
Japan
Prior art keywords
silicon
layer
wafer
depositing
sos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP07031925A
Other languages
English (en)
Japanese (ja)
Other versions
JPH07283383A (ja
Inventor
ジェームズ・エル・エグリー
ジョージ・エム・ガット
ダニエル・ジェイ・コッホ
マイケル・エイ・マトゥセヴィツ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPH07283383A publication Critical patent/JPH07283383A/ja
Application granted granted Critical
Publication of JP3083725B2 publication Critical patent/JP3083725B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/0242Crystalline insulating materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02658Pretreatments
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Light Receiving Elements (AREA)
  • Pressure Sensors (AREA)
JP07031925A 1994-04-07 1995-02-21 シリコン・オン・サファイア・ウエーハの製造方法 Expired - Fee Related JP3083725B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/224,451 US5877094A (en) 1994-04-07 1994-04-07 Method for fabricating a silicon-on-sapphire wafer
US224451 1994-04-07

Publications (2)

Publication Number Publication Date
JPH07283383A JPH07283383A (ja) 1995-10-27
JP3083725B2 true JP3083725B2 (ja) 2000-09-04

Family

ID=22840748

Family Applications (1)

Application Number Title Priority Date Filing Date
JP07031925A Expired - Fee Related JP3083725B2 (ja) 1994-04-07 1995-02-21 シリコン・オン・サファイア・ウエーハの製造方法

Country Status (5)

Country Link
US (2) US5877094A (US06623731-20030923-C00012.png)
EP (1) EP0676794A3 (US06623731-20030923-C00012.png)
JP (1) JP3083725B2 (US06623731-20030923-C00012.png)
KR (1) KR0170464B1 (US06623731-20030923-C00012.png)
TW (1) TW286426B (US06623731-20030923-C00012.png)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7893522B2 (en) 2007-09-27 2011-02-22 Oki Semiconductor Co., Ltd. Structural body and manufacturing method thereof
US7989324B2 (en) 2005-03-18 2011-08-02 Oki Semiconductor Co., Ltd. Method for manufacturing silicon on sapphire wafer
JPWO2013094665A1 (ja) * 2011-12-22 2015-04-27 信越化学工業株式会社 複合基板

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6235611B1 (en) * 1999-01-12 2001-05-22 Kulite Semiconductor Products Inc. Method for making silicon-on-sapphire transducers
US6698295B1 (en) * 2000-03-31 2004-03-02 Shipley Company, L.L.C. Microstructures comprising silicon nitride layer and thin conductive polysilicon layer
US7026697B2 (en) * 2000-03-31 2006-04-11 Shipley Company, L.L.C. Microstructures comprising a dielectric layer and a thin conductive layer
US6544810B1 (en) * 2000-08-31 2003-04-08 Motorola, Inc. Capacitively sensed micromachined component and method of manufacturing
JP4910066B2 (ja) * 2004-01-06 2012-04-04 ラピスセミコンダクタ株式会社 半導体ウエハとその製造方法
JP4714423B2 (ja) * 2004-01-06 2011-06-29 Okiセミコンダクタ株式会社 半導体ウエハとその製造方法
JP4897210B2 (ja) * 2004-11-18 2012-03-14 ラピスセミコンダクタ株式会社 半導体装置の構造及びその製造方法
JP4938243B2 (ja) * 2005-03-04 2012-05-23 ラピスセミコンダクタ株式会社 半導体装置及びその製造方法、並びに、半導体ウエハ及び半導体ウエハの製造方法
JP4708150B2 (ja) * 2005-10-14 2011-06-22 Okiセミコンダクタ株式会社 半導体装置の形成方法
JP5219527B2 (ja) * 2008-01-22 2013-06-26 ラピスセミコンダクタ株式会社 ウエハプロセス適用基板及びその製造方法
WO2009123261A1 (ja) * 2008-04-01 2009-10-08 信越化学工業株式会社 Soi基板の製造方法
JP2010010214A (ja) * 2008-06-24 2010-01-14 Oki Semiconductor Co Ltd 半導体装置の製造方法、半導体製造装置、及び記憶媒体
JP5633328B2 (ja) 2010-11-18 2014-12-03 住友電気工業株式会社 半導体装置の製造方法
US10052848B2 (en) 2012-03-06 2018-08-21 Apple Inc. Sapphire laminates
US9221289B2 (en) 2012-07-27 2015-12-29 Apple Inc. Sapphire window
US9232672B2 (en) 2013-01-10 2016-01-05 Apple Inc. Ceramic insert control mechanism
US9632537B2 (en) 2013-09-23 2017-04-25 Apple Inc. Electronic component embedded in ceramic material
US9678540B2 (en) 2013-09-23 2017-06-13 Apple Inc. Electronic component embedded in ceramic material
US9154678B2 (en) 2013-12-11 2015-10-06 Apple Inc. Cover glass arrangement for an electronic device
US9225056B2 (en) 2014-02-12 2015-12-29 Apple Inc. Antenna on sapphire structure
US10406634B2 (en) 2015-07-01 2019-09-10 Apple Inc. Enhancing strength in laser cutting of ceramic components

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5541709A (en) * 1978-09-16 1980-03-24 Chiyou Lsi Gijutsu Kenkyu Kumiai Sos semiconductor base
JPS55153347A (en) * 1979-05-18 1980-11-29 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device
JPS5827663B2 (ja) * 1979-06-04 1983-06-10 富士通株式会社 半導体装置の製造方法
US4230505A (en) * 1979-10-09 1980-10-28 Rca Corporation Method of making an impatt diode utilizing a combination of epitaxial deposition, ion implantation and substrate removal
JPS57153445A (en) * 1981-03-17 1982-09-22 Nec Corp Sos semiconductor substrate
JPS57162346A (en) * 1981-03-30 1982-10-06 Jido Keisoku Gijutsu Kenkiyuukumiai Manufacutre of insulating and isolating substrate
US4608095A (en) * 1983-02-14 1986-08-26 Monsanto Company Gettering
US4608096A (en) * 1983-04-04 1986-08-26 Monsanto Company Gettering
JPS62193147A (ja) * 1986-02-19 1987-08-25 Toshiba Corp 半導体装置の製造方法
US4732867A (en) * 1986-11-03 1988-03-22 General Electric Company Method of forming alignment marks in sapphire
US5006479A (en) * 1990-02-27 1991-04-09 Rockwell International Corporation Methods for improving radiation tolerance of silicon gate CMOS/silicon on sapphire devices
JPH0637317A (ja) * 1990-04-11 1994-02-10 General Motors Corp <Gm> 薄膜トランジスタおよびその製造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7989324B2 (en) 2005-03-18 2011-08-02 Oki Semiconductor Co., Ltd. Method for manufacturing silicon on sapphire wafer
US7893522B2 (en) 2007-09-27 2011-02-22 Oki Semiconductor Co., Ltd. Structural body and manufacturing method thereof
JPWO2013094665A1 (ja) * 2011-12-22 2015-04-27 信越化学工業株式会社 複合基板
US9425248B2 (en) 2011-12-22 2016-08-23 Shin-Etsu Chemical Co., Ltd. Composite substrate
KR101852229B1 (ko) 2011-12-22 2018-04-25 신에쓰 가가꾸 고교 가부시끼가이샤 복합 기판

Also Published As

Publication number Publication date
TW286426B (US06623731-20030923-C00012.png) 1996-09-21
EP0676794A2 (en) 1995-10-11
KR950030219A (ko) 1995-11-24
KR0170464B1 (ko) 1999-03-30
JPH07283383A (ja) 1995-10-27
US5877094A (en) 1999-03-02
US6238935B1 (en) 2001-05-29
EP0676794A3 (en) 1995-11-29

Similar Documents

Publication Publication Date Title
JP3083725B2 (ja) シリコン・オン・サファイア・ウエーハの製造方法
US5250445A (en) Discretionary gettering of semiconductor circuits
US5739067A (en) Method for forming active devices on and in exposed surfaces of both sides of a silicon wafer
US5324974A (en) Nitride capped MOSFET for integrated circuits
US7989324B2 (en) Method for manufacturing silicon on sapphire wafer
JPH07142567A (ja) Soi膜厚制御法
US5028564A (en) Edge doping processes for mesa structures in SOS and SOI devices
CN1199240C (zh) 利用快速热退火与氧化气体形成底部抗反射涂层的方法
JPH0454388B2 (US06623731-20030923-C00012.png)
US5897362A (en) Bonding silicon wafers
JPS63175431A (ja) ホウケイ酸ガラスを有する半導体装置の製造方法
US4194934A (en) Method of passivating a semiconductor device utilizing dual polycrystalline layers
US4161744A (en) Passivated semiconductor device and method of making same
US20030022461A1 (en) Amorphizing ion implant local oxidation of silicon (LOCOS) method for forming an isolation region
US6281146B1 (en) Plasma enhanced chemical vapor deposition (PECVD) method for forming microelectronic layer with enhanced film thickness uniformity
US11295982B2 (en) Forming ultra-thin chips for flexible electronics applications
JPH098150A (ja) 自己整合型二重ウェルプロセス
EP0656652B1 (en) Method of forming isolation trenches in integrated circuits
EP0066675B1 (en) Processes for the fabrication of field effect transistors
JPH02153525A (ja) 半導体装置の製造方法
KR0119275B1 (ko) 기판접합기술을 이용한 서로 다른 활성층 두께를 갖는 soi구조의 기판 제조방법
Söderbärg Investigation of buried etch stop layer in silicon made by nitrogen implantation
JPS5951549A (ja) 集積回路装置の製造方法
EP0383816B1 (en) Process methodology for two-sided fabrication of devices on thinned silicon
GB2168340A (en) Forming glass layers on semiconductor substrates

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees