JP2919223B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Generally, in a semiconductor integrated circuit, after a wafer is manufactured, all the semiconductor chips (hereinafter, referred to as "chips") on the wafer are manufactured.
A wafer test is performed to test the characteristics of the chip. In this case, a pad-shaped terminal (hereinafter, referred to as an external IC tester) used for inputting a signal from an external IC tester or the like, or used for outputting a signal inside the chip, is arranged around the chip arranged on the wafer. A needle (hereinafter, referred to as a signal application needle) for applying or taking in a predetermined signal is connected to the signal input / output pad. As for the connection between the signal input / output pad and the signal application needle, a circuit for transmitting a signal input from the signal input / output pad to an internal area (hereinafter referred to as an input protection circuit), and an internal area The diode characteristic of a circuit for transmitting the signal to the signal input / output pad (hereinafter referred to as an output buffer) is determined by applying a certain current from the signal input / output pad and detecting the voltage value at that time. Has been confirmed by

FIG. 3 shows an example of a conventional semiconductor integrated circuit. In FIG. 3, the on-wafer chip 1 includes an internal region 7 for forming a circuit inside the chip, and an input protection circuit 5 and an output buffer 6 are arranged around the internal region 7. A signal input / output pad 2 is arranged outside the input protection circuit 5 and the output buffer 6. In FIG. 3,
One signal input / output pad 2 is provided in the middle of one side of the chip (a total of four pads), and the input protection circuit 5 and the output buffer 6 are represented by one circuit configuration. As shown in FIG. 4 (a), the on-wafer chips 1 are arranged on the wafer 8 in several vertical and horizontal directions. A scribe area 4 is provided between the chips on the wafer.
Is interposed. In the wafer test of the wafer 8, as shown in FIG. 4 (a), usually, the same number of signal input / output pads 2 as the signal input / output pads 2 on the on-wafer chip 1 are provided and the signal application needles 3 arranged at the same position are provided. , These signal applying needles 3
This is performed using a probe card 10 that forms a substrate for connecting the tester signal terminals to the tester signal terminals. The connection between the signal application needle 3 and the signal terminal of the external IC tester is made via a connection portion 9 for connecting to the IC tester signal terminal on the probe card 10. When the wafer test is performed, the signal input / output pad 2 and the signal applying needle 3 are all connected to each other as shown in the II ′ cross-sectional view of the wafer 8 and the probe card 10 in FIG. Must be electrically connected. For this purpose, regarding the connection between the signal input / output pads 2 and the signal applying needles 3, the wafer is manually moved, the position is confirmed by silent gaze, and the contact check is repeated for all the signal input pads 2. It is done by that.

[0004]

In the above-described conventional semiconductor integrated circuit, a contact check on the connection between the signal input / output pad 2 and the signal applying needle 3 is performed on the chip on the chip. It is only determined whether or not connection between the signal application needle 3 and the signal application needle 3 is possible, and it is impossible to detect the degree of connection deviation with respect to the signal input / output pad 2 to which the signal application needle 3 is to be connected. . Therefore, there is no standard for adjusting the position of the wafer with respect to the signal applying needles 3, and therefore, there is a disadvantage that it is difficult to adjust the wafer position with respect to the signal applying needles 3.

[0005]

In a semiconductor integrated circuit according to a first aspect of the present invention, a predetermined signal input / output pad is arranged around a chip on a wafer, and an input protection circuit and an input protection circuit are provided inside the signal input / output pad. In a semiconductor integrated circuit having an output buffer disposed therein and further having an internal area inside the input protection circuit and the output buffer, A, B, C and D positioned at four corners of the on-wafer chip
Corresponding to each of the positions, the long side is set to be longer than the length of one side of the signal input / output pad, and the short side is set to be shorter than the length of one side of the signal input / output pad;
And a plurality of contact check pads arranged such that the long side is parallel to one side of the chip on the wafer at two corner positions specified by C corresponding to the diagonal positions, The shape is set to be longer than the length of one side of the signal input / output pad and the shorter side is shorter than the length of one side of the signal input / output pad, and designated by B and D corresponding to a diagonal position. A plurality of contact check pads arranged such that the long side is in a direction parallel to the other side orthogonal to the one side of the chip on the wafer at two corner positions; A plurality of resistive elements having different resistance values connected between mutually adjacent pads of the contact check dedicated pad are connected to at least the signal input / output pad and a predetermined signal applying needle. Is characterized by a comprising a wafer alignment for.

In a semiconductor integrated circuit according to a second aspect of the present invention, predetermined signal input / output pads are arranged around a chip on a wafer, and an input protection circuit and an output buffer are arranged inside the signal input / output pads. Further, in a semiconductor integrated circuit having an internal area inside the input protection circuit and the output buffer, the semiconductor integrated circuit may correspond to each of the positions A, B, C and D specified at the four corners of the chip on the wafer. The long side is set to be longer than the length of one side of the signal input / output pad, and the short side is set to be shorter than the length of one side of the signal input / output pad, corresponding to the A and the diagonal position. A plurality of (odd) contact check pads arranged so that the long side is parallel to one side of the chip on the wafer at two corner positions designated by C; The shape is set to be longer than the length of one side of the signal input / output pad and the shorter side is shorter than the length of one side of the signal input / output pad, and is designated by B and D corresponding to the diagonal position. A plurality of (odd) contact check-dedicated pads arranged at two corners such that the long side is in a direction parallel to the other side perpendicular to the one side of the chip on the wafer; A plurality of resistive elements having different resistance values connected between mutually adjacent pads of the contact check dedicated pads arranged, and a wafer for connecting at least the signal input / output pads and predetermined signal applying needles; together provided for the position adjustment, each contactor is located in central contact check dedicated pads disposed in two corners of the position specified by the a and C Check dedicated pad while connected by predetermined wiring, the B and D
It is characterized by connecting the respective contour <br/> transfected check only pad of Jo Tokoro wire positioned at the center of the contact check dedicated pads disposed in two corners of the position specified by the.

[0007]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a chip on a wafer according to a first embodiment of the present invention, and is a configuration diagram showing a state in which signal applying needles of a probe card are connected. As shown in FIG. 1, the on-wafer chip 1 according to the present embodiment has four scribe areas 4 corresponding to scribe areas 4 interposed between other on-wafer chips on the same probe card.
Signal input / output pads 2, four signal application needles 3 corresponding to each signal input / output pad 2, contact check pads P1 to P16, and resistance elements R1 to R
12 and contact check dedicated signal applying needles S1 to S8
And are arranged. In FIG. 1, an input protection circuit, an output buffer, and the like are not shown.

In FIG. 1, an on-wafer chip 1, signal input / output pads 2, signal application needles 3, and scribe areas 4 are provided.
Is the same as that of the conventional example in FIG. In this embodiment, the contact check pads P1 to P4
Are equally spaced in the upper left corner of the drawing,
The contact check pads P5 to P8 are arranged at regular intervals in the upper right corner of the drawing, and the contact check pads P9 to P12 are arranged at regular intervals in the lower right corner of the drawing. Dedicated pad P1
3 to P16 are arranged at equal intervals in the lower left corner of the drawing. In addition, adjacent contact check pads P1-P2, P2-P3, P3-P4, P5-
P6, P6-P7, P7-P8, P9-P10
, P10-P11, P11-P12, P13-P
14, between P14 and P15, and between P15 and P16, respectively, the resistance elements R1, R2, R3, R4, R5,
R6, R7, R8, R9, R10, R11 and R12
Is connected. The contact check dedicated signal applying needles S1 to S8 are respectively connected to two contact check dedicated pads P2 and P2 arranged at the center of four contact check dedicated pads at four corners on the chip on the wafer.
3, P6 and P7, P10 and P11, P14 and P15, so that all signal input / output pads 2 and all signal applying needles 3 are connected.
Each component is located on the probe card. Each of the contact check dedicated P1 to P16 has a rectangular shape in which one side is longer than the length of one side of the signal input / output pad 2 and the other side is shorter than the length of one side of the signal input / output pad 2. Are arranged at equal intervals one by one,
They are arranged in the orientation as shown in FIG. Further, the resistance elements R1 to R3, R4 to R6, R7 to R9, and R
In each of 10 to R12, three resistance values are set to different values, and those resistance values are measured in advance and clearly defined.

At the time of a wafer test, the positional relationship between all the signal input / output pads 25 and the corresponding signal applying needles 3 is first checked by visual inspection, and the positioning of the chip 1 on the wafer with respect to the probe card moves the wafer. It is performed while letting. Next, the signal applying needle S dedicated for contact check
1-S2, S3-S4, S5-S6, and S7
A potential difference is applied between −S8, and a resistance value is calculated from a current value flowing into the potential pad. Based on the calculation result of the resistance value, a contact check dedicated pad P2 to which the contact check dedicated signal applying needles S1 to S8 are connected. , P3, P
6, P7, P10, P11, P14 and P15 are determined. Thus, the signal applying needle 3
Is detected with respect to the signal input / output pad 2 to which is connected.

FIG. 2 is a structural layout of a chip on a wafer according to a second embodiment of the present invention, and is a structural diagram showing a state in which signal applying needles of a probe card are connected. As shown in FIG. 2, the chip 1 on the wafer in this embodiment has four scribe areas 4 corresponding to the scribe areas 4 interposed between the chips on another wafer on the same probe card.
Signal input / output pads 2, four signal application needles 3 corresponding to the respective signal input / output pads 2, contact check dedicated pads P17 to P28, and a resistance element R13.
~ R20 and contact check dedicated signal applying needle S9 ~
S12 is arranged. In FIG. 2, an input protection circuit, an output buffer, and the like are not shown.

In FIG. 2, on-wafer chip 1, signal input / output pad 2, signal applying needle 3, and scribe area 4
Is the same as that of the first embodiment in FIG. In this embodiment, the contact check pad P1 is used.
7 to P19 are equidistantly arranged in the upper left corner of the chip 1 on the wafer toward the drawing. The contact check pads P23 to P25 are arranged at regular intervals in the lower right corner of the on-wafer chip 1 facing the drawing, and the contact check pads P13 to P16 are placed on the wafer facing the drawing. The chips 1 are arranged at equal intervals in the lower left corner.
Adjacent contact check pad P17-P18
, P18-P19, P20-P21, P21-P
22, P23-P24, P24-P25, P26
-P27 and between P27 and P28, respectively, the resistance elements R14, R13, R16, R15, R17, R1
8, R20 and R19 are connected. Also, of these three contact check pads at the four corners,
The contact check pads P18 and P24, and P21 and P27, which are respectively disposed in the center, are connected by wirings W1 and W2, respectively. In addition,
These resistance elements R13 to R20 and wirings W1, W2
Are laid in the scribe area 4.

[0013] Contact check dedicated signal applying needle S9 ~
S12 is a contact check pad P18, P21, P24 arranged at the center of each of the three contact check pads at the four corners on the chip on the wafer.
And P27, whereby the respective components are arranged on the probe card such that all the signal input / output pads 2 and all the signal applying needles 3 are connected. P17-P28 for contact check is the first
As in the case of the embodiment of FIG.
Is longer than the length of one side, and the other side is a rectangle shorter than the length of one side of the signal input / output pad 2. Three rectangles are arranged at regular intervals, as shown in FIG. It is arranged in the direction. Further, the resistance elements R14 and R1
7, the sum of the resistance values of R13 and R18 is set to different values, respectively, and the resistance elements R15 and R19, R16 and R16
The sums of the respective resistance values of 20 are also set to different values, and the resistance values are measured in advance and clearly defined.

In the above-described first embodiment, eight contact check dedicated signal applying needles are required, but in this embodiment, only a contact check dedicated signal applying needle S is required.
Although the four contact check dedicated signal application needles including 9 to S12 are provided, the contact check dedicated signal apply needles S9 to S12 are connected by measuring and calculating the resistance value between the diagonal contact check dedicated signal apply needles. Contact check pads P18, P2
1, P24 and P27 are determined.
In this way, the degree of deviation from the signal input / output pad 2 to which the signal applying needle 3 is connected is detected. Note that, inside the on-wafer chip 1, the resistance elements R13 to R2
It is not necessary to secure areas for laying the wirings 0 and the wirings W1 and W2, and by increasing the number of pads dedicated to contact check, the degree of deviation from the signal input / output pad 2 to which the signal applying needle 3 is connected can be further widened. Needless to say, it can be detected over a wide range. Also, the function of measuring the resistance value between the contact check dedicated pads by the contact check dedicated signal applying needle, the function of determining the degree of deviation from the signal input / output pad to which the signal applying needle is connected, and the alignment of the chip with the probe card are performed. For example, by mounting a wafer moving function and the like on a wafer test apparatus, a contact check in a semiconductor integrated circuit can be automatically performed.

[0015]

As described above, according to the present invention, a plurality of contact check dedicated pads are arranged at four corners of a chip on a wafer, and resistance elements having different resistance values are connected between the adjacent contact check dedicated pads. By measuring the resistance value between the contact check dedicated pads with a contact check dedicated signal applying needle, it is possible to detect the degree of deviation of the signal applying needle from the signal input / output pad, There is an effect that the wafer position can be easily adjusted.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a chip on a wafer according to a first embodiment of the present invention.

FIG. 2 is a layout view of a chip on a wafer according to a second embodiment of the present invention.

FIG. 3 is a configuration diagram of a chip on a wafer in a conventional example.

FIG. 4 is a structural layout diagram and I- of a probe card.
It is a figure which shows I 'cross section.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 On-wafer chip 2 Signal input / output pad 3 Signal application needle 4 Scribe area 5 Input protection circuit 6 Output buffer 7 Internal area 8 Wafer 9 Connection part 10 Probe card 11 Insulation layer P1-P28 Contact check pad R1-R20 Resistance element S1 to S12 Contact check dedicated signal application needle W1, W2 Wiring

Claims (2)

(57) [Claims] 1. A predetermined signal input / output pad is arranged in the periphery of a chip on a wafer, and an input protection circuit and an output buffer are arranged inside the signal input / output pad. In a semiconductor integrated circuit having an internal area inside an output buffer, a long side corresponding to each of positions A, B, C and D specified at four corners of the chip on the wafer has a long side for signal input / output. Two corner positions designated by A and C corresponding to the diagonal position, wherein the shape is set to be longer than the length of one side of the pad and shorter than the length of one side of the signal input / output pad. A plurality of contact check pads arranged such that the long side is parallel to one side of the chip on the wafer; and the long side is longer than the length of one side of the signal input / output pad. The short side is set to a shape shorter than the length of one side of the signal input / output pad, and the long side is located at two corners designated by B and D corresponding to the diagonal position. A plurality of contact check-dedicated pads arranged in a direction parallel to the other side orthogonal to the one side of the upper chip; and between the mutually adjacent pads of the contact check-dedicated pads respectively arranged at the four corners A semiconductor integrated circuit, comprising: a plurality of resistance elements having different resistance values connected to a plurality of resistance elements for adjusting a wafer position for connecting at least the signal input / output pad and a predetermined signal application needle. 2. A predetermined signal input / output pad is arranged in the periphery of a chip on a wafer, and an input protection circuit and an output buffer are arranged inside the signal input / output pad. In a semiconductor integrated circuit having an internal area inside an output buffer, a long side corresponding to each of positions A, B, C and D specified at four corners of the chip on the wafer has a long side for signal input / output. Two corner positions designated by A and C corresponding to the diagonal position, wherein the shape is set to be longer than the length of one side of the pad and shorter than the length of one side of the signal input / output pad. A plurality of (odd) contact check pads arranged such that the long side is parallel to one side of the chip on the wafer; and the long side is the length of one side of the signal input / output pad. And the short side is set to a shape shorter than the length of one side of the signal input / output pad, and the long side is set at two corner positions designated by B and D corresponding to a diagonal position. A plurality of (odd) dedicated contact check pads arranged so as to be parallel to the other side orthogonal to the one side of the chip on the wafer; and the contact check dedicated pads respectively arranged at the four corners. A plurality of resistive elements having different resistance values connected between mutually adjacent pads, for adjusting a wafer position for connecting at least the signal input / output pad and a predetermined signal applying needle; given the respective contact check dedicated pads located in the center of the contact check dedicated pads disposed in two corners of the position designated by and C
Along with connecting the wiring to connect the respective contact check dedicated pad of Jo Tokoro wire positioned at the center of the contact check dedicated pads disposed in two corners of the position specified by the B and D Characteristic semiconductor integrated circuit.