JPH0494555A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To effectively conduct a characteristic test in a semiconductor chip stage by a method wherein presence or absence of conduction between a pair of pad electrodes for positioning in which relative position relationship with other pad electrodes for tests is precisely determined is detected. CONSTITUTION:A semiconductor chip 10 is formed with a plurality of input/ output buffer 2 and a pair of pad electrodes 3, 4 for probe card positioning which are connected to each other by a wire 7. The pair of pad electrodes 3, 4 for positioning are arranged after relative position relationship with other pad electrodes for signal input/output tests is precisely determined. When a characteristic test is carried out, if a current flows by applying a voltage to between the pad electrodes 3, 4, it is judged that all other needles are precisely positioned respectively. Thus, conduction between pad electrodes 3, 4 for probe card positioning is just detected, so that it can readily be confirmed whether or not the probe card and chip are precisely positioned.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device with high characteristic test efficiency.

[Prior Art 1] When a semiconductor integrated circuit device is manufactured, a characteristic test is first performed at the chip stage. This characteristic test is performed by placing the probe needle of the probe card on the characteristic test pad electrode arranged around the semiconductor chip. At this time, the probe card 8 is slightly moved in the θ direction as shown in There may be deviations. If the probe card is misaligned in this way, the probe needles will not come into contact with the characteristic test pad electrodes, so accurate test results may not be obtained. Therefore,
In this test, it is necessary to check each time whether the probe needle is in contact with the characteristic test pad electrode on the chip.

In the case of conventional semiconductor integrated circuit devices, this can be checked either by visually observing the semiconductor chip using a microscope from directly above it, or by applying voltage to all probe needles and checking whether current flows. Usually, this method is used.

[Problem to be solved by the invention] However, in the case of the former confirmation method, as the degree of integration of semiconductor devices increases, the number of pads increases, and the number of needles raised from the probe card increases. Even if you use , it is difficult to accurately confirm the positional relationship between the two. Therefore, a certain amount of experience is required to accurately judge whether there is a gap between the two. Furthermore, even in the latter case, it is necessary to check all the probe needles, which is too time-consuming, and both methods significantly reduce the test efficiency.

SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a semiconductor integrated circuit device that can efficiently perform characteristic tests at the semiconductor chip stage.

[Means for Solving the Problems j] According to the present invention, a semiconductor integrated circuit device includes a semiconductor substrate, an electronic circuit element region formed on the semiconductor substrate,
at least one pair of probe card alignment pad electrodes provided on the semiconductor substrate with a relative positional relationship with the characteristic test pad electrode of the electronic circuit element area being accurately defined in advance; and the at least one pair of probe card alignment pad electrodes. It is configured to include substrate wiring that connects the matching pad electrodes to each other.

[Function] According to the present invention, the integrity of the mounting of the probe card to the semiconductor chip is determined by a simple means of detecting whether or not current flows between a pair of probe card alignment pad electrodes provided on the semiconductor chip. will be judged. Therefore, even when the degree of integration of semiconductor integrated circuit devices increases and the number of pads for characteristic testing increases, mounting of the probe card can be completed in a short time.

[Example] Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a plan view of a semiconductor chip showing an embodiment of the present invention applied to a gate array semiconductor integrated circuit device. According to this embodiment, the semiconductor chip unit includes a plurality of input/output buffers 2 arranged around the substrate, and a probe card for rerouting which is arranged in the internal element area 1 inside the buffers and interconnected by wiring 7. a pair of pad electrodes 3.4. Here, 5 and 6 indicate corner blocks, respectively.

This pair of alignment pad electrodes 3 and 4 is provided with an accurate relative positional relationship with other pad electrodes for testing signal input/output characteristics. A probe needle is pressed between them and a voltage is applied. At this time, if a current flows between the pad electrodes 3 and 4, it is determined that all the other needles of the probe card are also accurately hitting the pad electrodes for signal input/output characteristic testing. However, in order to obtain good alignment accuracy, the size of the pad electrodes 3.4 for alignment must be smaller than the other pad electrodes for testing signal input/output characteristics.

FIG. 2 is a plan view of a semiconductor chip showing another embodiment in which the present invention is implemented in a gate array semiconductor integrated circuit device. According to this embodiment, the pad electrode 3 for alignment.
4 are provided in corner blocks 5 and 6, respectively, and are interconnected by wiring 7 as in the previous embodiment. In this embodiment as well, the same effects as in the previous embodiment can be obtained by applying a voltage between the pad electrodes 3 and 4 for alignment and measuring the value of the current flowing at this time.

Although the present invention has been described above in a case where it is applied to a gate array semiconductor integrated circuit device, extremely great effects can be achieved if it is applied to a memory device or other highly integrated semiconductor integrated circuit device.

[Effects of the Invention] As described above in detail, according to the present invention, the probe card and Since it is possible to easily check whether the alignment is good or bad with the semiconductor chip, it is possible to have a great effect on improving the efficiency of characteristic testing.In particular, the present invention can be implemented in a gate array semiconductor integrated circuit device, and this alignment can be easily confirmed. When the pad electrodes are placed inside the corner blocks, the wiring area in the internal element area is not reduced, and alignment accuracy can be expected to improve as the alignment pad electrodes are moved farther from the center of the chip. Therefore, more significant effects can be achieved.

[Brief explanation of drawings]

FIG. 1 is a plan view of a semiconductor chip showing one embodiment of the present invention implemented in a gate array semiconductor integrated circuit device, and FIG. 2 is another embodiment of the present invention implemented in a gate array semiconductor integrated circuit device. A plan view of a semiconductor chip showing an example, and a third example is a plan view of a semiconductor chip of a conventional semiconductor integrated circuit device. lO: semiconductor chip, l: internal element area, 2: input/output buffer, 3.4: pad electrode for probe card alignment. 5.6...Corner block, 7...Wiring connecting between pad electrodes for alignment.

Claims (1)

[Claims] At least one semiconductor substrate provided with a relative positional relationship between a semiconductor substrate, an electronic circuit element region formed on the semiconductor substrate, and a pad electrode for testing the characteristics of the electronic circuit element region on the semiconductor substrate accurately defined in advance. It includes a pair of probe card alignment pad electrodes and board wiring that connects the at least one pair of probe card alignment pad electrodes, and the probe card alignment pad electrode has characteristics of the electronic circuit element by the probe card. 1. A semiconductor integrated circuit device characterized in that when a test is performed, the semiconductor integrated circuit device is used as a means for confirming the position of a probe card mounting alignment by passing a current according to a voltage supplied from a probe needle of the probe card between counter electrodes.