JPH01318245A - Probe card inspection jig - Google Patents
Probe card inspection jigInfo
- Publication number
- JPH01318245A JPH01318245A JP15275588A JP15275588A JPH01318245A JP H01318245 A JPH01318245 A JP H01318245A JP 15275588 A JP15275588 A JP 15275588A JP 15275588 A JP15275588 A JP 15275588A JP H01318245 A JPH01318245 A JP H01318245A
- Authority
- JP
- Japan
- Prior art keywords
- probe card
- pads
- amplifier
- gain
- conductive layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000523 sample Substances 0.000 title claims abstract description 28
- 238000007689 inspection Methods 0.000 title claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000012360 testing method Methods 0.000 abstract description 8
- 239000010453 quartz Substances 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 2
- 238000000206 photolithography Methods 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000011111 cardboard Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000003908 quality control method Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Measuring Leads Or Probes (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体集積回路特性試験装置と半導体集積回
路（Ｉ Ｃ）との接続に使用するプローブカードの電気
的特性を検査する際に使用する治具に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention is used to test the electrical characteristics of a probe card used to connect a semiconductor integrated circuit characteristic testing device to a semiconductor integrated circuit (IC). Regarding jigs for
従来、半導体ウェハー内に多数形成された半導体集積回
路（ＩＣ）をウェハー状態で良品、不良品を判別する検
査装置においては、半導体集積回路（ＩＣ）内の所定の
電極群に電気的に接続される探針群を備えたプローブカ
ードが使用されていた。このプローブカードは第４図に
示すようにプローブカード基板１３に出力用と入力用の
探針群２．３と半導体集積回路（ＩＣ）からの電気信号
を増幅するアンプ１とが形成された構成となっていた。Conventionally, in an inspection device that distinguishes between good and defective semiconductor integrated circuits (ICs) formed in a large number in a semiconductor wafer in the wafer state, ICs are electrically connected to a predetermined group of electrodes in the semiconductor integrated circuits (ICs). A probe card with a group of probes was used. As shown in FIG. 4, this probe card has a configuration in which a probe card group 2.3 for output and input, and an amplifier 1 for amplifying electrical signals from a semiconductor integrated circuit (IC) are formed on a probe card board 13. It became.
上述したプローブカードのアンプｌは使用されている部
品の特性、配置により周波数特性や利得が異なる。従っ
て複数の検査装置で同一品種の検査を行うためにはすべ
ての検査装置の特性が同じである必要がある。特にＩＣ
の電気信号を最初に増幅するプローブカードのアンプの
利得等の電気的特性は厳密に調整する必要がある。The amplifier l of the probe card described above has different frequency characteristics and gain depending on the characteristics and arrangement of the components used. Therefore, in order to inspect the same product type using a plurality of inspection devices, it is necessary that all the inspection devices have the same characteristics. Especially IC
It is necessary to strictly adjust the electrical characteristics such as the gain of the amplifier of the probe card that first amplifies the electrical signal.
ところが現在ではプローブカード状態でプローブカード
の電気的特性を検査するためには外部信号をプローブカ
ードに配線するなどの作業が必要で、困難である。However, currently, testing the electrical characteristics of a probe card while it is still a probe card requires work such as wiring external signals to the probe card, which is difficult.
本発明のプローブカード検査用治具は絶縁基板の一主平
面上に導電層からなる探針接触用パッド群と該パッド群
の中の所望の２つ以−Ｌのパッド間を導電層で接続しで
ある。The probe card testing jig of the present invention includes a group of probe contact pads made of a conductive layer on one principal plane of an insulating substrate, and a conductive layer connecting two or more desired pads in the pad group. It is.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図の斜視図は本発明の一実施例を示す部分拡大図で
ある。石英基板６に２μｍのＣｕ層７を形成し、フォト
リングラフィ技術を用いて所望ノ出力ピン用のパッド４
と検査すべき入力ピン用パッド５とそれらのパッドを結
線する１００μｍ幅の配線８とが形成されている。テス
ターからプローブカードの出力ピン２に既知の電圧とパ
ルス幅を持つテス）・信号を印加し、プローブカードの
入力ビン３から得られるプローブカードの出力なテスタ
自身で検査し、その結果をもとに抵抗の変更等の手段に
よりアンプの利得を調整する。The perspective view of FIG. 1 is a partially enlarged view showing one embodiment of the present invention. A 2 μm thick Cu layer 7 is formed on a quartz substrate 6, and a desired output pin pad 4 is formed using photolithography technology.
An input pin pad 5 to be inspected and a 100 μm wide wiring 8 connecting these pads are formed. A signal with a known voltage and pulse width is applied from the tester to output pin 2 of the probe card, and the output of the probe card obtained from input bin 3 of the probe card is inspected by the tester itself, and based on the result. Then, the gain of the amplifier is adjusted by means such as changing the resistance.
第２図は本発明の製法を示した工程図である。FIG. 2 is a process diagram showing the manufacturing method of the present invention.
石英基板４にＣｕ／ｌをスパッタリング法により形成し
、フォトレジスト９を塗布した後、所望の配線パターン
を露光、現像させエツチングを行った後フォトレジスト
９を除去することにより作製する。It is manufactured by forming Cu/l on a quartz substrate 4 by sputtering, applying a photoresist 9, exposing a desired wiring pattern, developing and etching, and then removing the photoresist 9.
第３図は本発明の他の実施例を示す平面図である。FIG. 3 is a plan view showing another embodiment of the present invention.
基板１０としては半導体で使用するＳｉ基板を用い、パ
ッド１１及び配線１２はＡｐ層を使用する。The substrate 10 is a Si substrate used in semiconductors, and the pads 11 and wiring 12 are made of an Ap layer.
所望のテストビンが多数ある場合には、−枚のＳｉ基板
１０に所望数のチエツクパターンを形成しステップアン
ドリピートすることによりすべてのビンを検査できる。If there are a large number of desired test bins, all the bins can be tested by forming a desired number of check patterns on two Si substrates 10 and performing step-and-repeat.
この実施例では選別するＩＣが形成されているＳｉ基板
１０と同一の基板上にチエツクパターンが形成されて（
・るためＩＣの選別時と同一条件でプローブカードのア
ンプ利得が検査できるという利点がある。In this embodiment, a check pattern is formed on the same substrate as the Si substrate 10 on which the ICs to be selected are formed (
・There is an advantage that the amplifier gain of the probe card can be tested under the same conditions as when selecting ICs.
以上説明したように、本発明のプローブカード検査用治
具を用いることにより、従来困難であったプローブカー
ドのアンプの利得を簡単に正確かつ容易に検査すること
が可能となる。As explained above, by using the probe card testing jig of the present invention, it becomes possible to simply, accurately and easily test the gain of the amplifier of the probe card, which has been difficult in the past.
その結果として出力電圧が問題となるＩＣの選別が完全
なものとなりＩＣの品質管理上有効な手段となりうる。As a result, the selection of ICs with problematic output voltages can be completed, and this can be an effective means for quality control of ICs.
第１図は本発明の一実施例の斜視図である。
第２図（ａ）〜（「）は本発明の一実施例の製法工程を
示す断面図である。
第３図は本発明の他の実施例を示す平面図である。
第４図は従来のプローブカードを示す側面図である。
１・・・・・・アンプ、２・・・・・・出力ピン、３・
・・・・・入力ビン、４・・・・・・出力ビン用パッド
、５・・・・・・入力ピン用パッド、６・・・・・・石
英基板、７・・・・・・Ｃｕ層、８・・・・・・配線、
９・・・・・・フォトレジスト、１０・・・・・・Ｓｉ
基板、１１・・・・・・Ａβパッド、１２・・・・・・
Ａｆｆ配線、１３・・・・・・プローブカード基板
代理人 弁理士 内 原 音
２ 止カビン
６゛ジ（ｑごス男パッＦ。
Ｚ石犬暮版
３ 配縁
７・ｃ１１漕
ヂ ヲントトＦシズｈ
冬Ｚ図
〆２Ａ）Ｆ礫
／ ／
７′にン７・
Ｚ出力ピン
び入力ピン
／３′フｅ−ツカーＬＡ（本夕
僅４図FIG. 1 is a perspective view of an embodiment of the present invention. FIGS. 2(a) to 2(a) are cross-sectional views showing the manufacturing process of one embodiment of the present invention. FIG. 3 is a plan view showing another embodiment of the present invention. FIG. 4 is a conventional It is a side view showing the probe card of 1... Amplifier, 2... Output pin, 3.
...Input bin, 4...Output bin pad, 5...Input pin pad, 6...Quartz substrate, 7...Cu layer, 8... wiring,
9...Photoresist, 10...Si
Substrate, 11...Aβ pad, 12...
Aff wiring, 13... Probe card board agent Patent attorney Uchi Hara Oto 2 Stop Kabin 6゛ji (q gosu man pad F. h Winter Z diagram 〆2A) F gravel / / 7'N7・Z output pin and input pin / 3'E-Tsker LA (this evening only 4 diagrams)
Claims (1)
ッド群と該パッド群の中の所望の２つ以上のパッド間を
接続する導電層とを有していることを特徴とするプロー
ブカード検査用治具。A probe comprising, on one main plane of an insulating substrate, a group of probe contact pads made of a conductive layer and a conductive layer connecting two or more desired pads in the pad group. Card inspection jig.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15275588A JPH01318245A (en) | 1988-06-20 | 1988-06-20 | Probe card inspection jig |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15275588A JPH01318245A (en) | 1988-06-20 | 1988-06-20 | Probe card inspection jig |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01318245A true JPH01318245A (en) | 1989-12-22 |
Family
ID=15547457
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15275588A Pending JPH01318245A (en) | 1988-06-20 | 1988-06-20 | Probe card inspection jig |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01318245A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003531481A (en) * | 2000-04-13 | 2003-10-21 | フォームファクター，インコーポレイテッド | Method and apparatus for testing a signal path between an integrated circuit wafer and a wafer tester |
| JP2007524837A (en) * | 2003-07-01 | 2007-08-30 | フォームファクター， インコーポレイテッド | Apparatus and method for electromechanical testing and verification of probe cards |
| CN102062847A (en) * | 2010-11-08 | 2011-05-18 | 上海集成电路研发中心有限公司 | Method for detecting semiconductor parameter measurement system |
| CN102156271A (en) * | 2011-03-15 | 2011-08-17 | 上海宏力半导体制造有限公司 | Method for detecting semiconductor parameter measuring system |
| JP2015179821A (en) * | 2014-03-19 | 2015-10-08 | 株式会社アドバンテスト | Inspection wafer and test system |
-
1988
- 1988-06-20 JP JP15275588A patent/JPH01318245A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003531481A (en) * | 2000-04-13 | 2003-10-21 | フォームファクター，インコーポレイテッド | Method and apparatus for testing a signal path between an integrated circuit wafer and a wafer tester |
| JP2007524837A (en) * | 2003-07-01 | 2007-08-30 | フォームファクター， インコーポレイテッド | Apparatus and method for electromechanical testing and verification of probe cards |
| CN102062847A (en) * | 2010-11-08 | 2011-05-18 | 上海集成电路研发中心有限公司 | Method for detecting semiconductor parameter measurement system |
| CN102156271A (en) * | 2011-03-15 | 2011-08-17 | 上海宏力半导体制造有限公司 | Method for detecting semiconductor parameter measuring system |
| JP2015179821A (en) * | 2014-03-19 | 2015-10-08 | 株式会社アドバンテスト | Inspection wafer and test system |
| US9684053B2 (en) | 2014-03-19 | 2017-06-20 | Advantest Corporation | Wafer for testing and a test system |
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