CN110277363A - Semiconductor package - Google Patents
Semiconductor package Download PDFInfo
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- CN110277363A CN110277363A CN201810486450.4A CN201810486450A CN110277363A CN 110277363 A CN110277363 A CN 110277363A CN 201810486450 A CN201810486450 A CN 201810486450A CN 110277363 A CN110277363 A CN 110277363A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000012360 testing method Methods 0.000 claims abstract description 187
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 230000000149 penetrating effect Effects 0.000 claims 1
- 230000005540 biological transmission Effects 0.000 description 13
- 238000010586 diagram Methods 0.000 description 8
- 239000000523 sample Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 229920001225 polyester resin Polymers 0.000 description 2
- 239000004645 polyester resin Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- YTCQFLFGFXZUSN-BAQGIRSFSA-N microline Chemical compound OC12OC3(C)COC2(O)C(C(/Cl)=C/C)=CC(=O)C21C3C2 YTCQFLFGFXZUSN-BAQGIRSFSA-N 0.000 description 1
- 238000006748 scratching Methods 0.000 description 1
- 230000002393 scratching effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The present invention provides a kind of semiconductor package, including flexible substrate, multiple first testing cushions, multiple second testing cushions, multiple first conducting wires, multiple second conducting wires and chip.Flexible substrate has opposite first surface and second surface, and wherein these first conducting wires are set on first surface, and these first testing cushions being set on second surface are electrically connected by multiple first conductive through holes through flexible substrate.Each second conducting wire includes the second pin being set on first surface and the connecting line that is set on second surface, and each second pin passes through the second conductive through hole through flexible substrate and connects corresponding connecting line.These second testing cushions are set on second surface, and each connecting line connects corresponding second testing cushion.Chip is set on first surface, and is electrically connected these first pins and these second pins.
Description
Technical field
The present invention relates to a kind of encapsulating structure more particularly to a kind of semiconductor packages.
Background technique
Layout area in existing membrane of flip chip (chip on film, COF) encapsulating structure is limited, to meet high pin count
And the design requirement of micro- spacing, it is only capable of further narrowing the spacing between the width of each pin and wantonly two adjacent pin, phase
The area of Ying Di, the testing cushion corresponding to pin setting can also reduce therewith.In the case where the area reduction of testing cushion, use
It is refined therewith with visiting the needle diameter of the test probe of touching testing cushion, not only increases the difficulty that test probe visits touching testing cushion, and thin
The test probe of change may be prone to wear out, bend or deviate because of structural strength deficiency, so that it is bad to derive test reliability
The problems such as being improved with testing cost.In addition, even if the area continual reductions of testing cushion must still face the limitation of minimum setting size,
This limitation is but also the spacing of pin can not reduce again, and then limit to the development of high pin count and micro- line space design.
Summary of the invention
The present invention provides a kind of semiconductor package, has splendid cloth linear elasticity.
Semiconductor package of the invention includes flexible substrate, multiple first testing cushions, multiple second testing cushions, more
A first conducting wire, multiple second conducting wires and chip.Flexible substrate has opposite first surface and the second table
Face.First surface has chip setting area, extension area and the middle area between area and extension area is arranged positioned at chip.Second table
Face has test section, and wherein test section is to being located at extension area, and test section has the first test pad area and the second test pad area, the
Area is arranged far from chip compared with the second test pad area in one test pad area.These first testing cushions are set in the first test pad area, and
These second testing cushions are set in the second test pad area.Each first conducting wire road includes the first pin and the first connection pad, and
It is set on first surface.These first connection pads are located in extension area, and each first pin extends warp from chip setting area from inside to outside
It crosses middle area and terminates at extension area, and connect corresponding first connection pad.These first connection pads align respectively be overlapped in these
One testing cushion, and be electrically connected respectively by multiple first conductive through holes of perforation extension area and test section.Each second is conductive
Route includes second pin and connecting line.These second pins are set on first surface, and with these the first pin staggered rows
Column.Each second pin extends from inside to outside from chip setting area and terminates at middle area.These connecting lines are set on second surface.
The first end of each connecting line connects corresponding second pin, and each connecting line by the second conductive through hole through flexible substrate
Second end connect corresponding second testing cushion.Chip be set to chip setting area in, and be electrically connected these first pins with
These second pins.
Based on above-mentioned, in semiconductor package of the invention, since these first pins are with these second pins
It is arranged in staggered mode, thus increases the spacing of wantonly two adjacent the first pins or wantonly two adjacent second pin, and make
These first testing cushions of these the first pins must be correspondingly connected with and be correspondingly connected with these second testing cushions of these second pins
There is biggish space to be laid out, therefore the area or size of these first testing cushions and these the second testing cushions not will receive these
The influence of first pin and the micro- pitch layout of these second pins and reduce.It is reviewed, since test section is set to pliability
The second surface of substrate, and test section is divided into the first test pad area and the second test pad area, make in the first test pad area
First testing cushion is correspondingly connected to these the first pins, and the second testing cushion in the second test pad area be correspondingly connected to these
Two pins, these first pins and these second pins are not required to cooperate these first testing cushions and these the second testing cushions
Minimum setting size limits and increases spacing, therefore can meet the design requirement of high pin count Yu micro- spacing.In addition, these first surveys
Examination pad is set to the same face of flexible substrate with these second testing cushions, can not only improve test probe detection and visit the accurate of touching
Degree and reliability, also can save the testing time.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make
Carefully it is described as follows.
Detailed description of the invention
Figure 1A is the local overlooking schematic diagram of the semiconductor package of one embodiment of the invention；
Figure 1B is the fragmentary bottom schematic diagram of the semiconductor package of Figure 1A；
Fig. 1 C is schematic partial cross-sectional view of the Figure 1A along I-I line segment；
Fig. 1 D is schematic partial cross-sectional view of the Figure 1A along II-II line segment；
Fig. 2 is the local overlooking schematic diagram of the semiconductor package of another embodiment of the present invention；
Fig. 3 is the fragmentary bottom schematic diagram of the semiconductor package of further embodiment of this invention.Drawing reference numeral explanation:
100,100a, 100b: semiconductor package 110: flexible substrate
112: first surface
112a: area is arranged in chip
112a1,112a2: long side
112b: middle area
112c: extension area
112d: test section
114: second surface
114a: test section
114a1: the first test pad area
114a2: the second test pad area
115,116: transmission range
117: transmission hole
120, the 120b: the first testing cushion
122: the first groups
130, the 130b: the second testing cushion
132: the second groups
140: the first conducting wires
141: the first pins
142: the first connection pads
143: the first conductive through holes
150: the second conducting wires
151,151a: second pin
152: the second connection pads
153: the second conductive through holes
154: third connection pad
155: connecting line
155a: first end
155b: second end
160: chip
161: the first convex blocks
162: the second convex blocks
170: third pin
180: third testing cushion
190: soldermask layer
Specific embodiment
Figure 1A is the local overlooking schematic diagram of the semiconductor package of one embodiment of the invention.Figure 1B is partly leading for Figure 1A
The fragmentary bottom schematic diagram of body encapsulating structure.Fig. 1 C is schematic partial cross-sectional view of the Figure 1A along I-I line segment.Fig. 1 D is the edge Figure 1A
The schematic partial cross-sectional view of II-II line segment.Illustrate, be laid on flexible substrate 110 route (such as pin,
Connection pad, testing cushion or other cablings) some omits and shows, does not show one by one.Figure 1A to Fig. 1 D is please referred to, in this implementation
In example, semiconductor package 100 is, for example, package structure membrane of flip chip package comprising flexible substrate 110, multiple first tests
Pad 120, multiple second testing cushions 130, multiple first conducting wires 140, multiple second conducting wires 150 and chip 160.
The material of flexible substrate 110 is, for example, the insulation of polyimides (PI), polyester resin (PET) or other deflections
Material, wherein flexible substrate 110 has opposite first surface 112 and second surface 114, and chip 160 is set to the first table
On face 112, and these first testing cushions 120 and these second testing cushions 130 are all set on second surface 114.First surface
112 centre with chip setting area 112a, extension area 112c and between chip setting area 112a and extension area 112c
Area 112b, chip 160 are set in chip setting area 112a, and each first conducting wire 140 is distinguished with each second conducting wire 150
It is electrically connected chip 160, and is extended from inside to outside from chip setting area 112a.Furthermore, each first conducting wire 140 is set
It is placed on first surface 112, and extends through middle area 112b from inside to outside from chip setting area 112a and terminate at extension area
112c.A portion of each second conducting wire 150 is set on first surface 112, and from chip setting area 112a in
Outer extension simultaneously terminates at middle area 112b.
Second surface 114 has test section 114a, and 114a contraposition in test section is overlapped in extension area 112c.These first surveys
Examination pad 120 and these second testing cushions 130 are all set in the 114a of test section, and furthermore, test section 114a can be divided into
First test pad area 114a1 and the second test pad area 114a2, wherein the first test pad area 114a1 corresponds to these the first conductions
Route 140 is arranged, and the second test pad area 114a2 is arranged corresponding to these second conducting wires 150.As shown in Figure 1B, first
Area 112a is arranged far from chip compared with the second test pad area 114a2 in test pad area 114a1, that is to say, that the first test pad area 114a1
The shortest distance between chip setting area 112a is greater than most short between the second test pad area 114a2 and chip setting area 112a
Distance.On the other hand, these first testing cushions 120 are located in the first test pad area 114a1, and these second testing cushions 130
In in the second test pad area 114a2.That is, most short between any one first testing cushion 120 and chip setting area 112a
Distance is greater than the shortest distance between any one second testing cushion 130 and chip setting area 112a.
Please continue to refer to Figure 1A to Fig. 1 D, in the present embodiment, each first conducting wire 140 include the first pin 141 with
First connection pad 142, wherein these first connection pads 142 are located in extension area 112c, and area is arranged from chip in these first pins 141
112a extends past middle area 112b from inside to outside and terminates at extension area 112c.Also, each first pin 141 can with it is corresponding
First connection pad 142 be connected.On the other hand, these first connection pads 142 on first surface 112 align respectively is overlapped in
These first testing cushions 120 on second surface 114, also, in flexible substrate 110 each first connection pad 142 with it is corresponding
120 place of overlapping of the first testing cushion be equipped with first conductive through hole 143, the perforation of each first conductive through hole 143 extends
The first test pad area 114a1 of area 112c and test section 114a are for electrically connecting to corresponding one group of first connection pad 142 and first
Testing cushion 120.Therefore, each first testing cushion 120 can pass through corresponding first conductive through hole 143 and corresponding first connection pad 142
It is electrically connected corresponding first pin 141.
Each second conducting wire 150 includes the second pin 151 being set on first surface 112, is set to first surface
It the second connection pad 152 on 112, the third connection pad 154 being set on second surface 114 and is set on second surface 114
Connecting line 155, wherein these second pins 151 and these first pins 141 are in a staggered manner along being parallel to chip setting
The direction of the long side 112a1 of area 112a arranges, that is, is laid with a second pin between wantonly two the first adjacent pin 141
151.Furthermore, these second connection pads 152 are located in the 112b of middle area, and area is arranged from chip in these second pins 151
112a extends from inside to outside and terminates at middle area 112b.Also, each second pin 151 can connect corresponding one second and connect
Pad 152.On the other hand, these second connection pads 152 on first surface 112 align this being overlapped on second surface 114 respectively
A little third connection pads 154, also, each second connection pad 152 and 154 phase of a corresponding third connection pad in flexible substrate 110
Overlapping is equipped with second conductive through hole 153, and each second conductive through hole 153 runs through flexible substrate 110 in middle area 112b,
It is for electrically connecting to corresponding one group of second connection pad 152 and third connection pad 154.
In the present embodiment, each connecting line 155 has opposite first end 155a and second end 155b, wherein each first end
155a is located at the underface of middle area 112b, and is electrically connected corresponding third connection pad 154.Therefore, each connecting line 155 can pass through
Corresponding third connection pad 154, the second conductive through hole 153 and the second connection pad 152 are electrically connected corresponding second pin 151.Respectively
Connecting line 155 extends to the second test pad area 114a2 of test section 114a from immediately below the 112b of middle area, and passes through second end
155b is electrically connected with corresponding second testing cushion 130.Therefore, each second testing cushion 130 can by corresponding connecting line 155,
Third connection pad 154, the second conductive through hole 153 and the second connection pad 152 are electrically connected corresponding second pin 151.However, in it
In his embodiment, the second conductive through hole 153 can be directly arranged at second pin 151 and corresponding connecting line 155 and overlap place, make
Each second testing cushion 130 is only and corresponding second pin by corresponding connecting line 155 and the second conductive through hole 153
151 are electrically connected, that is to say, that the setting of the second connection pad 152 and third connection pad 154 is omitted.
Please continue to refer to Figure 1A to Fig. 1 D, these first testing cushions 120 can be divided into multiple first groups 122, and these
One group 122 connects arrangement along the direction for the long side 112a1 for being parallel to chip setting area 112a.Each first group 122 includes
Multiple first testing cushions 120, and area is arranged along perpendicular to chip in these first testing cushions 120 in each first group 122
The direction of the long side 112a1 of 112a is arranged at least two rows.Each first testing cushion 120, which has, is parallel to chip setting area 112a's
The width of long side 112a1, and the overall width for the first testing cushion 120 respectively arranged in these first groups 122 near chip by setting
Area 112a is set to be gradually increased to far from chip setting area 112a.That is, being arranged in these first groups 122 further away from chip
The overall width of these the first testing cushions 120 of area 112a is greater than these first testing cushions 120 of closer chip setting area 112a
Overall width.
On the other hand, these second testing cushions 130 can be divided into multiple second groups 132, and these second groups 132 along
The direction for being parallel to the long side 112a1 of chip setting area 112a connects arrangement.Each second group 132 includes multiple second testing cushions
130, and these second testing cushions 130 in each second group 132 are along the long side 112a1's perpendicular to chip setting area 112a
Direction is arranged at least two rows.Each second testing cushion 130 has the width for the long side 112a1 for being parallel to chip setting area 112a,
And the overall width for the second testing cushion 130 respectively arranged in these second groups 132 is from being arranged area 112a to far from core near chip
Piece setting area 112a is gradually increased.That is, in these second groups 132 further away from chip setting area 112a these second
The overall width of testing cushion 130 is greater than the overall width of these the second testing cushions 130 of closer chip setting area 112a.
In the present embodiment, each first group 122 is in the direction of the long side 112a1 perpendicular to chip setting area 112a
It is upper to be correspondingly arranged with second group 132, and the quantity of these the first testing cushions 120 in each first group 122 with it is corresponding
The second group 132 in these the second testing cushions 130 quantity it is equal.
Chip 160 is set in chip setting area 112a, and is electrically connected these first pins 141, these second pins
151 and multiple third pins 170.In the present embodiment, these third pins 170 can be input pin, and these first
Pin 141 and these second pins 151 can be output pin.Specifically, chip 160 include multiple first convex blocks 161 with
And multiple second convex blocks 162, these first convex blocks 161 are along the long side 112a1 arranged adjacent of chip setting area 112a, these second
Long side 112a2 arranged adjacent of the convex block 162 along chip setting area 112a.Chip 160 is set to flexible base in a manner of flip
On material 110, so that each first convex block 161 is engaged in corresponding first pin 141 or corresponding second pin 151, and each
Two convex blocks 162 are engaged in corresponding third pin 170.
Referring again to Figure 1A, the first surface 112 of flexible substrate 110 also has test section 112d, wherein test section
112d and extension area 112c is located at the opposite sides of chip 160.These third pins 170 from chip setting area 112a in
Outer extension and terminate at test section 112d, and multiple third testing cushions 180 in the 112d of test section are electrically connected.In
When test is electrical, electric signal is, for example, to input from these third testing cushions 180, then visited with probe and touch these first testing cushions 120
It is whether normal with the electric signal for testing output with these the second testing cushions 130.
On the other hand, flexible substrate 110 also has opposite two transmission ranges 115,116 and multiple transmission holes 117,
In these transmission holes 117 be located in transmission range 115 and 116, and run through flexible substrate 110.These transmission holes 117 along
Perpendicular to chip setting area 112a long side 112a1 direction arrangement, and the configuration of these transmission holes 117 to transmission mechanism
Cooperate and drives flexible substrate 110 mobile.However, two transmission ranges 115,116 of flexible substrate 110 are to form semiconductor
During encapsulating structure 100, for convenience of the mechanism that transmission drives flexible substrate 110 and uses.Work as semiconductor package
After 100 complete, the flexible substrate 110 of semiconductor package 100 can be separated with two transmission ranges 115,116.
In addition, please referring to Fig. 1 C and Fig. 1 D, semiconductor package 100 further includes multiple soldermask layers 190, is respectively arranged at
On the first surface 112 and second surface 114 of flexible substrate 110.Specifically, these soldermask layers 190 are covered each by part
First pin 141, part second pin 150, part third pin 170, the second connection pad 152, third connection pad 154 and part connect
Wiring 155, to protect these electrical transmission lines, avoid because scratching, foreign matter attachment or due to other factors caused by electrical short,
Breaking phenomena.It illustrates, for the technology of the present invention content can be clearly described, display soldermask layer 190 is omitted in Figure 1A and Figure 1B.
Such as the mode of above-mentioned route arrangement, being with these second pins 151 due to these first pins 141 is in staggered side
Formula arrangement, thus increases the spacing of wantonly two adjacent the first pins 141 or wantonly two adjacent second pin 151, and makes pair
These first testing cushions 120 of these the first pins 141 should be connected and be correspondingly connected with these second surveys of these second pins 151
Examination pad 130 has biggish space to be laid out, therefore the area or ruler of these first testing cushions 120 and these the second testing cushions 130
The very little influence that not will receive these first pins 141 and these micro- pitch layouts of second pin 151 and reduce.It is reviewed, due to
Test section 114a is set to the second surface 114 of flexible substrate 110, and test section 114a is divided into the first test pad area
114a1 and the second test pad area 114a2, make the first testing cushion 120 in the first test pad area 114a1 be correspondingly connected to these
One pin 141, and the second testing cushion 130 in the second test pad area 114a2 is correspondingly connected to these second pins 151, these
First pin 141 is not required to these second pins 151 in order to cooperate these first testing cushions 120 and these second testing cushions 130
Minimum setting size limit and increase spacing, therefore the design requirement of high pin count Yu micro- spacing can be met.In addition, these first
Testing cushion 120 and these second testing cushions 130 are set to the same face of flexible substrate 110, can not only improve test probe and visit
The accuracy and reliability of probing touching, also can save the testing time.
Other embodiments will be enumerated below using as explanation.It should be noted that, following embodiments continue to use aforementioned reality herein
The element numbers and partial content of example are applied, wherein adopting the identical or approximate element that is denoted by the same reference numerals, and are omitted
The explanation of same technique content.Explanation about clipped can refer to previous embodiment, and following embodiment will not be repeated herein.
Fig. 2 is the local overlooking schematic diagram of the semiconductor package of another embodiment of the present invention.Referring to figure 2., Fig. 2
The main difference of the semiconductor package 100 of semiconductor package 100a and Figure 1A is: each second pin 151a extends
To the line of demarcation of middle area 112b and extension area 112c, and terminate at this line of demarcation.Furthermore, in each second pin 151a
Extends from inside to outside from chip setting area 112a and with after corresponding second connection pad 152 is connected in the 112b of middle area, each the
The line of demarcation that two pin 151a are continued towards middle area 112b and extension area 112c extends, and terminates at this line of demarcation.Whereby, exist
It completes after testing and cutting test section 114a, the end of these first pins 141 and these second pins 151a all terminates at
Identical position.For subsequent outer pin connection process, i.e., with the end of these first pins 141 and these second pins 151a
Portion connects the terminal of outer member, and the configuration of the present embodiment can simplify connection process and reduce the design complexity of outer member terminal
Degree.
Fig. 3 is the fragmentary bottom schematic diagram of the semiconductor package of further embodiment of this invention.Referring to figure 3., Fig. 3
The main difference of the semiconductor package 100 of semiconductor package 100b and Figure 1B is: in each first group 122 extremely
A few row has two the first testing cushion 120b being symmetrically arranged, and at least row in each second group 132 has symmetrical row
Two the second testing cushion 130b of column.Furthermore, symmetric arrays and the two rows of first surveys in each first group 122
Examination pad 120b compared with other the first testing cushion 120b far from chip be arranged area 112a, and in each second group 132 be symmetrically arranged and at
Area 112a is arranged far from chip compared with other the second testing cushion 130b in the two second testing cushion 130b of row.Based on above-mentioned route cloth
If mode, the space of second surface 114 can be made full use of these the first testing cushion 120b and these second testing cushions are arranged
130b.It illustrates, the present embodiment is not intended to limit the number of rows of the testing cushion of symmetric arrays, in other embodiments, symmetrically
The number of rows of the testing cushion of arrangement can be multiple rows of.
In conclusion in semiconductor package of the invention, since these first pins are with these second pins
It is arranged in staggered mode, thus increases the spacing of wantonly two adjacent the first pins or wantonly two adjacent second pin, and make
These first testing cushions of these the first pins must be correspondingly connected with and be correspondingly connected with these second testing cushions of these second pins
There is biggish space to be laid out, therefore the area or size of these first testing cushions and these the second testing cushions not will receive these
The influence of first pin and the micro- pitch layout of these second pins and reduce.It is reviewed, since test section is set to pliability
The second surface of substrate, and test section is divided into the first test pad area and the second test pad area, make in the first test pad area
First testing cushion is correspondingly connected to these the first pins, and the second testing cushion in the second test pad area be correspondingly connected to these
Two pins, these first pins and these second pins are not required to cooperate these first testing cushions and these the second testing cushions
Minimum setting size limits and increases spacing, therefore can meet the design requirement of high pin count Yu micro- spacing.In addition, these first surveys
Examination pad is set to the same face of flexible substrate with these second testing cushions, can not only improve test probe detection and visit the accurate of touching
Degree and reliability, also can save the testing time.
Although the present invention is disclosed as above with embodiment, however, it is not to limit the invention, any technical field
Middle technical staff, without departing from the spirit and scope of the present invention, when can make a little change and retouching, therefore protection of the invention
Subject to range ought be defined depending on claim.
Claims (10)
1. a kind of semiconductor package characterized by comprising
Flexible substrate, has opposite first surface and second surface, and there is the first surface chip area, extension area is arranged
And the middle area between area and the extension area is set positioned at the chip, the second surface has test section, wherein institute
Test section is stated to being located at the extension area, and the test section has the first test pad area and the second test pad area, described first
Area is arranged far from the chip in test pad area second test pad area；
Multiple first testing cushions are set in first test pad area；
Multiple second testing cushions are set in second test pad area；
Multiple first conducting wires, each of the multiple first conducting wire includes the first pin and the first connection pad, and is arranged
In on the first surface, the multiple first connection pad is located in the extension area, the multiple first pin it is each from institute
It states chip setting area to extend past the middle area from inside to outside and terminate at the extension area, and connects corresponding described first and connect
Pad, the multiple first connection pad aligns respectively is overlapped in the multiple first testing cushion, and respectively by penetrating through the extension area
It is electrically connected with multiple first conductive through holes of the test section；
Multiple second conducting wires, the multiple second conducting wire it is each include second pin and connecting line, it is the multiple
Second pin is set on the first surface, and is staggered with the multiple first pin, the multiple second pin
Each to extend and terminate at the middle area from inside to outside from chip setting area, the multiple connecting line is set to described second
On surface, each first end of the multiple connecting line passes through the second conductive through hole connection pair through the flexible substrate
The second pin answered, and each second end of the multiple connecting line connects corresponding second testing cushion；And
Chip is set in chip setting area, and is electrically connected the multiple first pin and the multiple second pin.
2. semiconductor package according to claim 1, which is characterized in that chip setting area has opposite two
A long side, and the multiple first pin and the multiple second pin are in a staggered manner along being parallel to two long sides
Direction arrangement.
3. semiconductor package according to claim 2, which is characterized in that the multiple first testing cushion is divided into multiple
First group, the multiple first group connect along the direction for being parallel to two long sides and arrange, and the multiple first group
Group it is each in the multiple first testing cushion be arranged at least two rows along the direction perpendicular to two long sides.
4. semiconductor package according to claim 3, which is characterized in that each tool of the multiple first testing cushion
It is parallel to the width of two long sides, the overall width for the multiple first testing cushion respectively arranged in the multiple first group
It is gradually increased from area is arranged near the chip to far from chip setting area.
5. semiconductor package according to claim 3, which is characterized in that the multiple first group it is each in most
An at least row far from chip setting area has two first testing cushions being symmetrically arranged.
6. semiconductor package according to claim 3, which is characterized in that the multiple second testing cushion is divided into multiple
Second group, the multiple second group connect along the direction for being parallel to two long sides and arrange, and the multiple second group
Group it is each in the multiple second testing cushion be arranged at least two rows along the direction perpendicular to two long sides.
7. semiconductor package according to claim 6, which is characterized in that each tool of the multiple second testing cushion
It is parallel to the width of two long sides, the overall width for the multiple second testing cushion respectively arranged in the multiple second group
It is gradually increased from area is arranged near the chip to far from chip setting area.
8. semiconductor package according to claim 6, which is characterized in that the multiple second group it is each in most
An at least row far from chip setting area has two second testing cushions being symmetrically arranged.
9. semiconductor package according to claim 6, which is characterized in that the multiple first group respectively corresponds institute
State the setting of multiple second groups, and the multiple first group it is each in the multiple first testing cushion quantity with it is corresponding
Second group in the multiple second testing cushion quantity it is equal.
10. semiconductor package according to claim 1, which is characterized in that each company of the multiple second pin
The second connection pad positioned at the middle area is connect, each first end of the multiple connecting line connects third connection pad, described
Multiple second connection pads align respectively is overlapped in the multiple third connection pad, and each and corresponding institute of the multiple second connection pad
Third connection pad is stated to be connected by corresponding second conductive through hole.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW107109150 | 2018-03-16 | ||
| TW107109150A TWI700797B (en) | 2018-03-16 | 2018-03-16 | Semiconductor package structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
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| CN110611989A (en) * | 2019-10-29 | 2019-12-24 | 业成科技（成都）有限公司 | Circuit board and electronic device |
| CN111508931A (en) * | 2020-04-20 | 2020-08-07 | 京东方科技集团股份有限公司 | Display panel and manufacturing method thereof |
| CN113594126A (en) * | 2020-04-30 | 2021-11-02 | 南茂科技股份有限公司 | Flexible circuit substrate and chip-on-film package structure |
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| CN113594126A (en) * | 2020-04-30 | 2021-11-02 | 南茂科技股份有限公司 | Flexible circuit substrate and chip-on-film package structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110277363B (en) | 2021-05-04 |
| TW201939697A (en) | 2019-10-01 |
| TWI700797B (en) | 2020-08-01 |
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