TWI700797B - Semiconductor package structure - Google Patents

Abstract

A semiconductor package structure includes a flexible substrate, a plurality of first test pads, a plurality of second test pads, a plurality of first conductive circuits, a plurality of second conductive circuits, and a chip. The flexible substrate has a first surface and a second surface opposite to each other, wherein the first conductive circuits are disposed on the first surface and are electrically connected to the first test pads disposed on the second surface respectively through a plurality of first conductive vias penetrating the flexible substrate. Each of the second conductive circuits includes a second lead disposed on the first surface and a connecting line disposed on the second surface, and each of the second leads is connected to the corresponding connecting line through a second conductive via penetrating the flexible substrate. The second test pads are disposed on the second surface, and each of the connecting lines is connected to the corresponding second test pad. The chip is disposed on the first surface and electrically connected to the first leads and the second leads.

Description

Semiconductor package structure

The present invention relates to a packaging structure, and more particularly to a semiconductor packaging structure.

The wiring area in the current chip on film (COF) package structure is limited. In order to meet the design requirements of high pin count and fine pitch, the width of each pin can only be adjusted between any two adjacent pins. The distance between the two is further narrowed, and accordingly, the area of the test pad corresponding to the pin setting will also be reduced. When the area of the test pad is reduced, the needle diameter of the test probe used to probe the test pad will be refined, which not only increases the difficulty of the test probe to touch the test pad, but also the refined test probe may be Insufficient structural strength makes it easy to wear, bend or deviate, resulting in problems such as poor test reliability and increased test costs. In addition, even if the area of the test pad continues to shrink, it still has to face the limitation of the minimum setting size. This limitation also prevents the pin spacing from being reduced, which limits the development of high pin count and fine pitch designs.

The invention provides a semiconductor package structure with excellent wiring flexibility.

The semiconductor package structure of the present invention includes a flexible substrate, a plurality of first test pads, a plurality of second test pads, a plurality of first conductive circuits, a plurality of second conductive circuits, and a chip. The flexible substrate has a first surface and a second surface opposite to each other. The first surface has a wafer setting area, an extension area, and an intermediate area between the wafer setting area and the extension area. The second surface has a test area, wherein the test area pair is located in the extension area, and the test area has a first test pad area and a second test pad area, and the first test pad area is farther from the wafer setting area than the second test pad area. The first test pads are arranged in the first test pad area, and the second test pads are arranged in the second test pad area. Each first conductive circuit path includes a first pin and a first pad, and is disposed on the first surface. The first pads are located in the extension area, and each first pin extends from the chip placement area through the middle area to terminate in the extension area, and is connected to the corresponding first pad. The first pads are respectively aligned and overlapped on the first test pads, and are electrically connected through a plurality of first conductive vias that penetrate the extension area and the test area, respectively. Each second conductive circuit includes a second pin and a connecting wire. The second pins are arranged on the first surface and are arranged alternately with the first pins. Each second pin extends outward from the chip setting area and terminates in the middle area. These connecting lines are arranged on the second surface. The first end of each connecting wire is connected to the corresponding second pin through the second conductive through hole penetrating the flexible substrate, and the second end of each connecting wire is connected to the corresponding second test pad. The chip is arranged in the chip arrangement area, and is electrically connected to the first pins and the second pins.

Based on the above, in the semiconductor package structure of the present invention, since the first pins and the second pins are arranged in a staggered manner, any two adjacent first pins or any two adjacent ones are enlarged. The distance between the second pins is such that the first test pads corresponding to the first pins and the second test pads corresponding to the second pins have a larger space for layout. Therefore, the first test pads The area or size of the second test pads will not be reduced due to the influence of the fine pitch layout of the first pins and the second pins. Conversely, because the test area is arranged on the second surface of the flexible substrate and the test area is divided into the first test pad area and the second test pad area, the first test pad in the first test pad area corresponds to Connected to these first pins, and the second test pads in the second test pad area are correspondingly connected to these second pins. These first pins and these second pins do not need to match the first test pads and The minimum setting size of these second test pads is limited and the spacing is increased, so the design requirements for high pin count and fine spacing can be met. In addition, the first test pads and the second test pads are arranged on the same surface of the flexible substrate, which can not only improve the accuracy and reliability of detection by the test probe, but also save test time.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

FIG. 1A is a schematic partial top view of a semiconductor package structure according to an embodiment of the invention. FIG. 1B is a schematic partial bottom view of the semiconductor package structure of FIG. 1A. Figure 1C is a schematic partial cross-sectional view of Figure 1A along the line I-I'. Fig. 1D is a schematic partial cross-sectional view of Fig. 1A along the line II-II'. It is particularly noted that some of the circuits (such as pins, pads, test pads or other traces) arranged on the flexible substrate 110 are omitted from the drawing, and are not shown one by one. 1A to FIG. 1D, in this embodiment, the semiconductor package structure 100 is, for example, a film-on-chip package structure, which includes a flexible substrate 110, a plurality of first test pads 120, and a plurality of second test pads 130 , A plurality of first conductive circuits 140, a plurality of second conductive circuits 150 and a chip 160.

The material of the flexible substrate 110 is, for example, polyimide (PI), polyester resin (PET) or other flexible insulating materials. The flexible substrate 110 has a first surface 112 and a second surface 112 opposite to each other. On the surface 114, the wafer 160 is disposed on the first surface 112, and the first test pads 120 and the second test pads 130 are all disposed on the second surface 114. The first surface 112 has a wafer setting area 112a, an extension area 112c, and an intermediate area 112b between the wafer setting area 112a and the extension area 112c. The wafer 160 is provided in the wafer setting area 112a, and each first conductive circuit 140 and each second The conductive lines 150 are respectively electrically connected to the chip 160 and extend outward from the chip setting area 112a. Furthermore, each of the first conductive lines 140 is disposed on the first surface 112, and extends from the wafer setting area 112a to the outside through the middle area 112b and terminates at the extension area 112c. A part of each second conductive circuit 150 is disposed on the first surface 112, and extends from the wafer setting area 112a to the outside and ends in the middle area 112b.

The second surface 114 has a test area 114a, and the test area 114a aligns and overlaps the extension area 112c. The first test pads 120 and the second test pads 130 are all disposed in the test area 114a. Further, the test area 114a can be divided into a first test pad area 114a1 and a second test pad area 114a2. The first test pad The area 114a1 is provided corresponding to the first conductive lines 140, and the second test pad area 114a2 is provided corresponding to the second conductive lines 150. As shown in FIG. 1B, the first test pad area 114a1 is farther from the wafer setting area 112a than the second test pad area 114a2, that is, the shortest distance between the first test pad area 114a1 and the wafer setting area 112a is greater than that of the second test pad The shortest distance between the area 114a2 and the wafer setting area 112a. On the other hand, the first test pads 120 are located in the first test pad area 114a1, and the second test pads 130 are located in the second test pad area 114a2. That is, the shortest distance between any one of the first test pads 120 and the wafer setting area 112a is greater than the shortest distance between any of the second test pads 130 and the wafer setting area 112a.

Please continue to refer to FIGS. 1A to 1D. In this embodiment, each first conductive circuit 140 includes a first pin 141 and a first pad 142. The first pads 142 are located in the extension area 112c, and the first conductive lines 140 A pin 141 extends from the inside of the wafer placement area 112a to the outside through the middle area 112b and terminates at the extension area 112c. In addition, each first pin 141 is connected to a corresponding first pad 142. On the other hand, the first pads 142 on the first surface 112 are respectively aligned with the first test pads 120 on the second surface 114, and each of the first pads 142 in the flexible substrate 110 A first conductive via 143 is provided where it overlaps with a corresponding first test pad 120. Each first conductive via 143 penetrates through the extension area 112c and the first test pad area 114a1 of the test area 114a for electrical connection A corresponding set of first pads 142 and first test pads 120. Therefore, each first test pad 120 can be electrically connected to the corresponding first pin 141 through the corresponding first conductive via 143 and the corresponding first pad 142.

Each second conductive circuit 150 includes a second pin 151 disposed on the first surface 112, a second pad 152 disposed on the first surface 112, a third pad 154 disposed on the second surface 114, and The connecting lines 155 on the second surface 114, in which the second pins 151 and the first pins 141 are arranged in a staggered manner along a direction parallel to the long side 112a1 of the chip placement area 112a, that is, any two phases A second pin 151 is arranged between adjacent first pins 141. Furthermore, the second pads 152 are located in the middle area 112b, and the second pins 151 extend outward from the chip placement area 112a and terminate in the middle area 112b. Moreover, each second pin 151 is connected to a corresponding second pad 152. On the other hand, the second pads 152 on the first surface 112 are respectively aligned with the third pads 154 on the second surface 114, and each of the second pads 152 in the flexible substrate 110 A second conductive through hole 153 is provided where it overlaps with a corresponding third pad 154, and each second conductive through hole 153 penetrates the flexible substrate 110 in the middle area 112b to electrically connect a corresponding set The second pad 152 and the third pad 154.

In this embodiment, each connecting wire 155 has a first end 155a and a second end 155b opposite to each other. Each first end 155a is located directly under the middle region 112b and is electrically connected to the corresponding third pad 154. Therefore, each connecting wire 155 can be electrically connected to the corresponding second pin 151 through the corresponding third pad 154, the second conductive via 153, and the second pad 152. Each connection line 155 extends from directly below the middle area 112b to the second test pad area 114a2 of the test area 114a, and is electrically connected to the corresponding second test pad 130 through the second end 155b. Therefore, each second test pad 130 can be electrically connected to the corresponding second pin 151 through the corresponding connecting wire 155, the third pad 154, the second conductive via 153, and the second pad 152. However, in other embodiments, the second conductive via 153 can be directly provided where the second pin 151 overlaps the corresponding connection line 155, so that each second test pad 130 only passes through the corresponding connection line 155 and the second The conductive via 153 is electrically connected to the corresponding second pin 151, that is, the arrangement of the second pad 152 and the third pad 154 is omitted.

Please continue to refer to FIGS. 1A to 1D. The first test pads 120 can be divided into a plurality of first groups 122, and the first groups 122 are successively arranged along a direction parallel to the long side 112a1 of the chip arrangement area 112a. Each first group 122 includes a plurality of first test pads 120, and the first test pads 120 in each first group 122 are arranged in at least two rows along a direction perpendicular to the long side 112a1 of the wafer placement area 112a. Each of the first test pads 120 has a width parallel to the long side 112a1 of the wafer placement area 112a, and the total width of the first test pads 120 in each row in the first group 122 is set from the closest to the wafer placement area 112a to away from the wafer. The area 112a gradually increases. That is to say, the total width of the first test pads 120 farther from the wafer placement area 112a in the first groups 122 is larger than the total width of the first test pads 120 closer to the wafer placement area 112a.

On the other hand, the second test pads 130 can be divided into a plurality of second groups 132, and the second groups 132 are successively arranged along a direction parallel to the long side 112a1 of the chip arrangement area 112a. Each second group 132 includes a plurality of second test pads 130, and the second test pads 130 in each second group 132 are arranged in at least two rows along a direction perpendicular to the long side 112a1 of the chip arrangement area 112a. Each second test pad 130 has a width parallel to the long side 112a1 of the wafer placement area 112a, and the total width of the second test pads 130 in each row in the second group 132 is set from the closest to the wafer placement area 112a to away from the wafer The area 112a gradually increases. That is to say, the total width of the second test pads 130 farther from the wafer placement area 112a in the second groups 132 is greater than the total width of the second test pads 130 closer to the wafer placement area 112a.

In this embodiment, each first group 122 is arranged corresponding to a second group 132 in a direction perpendicular to the long side 112a1 of the chip arrangement area 112a, and these first tests in each first group 122 The number of the pads 120 is equal to the number of the second test pads 130 in the corresponding second group 132.

The chip 160 is disposed in the chip setting area 112a, and is electrically connected to the first pins 141, the second pins 151, and the third pins 170. In this embodiment, the third pins 170 may be input pins, and the first pins 141 and the second pins 151 may be output pins. Specifically, the wafer 160 includes a plurality of first bumps 161 and a plurality of second bumps 162. The first bumps 161 are arranged adjacently along the long side 112a1 of the wafer setting area 112a, and the second bumps 162 are arranged along the wafer. The long sides 112a2 of the setting area 112a are arranged adjacently. The chip 160 is disposed on the flexible substrate 110 in a flip-chip manner, so that each first bump 161 is bonded to the corresponding first pin 141 or the corresponding second pin 151, and each second bump 162 Connected to the corresponding third pin 170.

1A again, the first surface 112 of the flexible substrate 110 also has a test area 112d, wherein the test area 112d and the extension area 112c are located on opposite sides of the chip 160, respectively. The third pins 170 extend outward from the chip placement area 112a and terminate at the test area 112d, and are electrically connected to the plurality of third test pads 180 located in the test area 112d, respectively. When testing electrical properties, for example, electrical signals are input from the third test pads 180, and then probes are used to probe the first test pads 120 and the second test pads 130 to test whether the output electrical signals are normal.

On the other hand, the flexible substrate 110 also has two opposite transmission regions 115 and 116 and a plurality of transmission holes 117, wherein the transmission holes 117 are respectively located in the transmission regions 115 and 116 and penetrate the flexible substrate 110. The transmission holes 117 are arranged along a direction perpendicular to the long side 112a1 of the wafer setting area 112a, and the transmission holes 117 are configured to cooperate with the transmission mechanism to drive the flexible substrate 110 to move. However, the two transmission regions 115 and 116 of the flexible substrate 110 are mechanisms used to facilitate the transmission and drive the flexible substrate 110 during the process of forming the semiconductor packaging structure 100. After the semiconductor packaging structure 100 is completed, the flexible substrate 110 of the semiconductor packaging structure 100 can be separated from the two transmission regions 115 and 116.

In addition, referring to FIGS. 1C and 1D, the semiconductor package structure 100 further includes a plurality of solder mask layers 190, which are respectively disposed on the first surface 112 and the second surface 114 of the flexible substrate 110. Specifically, these solder masks 190 respectively cover a part of the first pin 141, a part of the second pin 150, a part of the third pin 170, the second pad 152, the third pad 154 and part of the connection Line 155 is used to protect these electrical transmission lines and avoid electrical short-circuits and open circuits caused by scratches, foreign matter adhesion, or other factors. In particular, in order to clearly describe the technical content of the present invention, the solder mask 190 is omitted in FIGS. 1A and 1B.

As with the above-mentioned wiring layout, since the first pins 141 and the second pins 151 are arranged in a staggered manner, any two adjacent first pins 141 or any two adjacent second pins 141 are enlarged. The distance between the pins 151 is such that the first test pads 120 corresponding to the first pins 141 and the second test pads 130 corresponding to the second pins 151 have a larger space for layout. The area or size of a test pad 120 and the second test pads 130 will not be reduced due to the influence of the fine-pitch layout of the first pins 141 and the second pins 151. In contrast, since the test area 114a is disposed on the second surface 114 of the flexible substrate 110, and the test area 114a is divided into the first test pad area 114a1 and the second test pad area 114a2, the first test pad area 114a1 The first test pad 120 in the second test pad area 114a2 is correspondingly connected to the first pins 141, and the second test pad 130 in the second test pad area 114a2 is correspondingly connected to the second pins 151. The first pins 141 are connected to the first pins 151. The two pins 151 do not need to increase the spacing in order to meet the minimum size limitation of the first test pads 120 and the second test pads 130, so the design requirements of high pin count and fine spacing can be met. In addition, the first test pads 120 and the second test pads 130 are disposed on the same surface of the flexible substrate 110, which not only improves the accuracy and reliability of the detection of the test probe, but also saves test time.

Other embodiments will be listed below for description. It must be noted here that the following embodiments use the element numbers and part of the content of the foregoing embodiments, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

2 is a schematic partial top view of a semiconductor package structure according to another embodiment of the invention. Please refer to FIG. 2. The main difference between the semiconductor package structure 100a of FIG. 2 and the semiconductor package structure 100 of FIG. 1A is that each second pin 151a extends to the boundary between the middle region 112b and the extension region 112c, and terminates at the boundary . Furthermore, after each second pin 151a extends outward from the chip placement area 112a and is connected to the corresponding second pad 152 located in the middle area 112b, each second pin 151a continues to extend toward the middle area 112b and The boundary of the area 112c extends and ends at this boundary. Thus, after the test is completed and the test area 114a is cut off, the ends of the first pins 141 and the second pins 151a all terminate at the same position. For the subsequent external pin bonding process, that is, the ends of the first pins 141 and the second pins 151a are used to connect the terminals of the external components, the configuration of this embodiment can simplify the bonding process and reduce the complexity of the external component terminal design. degree.

3 is a schematic partial bottom view of a semiconductor package structure according to another embodiment of the present invention. 3, the main difference between the semiconductor package structure 100b of FIG. 3 and the semiconductor package structure 100 of FIG. 1B is that at least one row in each first group 122 has two first test pads 120b arranged symmetrically, and each At least one row in the second group 132 has two second test pads 130b arranged symmetrically. Further, the two first test pads 120b arranged symmetrically and in rows in each first group 122 are farther away from the chip placement area 112a than the other first test pads 120b, and each second group 132 is symmetrically arranged and arranged The two second test pads 130b in the row are farther away from the wafer placement area 112a than the other second test pads 130b. Based on the above-mentioned wiring arrangement method, the space of the second surface 114 can be fully utilized to arrange the first test pads 120b and the second test pads 130b. It is particularly noted that this embodiment does not limit the number of rows of test pads arranged symmetrically. In other embodiments, the number of rows of test pads arranged symmetrically may be multiple rows.

In summary, in the semiconductor package structure of the present invention, since the first pins and the second pins are arranged in a staggered manner, any two adjacent first pins or any two phases are enlarged. The distance between the adjacent second pins and the first test pads corresponding to the first pins and the second test pads corresponding to the second pins have a larger space for layout. Therefore, these first The area or size of the test pads and the second test pads will not be reduced due to the influence of the fine-pitch layout of the first pins and the second pins. Conversely, because the test area is arranged on the second surface of the flexible substrate and the test area is divided into the first test pad area and the second test pad area, the first test pad in the first test pad area corresponds to Connected to these first pins, and the second test pads in the second test pad area are correspondingly connected to these second pins. These first pins and these second pins do not need to match the first test pads and The minimum setting size of these second test pads is limited and the spacing is increased, so the design requirements for high pin count and fine spacing can be met. In addition, the first test pads and the second test pads are arranged on the same surface of the flexible substrate, which can not only improve the accuracy and reliability of detection by the test probe, but also save test time.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make slight changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

100, 100a, 100b‧‧‧Semiconductor package structure 110‧‧‧Flexible substrate 112‧‧‧First surface 112a‧‧‧Chip setting area 112a1, 112a2‧‧‧Long side 112b‧‧‧Middle area 112c‧ ‧‧Extension zone 112d‧‧‧Test zone 114‧‧‧Second surface 114a‧‧‧Test zone 114a1‧‧‧First test pad zone 114a2‧‧‧Second test pad zone 115, 116‧‧‧Transmission zone 117 ‧‧‧Transmission hole 120, 120b‧‧‧First test pad 122‧‧‧First group 130,130b‧‧‧Second test pad 132‧‧‧Second group 140‧‧‧First conductive circuit 141 ‧‧‧First pin 142‧‧‧First pad 143‧‧‧First conductive via 150‧‧‧Second conductive line 151, 151a‧‧‧Second pin 152‧‧‧Second pad 153‧‧‧Second conductive via 154‧‧‧Third pad 155‧‧‧Connecting line 155a‧‧‧First end 155b‧‧‧Second end 160‧‧‧Chip 161‧‧‧First bump 162‧‧‧Second bump 170‧‧‧Third pin 180‧‧‧Third test pad 190‧‧‧Solder mask

FIG. 1A is a schematic partial top view of a semiconductor package structure according to an embodiment of the invention. FIG. 1B is a schematic partial bottom view of the semiconductor package structure of FIG. 1A. Figure 1C is a schematic partial cross-sectional view of Figure 1A along the line I-I'. Fig. 1D is a schematic partial cross-sectional view of Fig. 1A along the line II-II'. 2 is a schematic partial top view of a semiconductor package structure according to another embodiment of the invention. 3 is a schematic partial bottom view of a semiconductor package structure according to another embodiment of the present invention.

100‧‧‧Semiconductor package structure

110‧‧‧Flexible substrate

112‧‧‧First Surface

112a‧‧‧Chip setting area

112a1, 112a2‧‧‧long side

112b‧‧‧Middle area

112c‧‧‧Extension Area

112d‧‧‧Test area

115, 116‧‧‧Transmission area

117‧‧‧Transmission hole

130‧‧‧Second Test Pad

140‧‧‧First conductive circuit

141‧‧‧First pin

142‧‧‧First pad

143‧‧‧First conductive via

150‧‧‧Second conductive circuit

151‧‧‧Second pin

152‧‧‧Second pad

153‧‧‧Second conductive via

155‧‧‧Connecting line

160‧‧‧chip

170‧‧‧Third pin

180‧‧‧Third test pad

Claims (8)

A semiconductor packaging structure includes: a flexible substrate having a first surface and a second surface opposite to each other, the first surface having a wafer setting area, an extension area, and being located between the wafer setting area and the extension area An intermediate area between the second surface, the second surface has a test area, wherein the test area is located in the extension area, and the test area has a first test pad area and a second test pad area, the first test pad The area is farther away from the chip setting area than the second test pad area; a plurality of first test pads are arranged in the first test pad area; a plurality of second test pads are arranged in the second test pad area; The first conductive circuit, each of the first conductive circuit includes a first pin and a first pad, and is disposed on the first surface, the first pads are located in the extension area, and each of the first leads The pins extend outward from the chip placement area, pass through the intermediate area, and terminate at the extension area, and are connected to the corresponding first pads. The first pads are aligned and overlapped on the first test pads, and respectively Are electrically connected through a plurality of first conductive vias penetrating the extension area and the test area; a plurality of second conductive lines, each of the second conductive lines includes a second pin and a connecting line, the second The pins are arranged on the first surface and alternately arranged with the first pins. Each of the second pins extends outward from the chip arrangement area and terminates in the middle area. The connecting lines are arranged on the first On the two surfaces, a first end of each connecting line is connected to the corresponding second pin through a second conductive through hole penetrating the flexible substrate, and a second end of each connecting line is connected to the corresponding The second test pad; and a chip arranged in the chip setting area and electrically connected to the first pins With the second pins, the chip arrangement area has two opposite long sides, and the first pins and the second pins are arranged in a staggered manner along a direction parallel to each of the long sides , The first test pads are divided into a plurality of first groups, the first groups are successively arranged along a direction parallel to each of the long sides, and the first test pads in each first group are along Arranged in at least two rows along the direction perpendicular to each of the long sides. The semiconductor package structure described in claim 1, wherein each of the first test pads has a width parallel to each of the long sides, and the total of the first test pads in each row in the first groups The width gradually increases from the closest to the wafer placement area to the farther away from the wafer placement area. According to the semiconductor package structure described in claim 1, wherein at least one row of each of the first groups farthest from the chip placement area has two first test pads arranged symmetrically. According to the semiconductor package structure described in claim 1, wherein the second test pads are divided into a plurality of second groups, and the second groups are successively arranged along a direction parallel to each long side, each The second test pads in the second group are arranged in at least two rows along a direction perpendicular to each of the long sides. According to the semiconductor package structure described in claim 4, each of the second test pads has a width parallel to each of the long sides, and the total of the second test pads in each row in the second groups The width gradually increases from the closest to the wafer placement area to the farther away from the wafer placement area. According to the semiconductor package structure described in claim 4, in each of the second groups, at least one row farthest from the chip placement area has two second test pads arranged symmetrically. As for the semiconductor package structure described in claim 4, the first groups are arranged corresponding to the second groups, and the number of the first test pads in each first group corresponds to The number of the second test pads in the second group is equal. According to the semiconductor package structure described in claim 1, wherein each of the second pins is connected to a second pad located in the middle area, and the first end of each of the connecting lines is connected to a third pad, the The second pads are aligned and overlapped with the third pads, and each of the second pads is connected to the corresponding third pad through the corresponding second conductive via.

Images