CN113963622B - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN113963622B CN113963622B CN202111314946.1A CN202111314946A CN113963622B CN 113963622 B CN113963622 B CN 113963622B CN 202111314946 A CN202111314946 A CN 202111314946A CN 113963622 B CN113963622 B CN 113963622B
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- 238000012360 testing method Methods 0.000 claims abstract description 117
- 239000010409 thin film Substances 0.000 claims description 16
- 238000009413 insulation Methods 0.000 claims 1
- 230000009286 beneficial effect Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 23
- 230000002950 deficient Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/13338—Input devices, e.g. touch panels
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136254—Checking; Testing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0412—Digitisers structurally integrated in a display
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Optics & Photonics (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Human Computer Interaction (AREA)
- Liquid Crystal (AREA)
Abstract
The invention discloses a display device, which comprises a display panel, an IC chip and a flexible circuit board; the display panel includes: a display area and a non-display area; the non-display area comprises a binding area, the binding area is provided with a plurality of conductive bonding pads, and the flexible circuit board is electrically connected with the conductive bonding pads; a demultiplexer, a fan-out structure, a wiring area and a test circuit are arranged between the display area and the binding area; the fan-out structure comprises a plurality of fan-out lines, and the plurality of fan-out lines extend along a plurality of different directions; the wiring area comprises a plurality of wirings extending along the column direction, a first end of each wiring is electrically connected with the fan-out wire, and a second end of each wiring is electrically connected with the conductive bonding pad; the output end of the test circuit is electrically connected with the wiring, and the input end of the test circuit is electrically connected with the input end of the test signal; in the direction perpendicular to the display panel, the routing area overlaps with the area where the test circuit is located. The display panel and the display device provided by the embodiment can reduce the area of the non-display area, and are beneficial to realizing narrow frame.
Description
The application relates to a divisional application of application number 201710526337.X, application date 2017, 06 month and 30, and the name of the application, namely a display panel and a display device.
Technical Field
The present invention relates to the field of display technologies, and more particularly, to a display panel and a display device.
Background
Along with development of display technology, the display device is required to be light and thin and have a narrow frame so as to improve use experience of users.
Fig. 1 is a schematic diagram of a display panel provided in the prior art, including a display area 01 and a non-display area 02, wherein a demultiplexer circuit 03, a test circuit 04, a fan-out structure 05, a routing area 06 and a binding area 07 are sequentially disposed in the non-display area 02, and generally, the non-display area where the demultiplexer circuit 03, the test circuit 04, the fan-out structure 05, the routing area 06 and the binding area 07 are located is a lower frame area. The demultiplexer circuit 03 is used for transmitting data signals to data lines in the display panel, the test circuit 04 is used for transmitting test signals to the data lines in the display panel in a test stage so as to detect whether the display panel has poor display, the fan-out structure 05 comprises a plurality of densely arranged fan-out wires, the wire area 06 comprises a plurality of wires, the fan-out wires are electrically connected with the wires in a one-to-one correspondence manner, the binding area 07 is provided with conductive pads, the wires are electrically connected with the corresponding conductive pads, and the conductive pads are used for binding an IC chip or a flexible circuit board (Flexible Printed Circuit, abbreviated as FPC).
As can be seen from fig. 1, in the display panel provided in the prior art, the lower frame area includes more circuit structures, which is not beneficial to realizing the design of the narrow frame.
Disclosure of Invention
In view of this, the present invention provides a display panel and a display device.
The present invention provides a display panel, comprising: a display area and a non-display area; the display area comprises a plurality of data lines which are arranged in parallel and extend along the column direction; the non-display area comprises a binding area, and the binding area is provided with a plurality of conductive bonding pads; a demultiplexer, a fan-out structure, a wiring area and a test circuit are arranged between the display area and the binding area; the output end of the demultiplexer is electrically connected with the plurality of data lines, and the input end of the demultiplexer is electrically connected with the fan-out structure; the fan-out structure comprises a plurality of fan-out lines, and the plurality of fan-out lines extend along a plurality of different directions; the wiring area comprises a plurality of wirings extending along the column direction, a first end of each wiring is electrically connected with the fan-out wire, and a second end of each wiring is electrically connected with the conductive bonding pad; the output end of the test circuit is electrically connected with the wiring, and the input end of the test circuit is electrically connected with the input end of the test signal; in the direction perpendicular to the display panel, the routing area overlaps with the area where the test circuit is located.
In some alternative embodiments, the test circuit includes a plurality of sub-test circuits and a control signal line for controlling on and off of the sub-test circuits; the output end of the sub-test circuit is electrically connected with the wiring, and the input end of the sub-test circuit is electrically connected with the test signal input end.
In some alternative embodiments, a subtest circuit includes a first thin film transistor, a gate of the first thin film transistor is electrically connected to the control signal line, a first pole of the first thin film transistor is electrically connected to the fan-out line, and a second pole of the first thin film transistor is electrically connected to the test signal input.
In some alternative embodiments, the subtest circuit alternates with the first trace.
In some alternative embodiments, two adjacent sub-test circuits are a sub-test circuit group and two adjacent traces are a trace group; the sub-test circuit groups and the wiring groups are alternately arranged.
In some optional embodiments, the touch sensor further comprises a plurality of touch electrodes and a plurality of touch wires, wherein the touch electrodes are electrically connected with the corresponding touch wires; the conductive pads comprise a first conductive pad and a second conductive pad, the second end of the trace is electrically connected with the first conductive pad, and the second conductive pad is electrically connected with the touch trace.
In some alternative embodiments, the second conductive pad is disposed between two adjacent first conductive pads.
In some alternative embodiments, the demultiplexer comprises a plurality of sub-demultiplexers; a sub-demultiplexer includes a sub-input terminal and three sub-output terminals, the sub-output terminals are electrically connected to the data lines, and the sub-input terminals are electrically connected to a fan-out line.
In some alternative embodiments, along the row direction, the width of the side of the fan-out structure adjacent to the demultiplexer is d1, and the width of the side of the fan-out structure adjacent to the routing area is d2, where d1 > d2.
The invention also provides a display device, which comprises the display panel provided by the invention, an IC chip and a flexible circuit board, wherein the flexible circuit board is electrically connected with the conductive bonding pad; the IC chip is arranged on the flexible circuit board and is electrically connected with the flexible circuit board.
Compared with the prior art, the display panel and the display device provided by the invention have the following beneficial effects:
In the display panel and the display device provided by the invention, the wiring area is overlapped with the area where the test circuit is located in the direction vertical to the display panel, compared with the prior art, the area where the test circuit is located is adjusted, and the area where the test circuit is located is overlapped with the wiring area, so that the area of a non-display area can be reduced, and the narrow frames of the display panel and the display device are realized.
Other features of the present invention and its advantages will become apparent from the following detailed description of exemplary embodiments of the invention, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
FIG. 1 is a schematic diagram of a display panel according to the prior art;
FIG. 2 is a schematic diagram of a display panel according to an embodiment of the present invention;
FIG. 2a is an enlarged partial schematic view of area A of FIG. 2;
FIG. 3 is another enlarged partial schematic view of area A of FIG. 2;
FIG. 3a is a schematic diagram of a partial circuit structure of the display panel according to the embodiment of FIG. 3;
FIG. 3b is a schematic circuit diagram of a subtest circuit in the display panel according to the embodiment of FIG. 3;
FIG. 4 is a schematic diagram of another partial circuit structure in the display panel provided in the embodiment of FIG. 3;
FIG. 5 is a schematic diagram of a partial circuit structure of the display panel according to the embodiment of FIG. 3;
FIG. 6 is a schematic diagram of another display panel according to an embodiment of the present invention;
FIG. 6a is an enlarged partial schematic view of area B of FIG. 6;
FIG. 7 is a further enlarged partial schematic view of area A of FIG. 2;
fig. 8 is a schematic diagram of a display device according to an embodiment of the invention
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless it is specifically stated otherwise.
The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of exemplary embodiments may have different values.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.
Referring to fig. 2 and fig. 2a in combination, fig. 2 is a schematic diagram of a display panel according to an embodiment of the invention, and fig. 2a is a partially enlarged schematic diagram of a region a in fig. 2. The display panel provided in fig. 2 includes a display region 10 and a non-display region 20; the display area 10 includes a plurality of data lines 11 arranged in parallel and extending in a column direction; the non-display region 20 includes a bonding region 70, the bonding region 70 being provided with a plurality of conductive pads 71; a demultiplexer 30, a fan-out structure 40, a wiring area 50 and a test circuit 60 are arranged between the display area 10 and the binding area 70; wherein the output 31 of the demultiplexer 30 is electrically connected to the plurality of data lines 11, and the input 32 of the demultiplexer is electrically connected to the fan-out structure 40; the fan-out structure 40 includes a plurality of fan-out lines 41, the plurality of fan-out lines 41 extending in a plurality of different directions; the trace area 50 includes a plurality of traces 51 extending along the column direction, a first end of the trace 51 being electrically connected to the fan-out line 41, and a second end of the trace being electrically connected to the conductive pad 71; the output end of the test circuit 60 is electrically connected with the wiring 51, and the input end of the test circuit 60 is electrically connected with the test signal input end 63; in a direction perpendicular to the display panel, the trace area 50 overlaps with an area where the test circuit 60 is located.
In the display panel provided in fig. 2, the display area 10 is used for displaying image information, and may include a plurality of pixels, for example, the non-display area 20 does not have a display function, and the non-display area 20 may be provided with a wiring or a circuit structure. The display area 10 includes a plurality of data lines 11 arranged in parallel and extending in a column direction, the data lines 11 are used for transmitting electric signals, and the plurality of data lines 11 are arranged in parallel, and it should be noted that the data lines 11 generally extend in the column direction, but in a local area, a slight bend is adapted according to the shape of the pixels, and the slight bend does not affect the extending direction of the data lines 11 generally extending in the column direction. In order to transmit the electrical signals of the display panel to the terminal device where the display panel is located for analysis and calculation, a binding area 70 is provided for binding electronic components for analyzing and calculating the electrical signals in the display panel or for transmitting the electrical signals in the display panel. Specifically, a plurality of conductive pads 71 are disposed in the bonding area 70, and the conductive pads 71 are used for electrically connecting with an electronic component, wherein the electronic component may be an IC chip or a flexible circuit board (Flexible Printed Circuit, abbreviated as FPC). A demultiplexer 30 is disposed between the display area 10 and the binding area 70, an output end 31 of the demultiplexer 30 is electrically connected with the plurality of data lines 11, an input end 32 is electrically connected with the fan-out structure 40, and the data signal is transmitted to the demultiplexer 30 through the fan-out structure and is transmitted to the plurality of data lines 11 after being processed by the demultiplexer 30. A fan-out structure 40 and a routing area 50 are further arranged between the display area 10 and the binding area 70, the fan-out structure 40 comprises a plurality of fan-out wires 41 extending along a plurality of different directions, the routing area 50 comprises a plurality of routing wires 51 extending along a column direction, generally, one side of the fan-out structure close to the display area is wider, one side close to the binding area is narrower, the fan-out structure is similar to the fan-shaped structure in shape, the fan-out wires 41 in the fan-out structure 40 are arranged densely, the routing wires 51 in the routing area 50 are arranged relatively sparsely, blank positions are arranged between the routing wires 51, and the fan-out wires 41 are electrically connected with the corresponding routing wires 51; the traces 51 extend along the column direction to the bonding regions 70 and are then electrically connected to the corresponding conductive pads 71, thereby transmitting electrical signals in the display panel to the IC chip or the flexible circuit board. The display area 10 and the binding area 70 are further provided with a test circuit 60, an output end of the test circuit 60 is electrically connected with the wiring 51, an input end of the test circuit 60 is electrically connected with a test signal input end 63, the test signal input end 63 is used for inputting test signals to the test circuit 60, specifically, after the display panel is manufactured, the display panel is required to be tested to detect defective products, the test signals are input through the test signal input end 63, the test signals are transmitted to a fan-out line 41 electrically connected with the test circuit 60, the fan-out line 41 transmits the test signals to the display panel, and the defective products are detected by observing a display picture of the display panel after the display panel receives the test signals. In the direction perpendicular to the display panel, the trace area 50 overlaps with the area where the test circuit 60 is located, specifically, the schematic diagram of the display panel provided in fig. 2 is a schematic diagram obtained by observing in the direction perpendicular to the display panel; because of the relatively sparse arrangement of the traces 51 in the trace region 50, the test circuit 60 may be disposed in a void in the trace region 50 such that the trace region 50 overlaps the area where the test circuit 60 is located. The area where the trace area 50 overlaps the test circuit 60 may be four cases: in the first case, the trace area 50 is partially overlapped with the area where the test circuit 60 is located; in the second case, the trace area 50 completely covers the area where the test circuit 60 is located; in the third case, the area where the test circuit 60 is located completely covers the trace area 50; in the fourth case, the shape and the area of the area where the trace area 50 and the test circuit 60 are located are the same, and the trace area 50 and the test circuit 60 are completely overlapped. In the display panel provided in the embodiment of fig. 2, only the first case is taken as an example, where the trace area 50 and the area where the test circuit 60 is located are partially overlapped.
In the display panel provided by the embodiment, in the direction perpendicular to the display panel, the area where the routing area and the test circuit are located is overlapped, compared with the prior art, the area where the test circuit is located is adjusted, and the area where the test circuit is located and the routing area are overlapped, so that the area of a non-display area can be reduced, and the display panel and the display device are narrowed.
In some alternative implementations, please refer to fig. 3 and fig. 3a, fig. 3 is another enlarged partial schematic view of the area a in fig. 2, and fig. 3a is a schematic view of a partial circuit structure in the display panel provided by the embodiment of fig. 3. Specifically, fig. 3a provides a schematic circuit diagram of the test circuit 60 and the trace area 50. In the display panel provided in the embodiment of fig. 3, the test circuit 60 includes a plurality of sub-test circuits 61 and a control signal line 62, and the control signal line 62 is used for controlling the sub-test circuits 61 to be turned on and off; an output of the subtest circuit 61 is electrically connected to the trace 51 and an input of the subtest circuit is electrically connected to the test signal input 63. Specifically, the test circuit 60 includes a plurality of sub-test circuits 61 and a control signal line 62, each sub-test circuit 61 is electrically connected to a corresponding test signal input terminal 63, and the control signal line 62 is used for controlling on and off of the sub-test circuit 61, so as to control whether a test signal of the test signal input terminal 63 is input into the display panel. Optionally, in the display panel provided by the embodiment of the invention, two test signal input ends 63 are included, one test signal input end 63 is used for being electrically connected with the odd-numbered sub-test circuit 61, and the other test signal input end 63 is used for being electrically connected with the even-numbered sub-test circuit 61. In the display panel provided in this embodiment, the area where the testing circuit 60 is located is completely covered by the routing area 50, and compared with the prior art, the area where the testing circuit 60 is located is completely integrated in the routing area 50, so that the area of the non-display area can be further reduced, and the narrow frame of the display panel and the display device can be realized. .
In the following, the present invention provides a specific circuit structure of the subtest circuit 61, and it is understood that in other alternative implementations, the specific circuit structure of the subtest circuit 61 may be varied, and the present invention is not limited to the specific circuit structure of the subtest circuit 61.
Referring to fig. 3b, fig. 3b is a schematic circuit diagram of a subtest circuit in the display panel according to the embodiment of fig. 3. In the embodiment provided in fig. 3b, a sub-test circuit 61 includes a first thin film transistor T1, wherein a gate of the first thin film transistor T1 is electrically connected to the control signal line 62, a first pole of the first thin film transistor T1 is electrically connected to the trace 51, and a second pole of the first thin film transistor T1 is electrically connected to the test signal input terminal 63. The sub-test circuit 61 provided in this embodiment has a simple circuit structure, and only includes a first thin film transistor T1, the gate of the first thin film transistor T1 is electrically connected to the control signal line 62, the control signal line 62 can control the on or off of the first thin film transistor T1, and the test signals can be respectively input into the sub-test circuit 61 from the test signal input terminal 63.
In the following, the present invention provides two embodiments of a specific arrangement of a subtest circuit in a routing area, and it is to be understood that, in other alternative implementations, the specific arrangement of the subtest circuit may be multiple, and the present invention is not limited to the specific embodiment of the present invention.
Referring to fig. 4, fig. 4 is a schematic diagram of another partial circuit structure in the display panel provided in the embodiment of fig. 3, and fig. 4 is a schematic diagram of a circuit structure of the wiring area and the test circuit in the display panel provided in the embodiment of fig. 3. Fig. 4 is only described on the basis of the embodiment provided in fig. 3b, and the same parts are not repeated. In the embodiment provided in fig. 4, the subtest circuit 61 is alternately arranged with the first traces 51. Specifically, a subtest circuit 61 is disposed between two adjacent first wires 51.
Referring to fig. 5, fig. 5 is a schematic diagram of a partial circuit structure in the display panel provided in the embodiment of fig. 3, and fig. 5 is a schematic diagram of a circuit structure of the wiring area and the test circuit in the display panel provided in the embodiment of fig. 3. Fig. 5 is only described on the basis of the embodiment provided in fig. 3b, and the same parts are not repeated. In the embodiment provided in fig. 5, two adjacent sub-test circuits 61 are a sub-test circuit group 611 and two adjacent wires 51 are a wire group 511; sub-test circuit groups 611 alternate with trace groups 511. It will be appreciated that in the display panel provided in this embodiment, the sub-test circuit groups 611 are alternately arranged with the trace groups 511, but at the edge portion of the display panel, there may be a single one of the traces 51 or a single one of the sub-test circuits 61. Specifically, in the present embodiment, two wires 51 are disposed adjacently, two sub-test circuits 61 are disposed adjacently, and the adjacent two sub-test circuits 61 can share a part of control signal lines, so that the wires and the circuit layout of the display panel can be simplified.
In some optional implementations, the display panel provided in any of the foregoing embodiments of the present invention may further have a touch function, including a plurality of touch electrodes and a plurality of touch traces, where the touch electrodes are electrically connected to the corresponding touch traces; the conductive pads comprise a first conductive pad and a second conductive pad, the second end of the trace is electrically connected with the first conductive pad, and the second conductive pad is electrically connected with the touch trace. Referring to fig. 6 and fig. 6a, fig. 6 is a schematic diagram of another display panel according to an embodiment of the invention, and fig. 6a is a partially enlarged schematic diagram of a region B in fig. 6. Fig. 6 is a schematic diagram of the display panel provided in the embodiment of fig. 2, and the display panel provided in fig. 6 further includes a plurality of touch electrodes 80 and a plurality of touch traces 81, where the touch electrodes 80 are electrically connected to the corresponding touch traces 81; the conductive pads 71 include a first conductive pad 711 and a second conductive pad 712, the second end of the trace 51 is electrically connected to the first conductive pad 711, and the second conductive pad 712 is electrically connected to the touch trace 81. It should be noted that, in the display panel provided in this embodiment, the touch electrode in the mutual capacitance mode is illustrated as an example, where the touch electrode 80 includes a first touch electrode 801 and a second touch electrode 802, the first touch electrode 801 and the second touch electrode 802 are insulated in a crossing manner, and one of the first touch electrode 801 and the second touch electrode 802 is a touch emission electrode, and the other is a touch sensing electrode. The first touch electrode 801 is electrically connected to the first touch trace 811, and the second touch electrode 802 is electrically connected to the second touch trace 812. It can be understood that, in the display panel provided in this embodiment, the operation mode of the touch electrode may also be self-capacitance, and the shape and operation mode of the touch electrode are not particularly limited in the present invention. In the display panel provided in this embodiment, the conductive pad 71 includes a first conductive pad 711 and a second conductive pad 712, the first conductive pad 711 is used for transmitting an electrical signal to the trace 51, and the second conductive pad 712 is used for transmitting an electrical signal to the touch trace 81. In the display panel provided in this embodiment, the conductive pad 712 electrically connected to the touch trace 81 is also disposed in the binding area, and by subsequently binding an IC chip or a flexible circuit board, electrical signals can be transmitted to the trace 51 and the touch trace 81 at the same time, so that the layout of the display panel is simplified.
Optionally, a second conductive pad 712 is disposed between two adjacent first conductive pads 711. Specifically, the second conductive pads 712 may be alternately arranged with the first conductive pads 711, or one second conductive pad 712 may be arranged every two or more first conductive pads 711. The specific arrangement manner of the second conductive pads 712 may be set according to a specific implementation, which is not particularly limited in this embodiment. In the display panel provided in this embodiment, the second conductive pads 712 are disposed between two adjacent first conductive pads 711, and the second conductive pads 712 do not need to be disposed in the same area in a concentrated manner, so that the layout of circuit traces such as traces and touch traces in the display panel can be simplified.
In some alternative implementations, the demultiplexer includes a plurality of sub-demultiplexers in accordance with any one of the embodiments of the present invention; a sub-demultiplexer includes a sub-input terminal and three sub-output terminals, the sub-output terminals are electrically connected to the data lines, and the sub-input terminals are electrically connected to a fan-out line. Specifically, referring to fig. 7, fig. 7 is a schematic enlarged view of a portion a in fig. 2, and in the display panel provided in the embodiment of fig. 7, the demultiplexer 30 includes a plurality of sub-demultiplexers 301; a sub-demultiplexer 301 includes a sub-input 321 and three sub-outputs 311, the sub-outputs 311 being electrically connected to the data lines 11, the sub-inputs 321 being electrically connected to a fan-out line 41. In the display panel provided in this embodiment, the input/output ratio of the demultiplexer 30 is 1:3, and data signals can be provided for three data lines 11 through one sub-input end 321, and by providing a plurality of sub-demultiplexers 301, the circuit routing of the non-display area 20 can be simplified, the number of conductive pads 71 can be reduced, and the narrow frame of the display panel can be realized.
In some alternative implementations, referring to fig. 7, along the row direction, the fan-out structure 40 has a width d1 on a side near the demultiplexer 30, and the fan-out structure 40 has a width d2 on a side near the routing area 50, where d1 > d2. In this embodiment, the fan-out structure has a wider side near the demultiplexer 30 and a narrower side near the routing area 50, so that the routing area 50 is narrower and the area of the non-display area 20 is saved.
The application also provides a display device, which comprises the display panel provided by the application, an IC chip and a flexible circuit board, wherein the flexible circuit board is electrically connected with the conductive bonding pad; the IC chip is arranged on the flexible circuit board and is electrically connected with the flexible circuit board. Specifically, referring to fig. 8, fig. 8 is a schematic diagram of a display device according to an embodiment of the application. Fig. 8 is only described on the basis of the display panel provided in the embodiment of fig. 2, and fig. 8 uses the reference numerals of fig. 2, and the details of the reference numerals are not repeated, and the display device provided in fig. 8 includes the display panel 100 provided in any of the above embodiments of the present application, and further includes an IC chip 300 and a flexible circuit board 200, where the flexible circuit board 200 is electrically connected to the conductive pads 71; the IC chip 300 is disposed on the flexible wiring board 200, and the IC chip 300 is electrically connected with the flexible wiring board 200. In the display device provided in this embodiment, the IC chip 300 is bound to the flexible circuit board 200, the flexible circuit board 200 is bound to the display panel 100, and the electrical signals in the display panel 100 can be transmitted to the IC chip 300 through the flexible circuit board 200, and the IC chip 300 calculates and analyzes the electrical signals in the display panel 100. The display device provided in this embodiment has the excellent effects of the display panel provided in this embodiment, and will not be described herein. The display device provided in this embodiment may be any display device having an input/output interface, such as a mobile phone, a television, a tablet computer, a vehicle-mounted display, an industrial control display, etc., which is not limited in this application, and may be specifically determined according to circumstances.
Compared with the prior art, the display panel and the display device provided by the invention have the following beneficial effects:
In the display panel and the display device provided by the invention, the wiring area is overlapped with the area where the test circuit is located in the direction vertical to the display panel, so that the area of a non-display area can be reduced, and the narrow frames of the display panel and the display device are realized.
While certain specific embodiments of the invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (14)
1. The display device is characterized by comprising a display panel, an IC chip and a flexible circuit board;
the IC chip is arranged on the flexible circuit board, and the IC chip is electrically connected with the flexible circuit board, and the display panel comprises: a display area and a non-display area;
the display area comprises a plurality of data lines which are arranged in parallel and extend along the column direction;
the non-display area comprises a binding area, the binding area is provided with a plurality of conductive bonding pads, and the flexible circuit board is electrically connected with the conductive bonding pads;
a demultiplexer, a fan-out structure, a wiring area and a test circuit are arranged between the display area and the binding area; wherein,
The output end of the demultiplexer is electrically connected with a plurality of data lines, and the input end of the demultiplexer is electrically connected with the fan-out structure;
The fan-out structure comprises a plurality of fan-out lines, wherein the fan-out lines extend along a plurality of different directions;
the width of one side of the fan-out structure close to the demultiplexer is d1, and the width of one side of the fan-out structure close to the routing area is d2, wherein d1 is more than d2;
The wiring area comprises a plurality of wirings extending along the column direction, a first end of each wiring is electrically connected with the fan-out wire, and a second end of each wiring is electrically connected with the conductive bonding pad;
The output end of the test circuit is electrically connected with the wiring, and the input end of the test circuit is electrically connected with the input end of the test signal;
along the row direction, a blank is arranged between the wires, and the test circuit is arranged at the blank in the wire area;
in the direction perpendicular to the display panel, the wiring area overlaps with the area where the test circuit is located;
The test circuit comprises a plurality of sub-test circuits and a control signal line, wherein the control signal line is used for controlling the on and off of the sub-test circuits; the output end of the sub-test circuit is electrically connected with the wiring, and the input end of the sub-test circuit is electrically connected with the test signal input end;
the display device further comprises a plurality of touch electrodes and a plurality of touch wires, and the touch electrodes are electrically connected with the corresponding touch wires;
The conductive pads comprise first conductive pads and second conductive pads, the second ends of the wires are electrically connected with the first conductive pads, and the second conductive pads are electrically connected with the touch wires;
The first conductive pad and the second conductive pad are electrically connected to the same IC chip.
2. The display device according to claim 1, wherein one of the sub-test circuits includes a first thin film transistor, a gate electrode of the first thin film transistor is electrically connected to the control signal line, a first electrode of the first thin film transistor is electrically connected to the fan-out line, and a second electrode of the first thin film transistor is electrically connected to the test signal input terminal.
3. The display device of claim 1, wherein the subtest circuits alternate with the traces.
4. The display device of claim 1, wherein two adjacent ones of the sub-test circuits are a sub-test circuit group and two adjacent ones of the traces are a trace group;
The sub-test circuit groups and the wiring groups are alternately arranged.
5. The display device according to claim 1, wherein the second conductive pad is disposed between two adjacent first conductive pads.
6. The display device of claim 1, wherein the demultiplexer comprises a plurality of sub-demultiplexers;
A sub-demultiplexer includes a sub-input electrically connected to the data line and three sub-outputs electrically connected to one of the fan-out lines.
7. The display device according to claim 2, wherein a size of the wiring is larger than a size of the thin film transistor in a column direction.
8. The display device of claim 2, wherein the trace area completely covers an area where the test circuit is located.
9. The display device according to claim 4, wherein the display panel includes a dicing line, and in an edge region of the display panel in a row direction, the number of the wirings provided between the sub-test circuit group and the dicing line is only one, or the number of the sub-test circuits provided between the wiring group and the dicing line is only one.
10. The display device of claim 4, wherein adjacent two of said sub-test circuits in one of said test circuit sub-groups share a portion of said control signal line.
11. The display device of claim 1, wherein the touch electrode comprises a first touch electrode and a second touch electrode arranged in a cross insulation manner, the first touch electrode is electrically connected with a first touch trace, the second touch electrode is electrically connected with a second touch trace, and the second conductive pad is electrically connected with the first touch trace or the second touch trace.
12. The display device of claim 1, wherein the touch electrode comprises a self-capacitive touch electrode.
13. The display device of claim 5, wherein at least a portion of two adjacent touch traces include N traces, where N is an integer greater than 1.
14. The display device according to claim 5, wherein M sub-test circuits are included between at least two adjacent touch traces, M being an integer greater than 1.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111314946.1A CN113963622B (en) | 2017-06-30 | 2017-06-30 | Display panel and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710526337.XA CN107180594B (en) | 2017-06-30 | 2017-06-30 | Display panel and display device |
| CN202111314946.1A CN113963622B (en) | 2017-06-30 | 2017-06-30 | Display panel and display device |
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| CN201710526337.XA Division CN107180594B (en) | 2017-06-30 | 2017-06-30 | Display panel and display device |
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Also Published As
| Publication number | Publication date |
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| CN113963622A (en) | 2022-01-21 |
| CN107180594A (en) | 2017-09-19 |
| CN107180594B (en) | 2021-11-30 |
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