CN111880344B - Display panel, preparation method thereof and display device - Google Patents
Display panel, preparation method thereof and display device Download PDFInfo
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- CN111880344B CN111880344B CN202010754301.9A CN202010754301A CN111880344B CN 111880344 B CN111880344 B CN 111880344B CN 202010754301 A CN202010754301 A CN 202010754301A CN 111880344 B CN111880344 B CN 111880344B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13458—Terminal pads
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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Abstract
The invention discloses a display panel, a preparation method thereof and a display device. In the display panel, along the extension direction parallel to the boundary of the fan-out area and the display area, the binding area comprises a first area, a second area and a third area which are sequentially arranged, the vertical projection of the planarization layer on the substrate is not overlapped with the vertical projection of the binding pad on the substrate, the thickness of the planarization layer in the area between the binding pad and the fan-out area in the first area and the thickness of the planarization layer in the area between the binding pad and the fan-out area in the third area are smaller than the thickness of the planarization layer in the fan-out area. The technical scheme provided by the embodiment of the invention avoids the damage of the drive chip in the binding process and improves the binding stability of the drive chip.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a display panel, a preparation method of the display panel and a display device.
Background
Chip On Glass (COG) technology has the advantages of simple process, high integration level, difficult deformation of a driver chip and the like, and is one of the current mainstream driver chip binding technologies.
The display panel adopting the COG technology is provided with the input binding pads and the output binding pads, the conventional input binding pads and the conventional output binding pads are arranged in a linear mode, and the fan-out area is not overlapped with the binding area, so that the width of a frame where the fan-out area and the binding area are located in the display panel is large. In order to solve the above problems, in the prior art, the output bonding pads are arranged in a manner that two ends of the output bonding pads are sunk, but in this manner, the vacated region of the sunk output bonding pads has a height difference with other regions in the bonding region, so that the bonding surface of the driving chip is uneven, the phenomenon of breaking of the driving chip is easy to occur, and the bonding stability of the driving chip is poor.
Disclosure of Invention
The invention provides a display panel, a manufacturing method thereof and a display device, which are used for avoiding damage of a driving chip in a binding process and improving the binding stability of the driving chip.
In a first aspect, an embodiment of the present invention provides a display panel, including:
a display area and a non-display area surrounding the display area; the non-display area comprises a binding area and a fan-out area; the fan-out area is positioned between the display area and the binding area; the binding region comprises a first region, a second region and a third region which are sequentially arranged along a boundary extension direction parallel to the fan-out region and the display region;
the binding region is provided with a binding pad group; the bonding pad group comprises a plurality of bonding pads; along the direction that the first area points to the second area, the distance between each binding pad positioned in the first area and the display area is gradually reduced, and the distance between each binding pad positioned in the third area and the display area is gradually increased; the distances between each binding pad of the second area and the display area are equal;
the fan-out area is provided with a plurality of fan-out lines; one end of the fanout line is electrically connected with the signal line of the display area; the other end of the fanout wire is electrically connected with the binding pads in a one-to-one correspondence manner; the fan-out line electrically connected with the bonding pad of the first region extends to the first region; the fan-out line electrically connected with the bonding pad of the third region extends to the third region;
the display panel further comprises a substrate, and a pixel circuit layer and a planarization layer which are sequentially arranged on the substrate;
the vertical projection of the planarization layer on the substrate and the vertical projection of the bonding pad on the substrate do not overlap, and the thickness of the planarization layer in the area between the bonding pad and the fan-out area in the first region and the area between the bonding pad and the fan-out area in the third region is smaller than the thickness of the planarization layer of the fan-out area.
In a second aspect, an embodiment of the present invention further provides a method for manufacturing a display panel, including:
sequentially forming a pixel circuit layer and a planarization layer on a substrate;
processing the planarization layer to remove the planarization layer at a bond pad, and a thickness of the planarization layer in a region between the bond pad and a fan-out region in a first region and a region between the bond pad and the fan-out region in a third region is less than a thickness of the planarization layer of the fan-out region;
wherein the display panel includes a display area and a non-display area surrounding the display area; the non-display area comprises a binding area and a fan-out area which are arranged in sequence and deviate from the display area; the binding region comprises a first region, a second region and a third region which are sequentially arranged along a boundary extension direction parallel to the fan-out region and the display region; the binding region is provided with a binding pad group; the bonding pad group comprises a plurality of bonding pads; along the direction that the first area points to the second area, the distance between each binding pad positioned in the first area and the display area is gradually reduced, and the distance between each binding pad positioned in the third area and the display area is gradually increased; the distances between each binding pad of the second area and the display area are equal; the fan-out area is provided with a plurality of fan-out lines; one end of the fanout line is electrically connected with the signal line of the display area; the other end of the fanout line is electrically connected with the binding pads in a one-to-one correspondence manner; the fan-out line electrically connected with the bonding pad of the first region extends to the first region; the fan-out line electrically connected with the bonding pad of the third region extends to the third region.
In a third aspect, an embodiment of the present invention further provides a display device, including:
the display panel according to the first aspect, and a driving chip;
and each output terminal of the driving chip is electrically connected with each binding pad in a one-to-one correspondence manner.
In the display panel provided by the embodiment of the invention, along the extension direction parallel to the boundary of the fan-out area and the display area, the binding area comprises a first area, a second area and a third area which are sequentially arranged, the vertical projection of the planarization layer on the substrate is not overlapped with the vertical projection of the binding pad on the substrate, the thickness of the planarization layer in the area between the binding pad and the fan-out area in the first area and the thickness of the planarization layer in the area between the binding pad and the fan-out area in the third area are smaller than that of the planarization layer of the fan-out area, the area between the binding pad and the fan-out area in the first area and the thickness difference between the area between the binding pad and the fan-out area in the third area and other areas in the binding area are reduced, the flatness of the binding surface of the driving chip is improved, the driving chip is prevented from being damaged in the binding process, and the stability of the driving chip is improved.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments made with reference to the following drawings:
FIG. 1 is a schematic partial cross-sectional view of a display panel of the prior art;
fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a partial structure of the display panel shown in FIG. 2;
FIG. 4 is a schematic cross-sectional view taken along the dashed line AB in FIG. 3;
fig. 5 is a schematic partial structure diagram of a display panel according to an embodiment of the present invention;
FIG. 6 is a schematic view of a further cross-sectional configuration taken along the dashed line AB of FIG. 3;
FIG. 7 is a schematic view of a further cross-sectional configuration taken along the dashed line AB of FIG. 3;
FIG. 8 is a schematic diagram of a partial structure of another display panel according to an embodiment of the present invention;
FIG. 9 is a schematic cross-sectional view taken along the dashed line CD in FIG. 8;
FIG. 10 is a schematic view of a further cross-sectional configuration along the dashed line CD in FIG. 8;
FIG. 11 is a schematic view of a further cross-sectional configuration along the dashed line CD in FIG. 8;
FIG. 12 is a schematic view of a further cross-sectional configuration taken along the dashed line AB of FIG. 3;
FIG. 13 is a schematic view of a further cross-sectional configuration taken along the dashed line AB of FIG. 3;
fig. 14 is a schematic flow chart of a method for manufacturing a display panel according to an embodiment of the present invention;
fig. 15 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description will be made on a display panel and a manufacturing method thereof, and a specific implementation manner, a structure, features and effects of a display device according to the present invention, with reference to the accompanying drawings and preferred embodiments.
An embodiment of the present invention provides a display panel, including:
a display area and a non-display area surrounding the display area; the non-display area comprises a binding area and a fan-out area; the fan-out area is positioned between the display area and the binding area; the binding region comprises a first region, a second region and a third region which are sequentially arranged along a boundary extension direction parallel to the fan-out region and the display region;
the binding region is provided with a binding pad group; the binding pad group comprises a plurality of binding pads; along the direction that the first area points to the second area, the distance between each binding pad positioned in the first area and the display area is gradually reduced, and the distance between each binding pad positioned in the third area and the display area is gradually increased; the distances between each binding pad of the second area and the display area are equal;
the fan-out area is provided with a plurality of fan-out lines; one end of the fanout line is electrically connected with the signal line of the display area; the other end of the fanout wire is electrically connected with the binding pads in a one-to-one correspondence manner; the fan-out line electrically connected with the bonding pad of the first region extends to the first region; the fan-out line electrically connected with the bonding pad of the third region extends to the third region;
the display panel further comprises a substrate, and a pixel circuit layer and a planarization layer which are sequentially arranged on the substrate;
the vertical projection of the planarization layer on the substrate and the vertical projection of the bonding pad on the substrate do not overlap, and the thickness of the planarization layer in the area between the bonding pad and the fan-out area in the first region and the area between the bonding pad and the fan-out area in the third region is smaller than the thickness of the planarization layer of the fan-out area.
In the display panel provided by the embodiment of the invention, along the extension direction parallel to the boundary of the fan-out area and the display area, the binding area comprises a first area, a second area and a third area which are sequentially arranged, the vertical projection of the planarization layer on the substrate is not overlapped with the vertical projection of the binding pad on the substrate, the thickness of the planarization layer in the area between the binding pad and the fan-out area in the first area and the thickness of the planarization layer in the area between the binding pad and the fan-out area in the third area are smaller than that of the planarization layer of the fan-out area, the area between the binding pad and the fan-out area in the first area and the thickness difference between the area between the binding pad and the fan-out area in the third area and other areas in the binding area are reduced, the flatness of the binding surface of the driving chip is improved, the driving chip is prevented from being damaged in the binding process, and the stability of the driving chip is improved.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art based on the embodiments of the present invention without any creative work, belong to the protection scope of the present invention.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other embodiments that depart from the specific details disclosed herein, and it will be recognized by those skilled in the art that the present invention may be practiced without these specific details.
Next, the present invention is described in detail with reference to the schematic drawings, and in the detailed description of the embodiments of the present invention, the schematic drawings showing the structure of the device are not partially enlarged in general scale for convenience of description, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and height should be included in the actual fabrication.
Fig. 1 is a partial cross-sectional view of a display panel in the prior art. As shown in fig. 1, the display panel includes a display area 10, a fan-out area 21, and a bonding area 22, where the bonding area 22 is provided with a plurality of bonding pads 201, and the bonding pads 201 are used to implement COG mounting of a driver chip on the display panel. The bonding region 22 comprises a first region 212 where signal lines exist and a second region 222 where the bonding pad 201 is arranged, so that the preparation of the bonding pad 201 is facilitated, the electrical performance of the bonding pad 201 is improved, the planarization layer 120 in the second region 222 is removed, and meanwhile, the planarization layer 120 in the first region 212 is reserved, and the phenomenon that electrical signals are disordered in the first region 212 is avoided. Due to the large thickness of the planarization layer 120, the second region 222 and the first region 212 form a significant height difference, which results in an uneven bonding surface during the bonding process of the driver chip, and is prone to breaking and poor bonding stability.
In order to solve the above problem, an embodiment of the present invention provides a display panel, where a thickness of a planarization layer in a region where a signal line exists in a bonding region is smaller than a thickness of a planarization layer in a fan-out region, so that flatness of a bonding surface of a driver chip is improved, the driver chip is prevented from being broken, and bonding stability of the driver chip is improved.
Specifically, fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the present invention. As shown in fig. 2, the display panel includes a display area 10 and a non-display area 20 surrounding the display area 10, the non-display area 20 including a bonding area 22 and a fan-out area 21, the fan-out area 21 being located between the display area 10 and the bonding area 22.
Fig. 3 is a schematic partial structure diagram of the display panel in fig. 2. As shown in fig. 3, the bonding region 22 includes a first region 210, a second region 220, and a third region 230 sequentially arranged along a direction X parallel to the boundary extension direction of the fan-out region 21 and the display region 10.
The bind region 22 is provided with a bind pad group 200, and the bind pad group 200 includes a plurality of bind pads 201. Along the direction X in which the first region 210 points to the second region 220, the distance k between each bonding pad 201 located in the first region 210 and the display region 10 gradually decreases, the distance k between each bonding pad 201 located in the third region 230 and the display region 10 gradually increases, and the distances k between each bonding pad 201 located in the second region 220 and the display region 10 are equal.
The fan-out area 21 is provided with a plurality of fan-out lines 401, one end of each fan-out line 401 is electrically connected with the signal line 402 of the display area 10, the other end of each fan-out line 401 is electrically connected with the corresponding binding pad 201, the fan-out lines 401 electrically connected with the binding pads 201 of the first area 210 extend to the first area 210, and the fan-out lines 401 electrically connected with the binding pads 201 of the third area 230 extend to the third area 230.
Fig. 4 is a schematic sectional view along the broken line AB in fig. 3. As shown in fig. 3 and 4, the display panel further includes a substrate 100, and a pixel circuit layer 110 and a planarization layer 120 sequentially disposed on the substrate 100. A vertical projection of the planarization layer 120 on the substrate 100 does not overlap a vertical projection of the bonding pad 201 on the substrate 100, and a thickness a of the planarization layer 120 in a region 211 between the bonding pad 201 and the fan-out region 21 in the first region 210 is less than a thickness b of the planarization layer 120 of the fan-out region 21. The third region 230 has a structure similar to the first region 210, and a thickness of the planarization layer 120 in a region 231 between the bonding pad 201 and the fan-out region 21 in the third region 230 is smaller than a thickness of the planarization layer 120 of the fan-out region 21.
It is understood that the planarization layer 120 in the region 212 within the bonding region 22 except for the region 211 between the bonding pad 201 and the fan-out region 21 in the first region 210 and the region 231 between the bonding pad 201 and the fan-out region 21 in the third region 230 is removed to facilitate the formation of the bonding pad 201.
It should be noted that, fig. 2 and fig. 3 only illustrate the plurality of bonding pads 201 arranged in a row without limitation, in other embodiments of this embodiment, the plurality of bonding pads 201 may be arranged in a plurality of rows, and all the bonding pad 201 arrangement modes that satisfy "the distance k between each bonding pad 201 located in the first region 210 and the display region 10 gradually decreases, the distance k between each bonding pad 201 located in the third region 230 and the display region 10 gradually increases, and the distance k between each bonding pad 201 located in the second region 220 and the display region 10 is equal" are within the protection range of this embodiment.
Exemplarily, fig. 5 is a schematic view of a partial structure of a display panel according to an embodiment of the present invention. As shown in fig. 5, the bonding pad 201 in this embodiment may be an output bonding pad 202, and on this basis, the bonding region 22 may further include a plurality of input bonding pads 203, the plurality of input bonding pads 203 are located on a side of the plurality of output bonding pads 202 away from the fan-out region 21, and the plurality of output bonding pads 202 are linearly arranged along the direction X.
In the present embodiment, the thickness of the planarization layer 120 in the region 211 between the bonding pad 201 and the fan-out region 21 in the first region 210, and the region 231 between the bonding pad 201 and the fan-out region 21 in the third region 230 may be a constant greater than or equal to 0, as shown in fig. 4; alternatively, the thickness of the planarization layer 120 in the region 211 between the bonding pad 201 and the fan-out region 21 in the first region 210 and the region 231 between the bonding pad 201 and the fan-out region 21 in the third region 230 is non-constant, for example, varies regularly.
With continued reference to fig. 4, the display panel may be a liquid crystal display panel, and in addition to the substrate 100, the driving circuit layer 110 and the planarization layer 120, the display panel further includes a common electrode 130, a pixel electrode 140 and a liquid crystal layer (not shown in fig. 4), wherein the driving circuit layer 110 includes a thin film transistor 111 and a light shielding layer 150 located on one side of the thin film transistor 111 close to the substrate 100, and a drain of the thin film transistor 111 is electrically connected to the pixel electrode 140. During normal operation of the display panel, an electric field is formed between the pixel electrode 140 and the common electrode 120, and the liquid crystal molecules are deflected by a certain angle under the action of the electric field, so as to adjust the light flux passing through the liquid crystal layer (not shown in fig. 4).
In other embodiments of this embodiment, the display panel may be an organic light emitting display panel, as shown in fig. 6, in addition to the substrate 100, the driving circuit layer 110 and the planarization layer 120, the display panel further includes a plurality of organic light emitting elements (not shown in fig. 6), each of the organic light emitting elements includes an anode 170, the anodes 170 are electrically connected to the driving circuits in the driving circuit layer 110 in a one-to-one correspondence manner, for example, the driving circuits may have a 7T1C structure, and fig. 6 only illustrates the thin film transistors 111 in the driving circuits, which are directly connected to the anodes 170, and the light shielding layer 150 located on the side of the thin film transistors 111 close to the substrate 100. The organic light emitting element further includes an organic light emitting functional layer (not shown in fig. 6) and a cathode (not shown in fig. 6) sequentially stacked on the anode 170, and in a normal operation of the display panel, electrons and holes are injected from the cathode and the anode 170 to the organic light emitting functional layer, respectively, and meet in the organic light emitting functional layer to form excitons and excite light emitting molecules, which emit visible light through radiation relaxation.
In the display panel provided by this embodiment, along the extending direction X parallel to the boundary between the fan-out region 21 and the display region 10, the bonding region 22 includes the first region 210, the second region 220, and the third region 230, which are sequentially arranged, the vertical projection of the planarization layer 120 on the substrate 100 and the vertical projection of the bonding pad 201 on the substrate 100 do not overlap, and the thickness of the region 211 between the bonding pad 201 and the fan-out region 21 in the first region 210, and the thickness of the planarization layer 120 in the region 231 between the bonding pad 201 and the fan-out region 21 in the third region 230 are smaller than the thickness of the planarization layer 120 of the fan-out region 21, so that the thickness difference between the region 211 between the bonding pad 201 and the fan-out region 21 in the first region 210, and the thickness difference between the region 231 between the bonding pad 201 and the fan-out region 21 in the third region 230 and other regions in the bonding region 22 is reduced, the flatness of the bonding surface of the driving chip is improved, and the driving chip is prevented from being damaged in the bonding process, the binding stability of the drive chip is improved.
Fig. 7 is a schematic view of another cross-sectional structure taken along the dashed line AB in fig. 3. As shown in fig. 7, the planarization layer 120 does not overlap the bonding region 22.
At this time, the thickness of the planarization layer 120 in the bonding region 22 is 0, the flatness of the bonding region 22 is not affected by the planarization layer 120, the flatness of the bonding surface of the driver chip is good, and the improvement of the bonding stability of the driver chip is facilitated.
Fig. 8 is a schematic partial structure diagram of another display panel according to an embodiment of the present invention. Fig. 9 is a schematic cross-sectional view along the dashed line CD in fig. 8. As shown in fig. 8 and 9, the bonding pad 201 includes a first conductive structure 301, a second conductive structure 302, and a third conductive structure 303 stacked, the pixel circuit layer 110 includes a first conductive layer 112 and a second conductive layer 113 stacked and insulated, the first conductive layer 112 forms the first conductive structure 301 of the bonding pad 201 at the bonding region 22, and the second conductive layer 113 forms the second conductive structure 302 of the bonding pad 201 at the bonding region 22.
The display panel further includes an electrode layer 310 located on a side of the pixel circuit layer 110 away from the substrate 100, the electrode layer 310 forms a third conductive structure 303 of the bonding pad 201 in the bonding region 22, and the first conductive structure 301, the second conductive structure 302, and the third conductive structure 303 are sequentially stacked and electrically connected. A region 211 between the bonding pad 201 and the fan-out region 21 in the first region 210, and a region 231 between the bonding pad 201 and the fan-out region 21 in the third region 230 are also provided with a dummy support pad 202, and a vertical projection of the dummy support pad 202 on the substrate 100 overlaps with a vertical projection of the fan-out line 401 on the substrate 100.
It should be noted that the first conductive structure 301, the second conductive structure 302, and the third conductive structure 303 of the bonding pad 201 are formed by using the inherent film layer of the display panel, on one hand, no dedicated film layer or dedicated process step is required to be provided for the bonding pad 201, which is beneficial to thinning the display panel and simplifying the manufacturing process of the display panel. On the other hand, the fanout line 401 is usually located on the first conductive layer 112 and the second conductive layer 113, and the bonding pad 201 can be electrically connected to the fanout line 401 simply through a conductive structure disposed on the same layer, without adopting a cross-wire or other methods, and has a simple process and good electrical connection stability.
For a liquid crystal display panel, the electrode layer 310 may include at least one of the pixel electrode 140 and the common electrode 130, and exemplarily, as shown in fig. 9, the electrode layer 310 includes the pixel electrode 140 and the common electrode 130, and the pixel electrode 140 and the common electrode 130 together form the third conductive structure 303 of the bonding pad 201 in the bonding region 22. For an organic light emitting display panel, the electrode layer 310 may be, for example, an anode, which forms the third conductive structure 303 of the bonding pad 201 at the bonding region 22.
It should be further noted that a position of the fan-out line 401 in the fan-out region 21 is raised, a groove is formed between adjacent fan-out lines 401, and in order to ensure a supporting function of the virtual support pad 202, the virtual support pad 202 is arranged to overlap the fan-out lines 401.
Alternatively, referring to fig. 8 and 9, the electrode layer 310 forms the dummy support pad 202 in a region 211 between the bonding pad 201 and the fan-out region 21 in the first region 210, and a region 231 between the bonding pad 201 and the fan-out region 21 in the third region 230.
It should be noted that the electrode layer 310 is an intrinsic film layer of the display panel, and the virtual support pad 202 is formed by using the intrinsic film layer of the display panel, so that an exclusive film layer and an exclusive process step are not required to be provided for the virtual support pad 202, which is beneficial to simplifying the preparation process of the display panel and thinning the display panel.
Illustratively, with continued reference to fig. 8 and 9, the electrode layer 310 includes a first electrode layer 311 and a second electrode layer 312 stacked and insulated from the first electrode layer 311, the first electrode layer 311 and the second electrode layer 312 form a dummy support pad 202 in a region 211 between the bonding pad 201 and the fan-out region 21 in the first region 210, and a region 231 between the bonding pad 201 and the fan-out region 21 in the third region 230.
In other embodiments of the present embodiment, the first electrode layer 311 in the electrode layer 310 forms the dummy support pad 202 in the region 211 between the bonding pad 201 and the fan-out region 21 in the first region 210, and the region 231 between the bonding pad 201 and the fan-out region 21 in the third region 230, as shown in fig. 8 and 10. Alternatively, the second electrode layer 312 in the electrode layer 310 forms the dummy support pad 202 in the region 211 between the bonding pad 201 and the fan-out region 21 in the first region 210, and the region 231 between the bonding pad 201 and the fan-out region 21 in the third region 230, as shown in fig. 8 and 11.
The first electrode layer 311 and the second electrode layer 312 may be, for example, the pixel electrode 140 and the common electrode 130, respectively.
It should be noted that, fig. 9, fig. 10, and fig. 11 are only used for illustrating, but not limited to, the pixel electrode 140 being located on the side of the common electrode 130 away from the substrate 100, and in other embodiments of the present embodiment, the pixel electrode 140 may be located on the side of the common electrode 130 close to the substrate 100.
Fig. 12 is a schematic view of another cross-sectional structure taken along the dashed line AB in fig. 3. As shown in fig. 12, the display panel further includes a touch routing layer 160, the touch routing layer 160 is located between the planarization layer 120 and the electrode layer 130, and an insulating layer 180 is disposed between the touch routing layer 160 and the electrode layer 130.
It should be noted that the touch routing layer 160 includes a plurality of touch signal lines, and the touch signal lines are used for transmitting touch signals so as to implement a touch function through touch electrodes electrically connected to the touch signal lines.
It should be noted that, the touch routing layer 160 and the electrode layer 130 are both conductors, and in order to avoid the interference of electrical signals between the two, an insulating layer 180 is disposed between the touch routing layer 160 and the electrode layer 130.
It can be understood that the first conductive layer 112 and the second conductive layer 113 in the driving circuit layer 110, and the touch routing layer 160 can be used as routing film layers of signal lines such as data lines, the signal lines in the fan-out area 21 and the binding area 22 are densely arranged, the distance between adjacent signal lines is small, in order to avoid mutual interference between the signal lines, the arrangement direction of the signal lines can be set, each signal line is sequentially and circularly arranged on the first conductive layer 112, the second conductive layer 113, and the touch routing layer 160, for the same signal line, the film layer where the display area 10 is located can be different from the film layer where the fan-out area 21 is located, and a jumper wire can be realized through a through hole penetrating through the insulating layer. In other embodiments of this embodiment, the arrangement manner of the film layer where the signal line is located may also be other cases, and this embodiment is not limited in particular.
Fig. 13 is a schematic view of another cross-sectional structure taken along the dashed line AB in fig. 3. As shown in fig. 13, the thickness of the planarization layer 120 in the region 211 between the binding pad 201 and the fan-out region 21 in the first region gradually increases along the direction Y in which the binding region 22 points toward the fan-out region 21. Similarly, the thickness of the planarization layer in the region between the bonding pad and the fan-out region in the third region gradually increases.
It should be noted that, in such an arrangement manner, the thickness of the planarization layer 120 gradually transits from the fan-out region 21 to the bonding pad 201, a step with a large height difference does not occur, the probability that the driver chip is broken due to the influence of the step is small, and the bonding stability of the driver chip is good.
Fig. 14 is a schematic flow chart of a method for manufacturing a display panel according to an embodiment of the present invention. The preparation method of the display panel is used for preparing the display panel provided by any embodiment of the invention. As shown in fig. 14, the preparation method of the display panel may specifically include the following steps:
and 11, forming a pixel circuit layer and a planarization layer on the substrate in sequence.
And step 12, processing the planarization layer to remove the planarization layer at the bonding pad, wherein the thickness of the planarization layer in the area between the bonding pad and the fan-out area in the first area and the thickness of the planarization layer in the area between the bonding pad and the fan-out area in the third area are smaller than that of the planarization layer of the fan-out area. Wherein, the display panel comprises a display area and a non-display area surrounding the display area, the non-display area comprises a binding area and a fan-out area which are arranged in turn and depart from the display area, the binding area comprises a first area, a second area and a third area which are arranged in turn along the extension direction parallel to the boundary of the fan-out area and the display area, the binding area is provided with a binding pad group, the binding pad group comprises a plurality of binding pads, the distance between each binding pad positioned in the first area and the display area is gradually reduced along the direction of the first area pointing to the second area, the distance between each binding pad positioned in the third area and the display area is gradually increased, the distance between each binding pad positioned in the second area and the display area is equal, the fan-out line is provided with a plurality of fan-out lines, one end of each fan-out line is electrically connected with a signal line of the display area, the other end of each fan-out line is electrically connected with the binding pad in one-to-one correspondence, and the fan-out line electrically connected with the binding pad of the first area extends to the first area, and the fanout line electrically connected with the bonding pad of the third region extends to the third region.
According to the technical scheme provided by the embodiment of the invention, the pixel circuit layer and the planarization layer are sequentially formed on the substrate, the planarization layer is processed to remove the planarization layer at the binding pad, the thickness of the planarization layer in the area between the binding pad and the fan-out area in the first area and the thickness of the planarization layer in the area between the binding pad and the fan-out area in the third area are smaller than that of the planarization layer of the fan-out area, the area between the binding pad and the fan-out area in the first area and the thickness difference between the area between the binding pad and the fan-out area in the third area and other areas in the binding area are reduced, the flatness of the binding surface of the driving chip is improved, the driving chip is prevented from being damaged in the binding process, and the binding stability of the driving chip is improved.
Optionally, the processing the planarization layer may include: the planarization layer in the binding region is removed.
It should be noted that the planarization layer in the bonding region may be removed by a photolithography process.
Alternatively, the processing of the planarization layer may include: and thinning the planarization layer in the region between the binding pad and the fan-out region in the first region and the region between the binding pad and the fan-out region in the third region by adopting a half-tone mask process, and removing the planarization layer at the binding pad.
It should be noted that, the halftone mask process combines the two exposure processes into one process, so that one exposure process is saved, the production period is shortened, the production efficiency is improved, and the production cost is reduced.
Alternatively, the processing of the planarization layer may include: forming photoresist on the planarization layer, exposing the photoresist by adopting a mask plate, gradually reducing the exposure transmittance of the mask plate corresponding to the region between the binding pad and the fan-out region in the first region and the region between the binding pad and the fan-out region in the third region along the direction of the binding region pointing to the fan-out region, and sequentially developing and etching to gradually increase the thickness of the planarization layer in the region between the binding pad and the fan-out region in the first region and the region between the binding pad and the fan-out region in the third region along the direction of the binding region pointing to the fan-out region.
Fig. 15 is a schematic structural diagram of a display device according to an embodiment of the present invention. As shown in fig. 15, the display device 1 includes a display panel 2 according to any embodiment of the present invention, and a driving chip 3, wherein each output terminal 4 of the driving chip 3 is electrically connected to each bonding pad 201 in a one-to-one correspondence.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (12)
1. A display panel, comprising:
a display area and a non-display area surrounding the display area; the non-display area comprises a binding area and a fan-out area; the fan-out area is positioned between the display area and the binding area; the binding region comprises a first region, a second region and a third region which are sequentially arranged along a boundary extension direction parallel to the fan-out region and the display region;
the binding region is provided with a binding pad group; the bonding pad group comprises a plurality of bonding pads; along the direction that the first area points to the second area, the distance between each binding pad positioned in the first area and the display area is gradually reduced, and the distance between each binding pad positioned in the third area and the display area is gradually increased; the distances between each binding pad of the second area and the display area are equal;
the fan-out area is provided with a plurality of fan-out lines; one end of the fanout line is electrically connected with the signal line of the display area; the other end of the fanout wire is electrically connected with the binding pads in a one-to-one correspondence manner; the fan-out line electrically connected with the bonding pad of the first region extends to the first region; the fan-out line electrically connected with the bonding pad of the third region extends to the third region;
the display panel further comprises a substrate, and a pixel circuit layer and a planarization layer which are sequentially arranged on the substrate;
the vertical projection of the planarization layer on the substrate and the vertical projection of the bonding pad on the substrate do not overlap, and the thickness of the planarization layer in the area between the bonding pad and the fan-out area in the first region and the area between the bonding pad and the fan-out area in the third region is smaller than the thickness of the planarization layer of the fan-out area.
2. The display panel of claim 1, wherein the planarization layer does not overlap the bonding region.
3. The display panel of claim 1, wherein the bonding pad comprises a first conductive structure, a second conductive structure, and a third conductive structure stacked;
the pixel circuit layer comprises a first conductive layer and a second conductive layer which are stacked and insulated;
the first conductive layer forms the first conductive structure of the bond pad at the bonding region; the second conductive layer forms the second conductive structure of the bond pad at the bonding region;
the display panel further comprises an electrode layer positioned on one side of the pixel circuit layer, which is far away from the substrate; the electrode layer forms the third conductive structure of the bonding pad at the bonding region;
the first conductive structure, the second conductive structure and the third conductive structure are sequentially stacked and electrically connected;
virtual support pads are further arranged in a region between the binding pad and the fan-out region in the first region and a region between the binding pad and the fan-out region in the third region;
the vertical projection of the virtual support bonding pad on the substrate is overlapped with the vertical projection of the fanout line on the substrate.
4. The display panel according to claim 3, wherein the electrode layer forms the dummy support pad in a region between the bonding pad and the fan-out region in the first region, and a region between the bonding pad and the fan-out region in the third region.
5. The display panel according to claim 4, wherein the electrode layer comprises a first electrode layer, and a second electrode layer stacked and insulated from the first electrode layer;
the first electrode layer and/or the second electrode layer form the dummy support pad in a region between the bonding pad and the fan-out region in the first region, and a region between the bonding pad and the fan-out region in the third region.
6. The display panel of claim 3, further comprising a touch routing layer; the touch wiring layer is positioned between the planarization layer and the electrode layer; an insulating layer is arranged between the touch wiring layer and the electrode layer.
7. The display panel according to claim 1, wherein in a direction in which the binding region points toward the fan-out region, thicknesses of the planarization layer in a region between the binding pad and the fan-out region in the first region and a region between the binding pad and the fan-out region in the third region gradually increase.
8. A method for manufacturing a display panel, comprising:
sequentially forming a pixel circuit layer and a planarization layer on a substrate;
processing the planarization layer to remove the planarization layer at a bond pad, and a thickness of the planarization layer in a region between the bond pad and a fan-out region in a first region and a region between the bond pad and the fan-out region in a third region is less than a thickness of the planarization layer of the fan-out region;
wherein the display panel includes a display area and a non-display area surrounding the display area; the non-display area comprises a binding area and a fan-out area which are arranged in sequence and deviate from the display area; the binding region comprises a first region, a second region and a third region which are sequentially arranged along a boundary extension direction parallel to the fan-out region and the display region; the binding region is provided with a binding pad group; the bonding pad group comprises a plurality of bonding pads; along the direction that the first area points to the second area, the distance between each binding pad positioned in the first area and the display area is gradually reduced, and the distance between each binding pad positioned in the third area and the display area is gradually increased; the distances between each binding pad of the second area and the display area are equal; the fan-out area is provided with a plurality of fan-out lines; one end of the fanout line is electrically connected with the signal line of the display area; the other end of the fanout line is electrically connected with the binding pads in a one-to-one correspondence manner; the fan-out line electrically connected with the bonding pad of the first region extends to the first region; the fan-out line electrically connected with the bonding pad of the third region extends to the third region.
9. The method of claim 8, wherein processing the planarization layer comprises:
removing the planarization layer in the bonding region.
10. The method of claim 8, wherein processing the planarization layer comprises:
and thinning the planarization layer in the area between the binding pad and the fan-out area in the first area and the area between the binding pad and the fan-out area in the third area by adopting a half-tone mask process, and removing the planarization layer at the binding pad.
11. The method of claim 8, wherein processing the planarization layer comprises:
forming a photoresist on the planarization layer;
exposing the photoresist by using a mask; along the direction that the binding region points to the fan-out region, the exposure transmittances of the mask corresponding to the region between the binding pad and the fan-out region in the first region and the region between the binding pad and the fan-out region in the third region are gradually reduced;
developing and etching are sequentially carried out, so that the direction of the fan-out area is pointed by the binding area, the area between the binding pad and the fan-out area in the first area is increased gradually, and the thickness of the planarization layer in the area between the binding pad and the fan-out area in the third area is increased gradually.
12. A display device, comprising:
the display panel according to any one of claims 1 to 7, and a driving chip;
and each output terminal of the driving chip is electrically connected with each binding pad in a one-to-one correspondence manner.
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| CN113130612A (en) * | 2021-04-13 | 2021-07-16 | 京东方科技集团股份有限公司 | Display panel, control circuit board and display device |
| WO2022252069A1 (en) * | 2021-05-31 | 2022-12-08 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN113299218B (en) * | 2021-06-01 | 2024-03-29 | 厦门天马微电子有限公司 | Display panel and display device |
| US20240179967A1 (en) * | 2021-06-25 | 2024-05-30 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display substrate, manufacturing method thereof and display apparatus |
| CN113745393B (en) * | 2021-09-06 | 2023-09-29 | 合肥京东方瑞晟科技有限公司 | Display substrate, display panel and display device |
| CN114185210A (en) * | 2021-12-03 | 2022-03-15 | 武汉华星光电技术有限公司 | Array substrate and display panel |
| CN114203786B (en) * | 2021-12-10 | 2023-07-04 | 深圳市华星光电半导体显示技术有限公司 | Display panel and manufacturing method thereof |
| CN114255658B (en) * | 2021-12-16 | 2023-03-17 | 武汉华星光电技术有限公司 | Display panel and display device |
| US20240244901A1 (en) * | 2022-02-25 | 2024-07-18 | Yunnan Invensight Optoelectronics Technology Co., Ltd. | Display Substrate, Preparing Method thereof, and Display Apparatus |
| CN115016186B (en) * | 2022-06-30 | 2023-12-05 | 苏州华星光电技术有限公司 | Display mother board and display panel |
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