CN115311975A - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN115311975A CN115311975A CN202210949379.5A CN202210949379A CN115311975A CN 115311975 A CN115311975 A CN 115311975A CN 202210949379 A CN202210949379 A CN 202210949379A CN 115311975 A CN115311975 A CN 115311975A
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- driving circuit
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
Abstract
The application provides a display panel and display device, display panel's frame district is including first frame district and the second frame district that is located the relative both sides of display area, and display panel includes: a substrate; a driver circuit layer comprising: the pixel driving circuit comprises a plurality of pixel driving circuits arranged in the display area and a plurality of multiplexing circuits arranged in the first frame area, wherein one end of one multiplexing circuit is electrically connected with the plurality of pixel driving circuits; the signal terminal is positioned in the second frame area; the first metal layer comprises a plurality of patch cords, one end of each patch cord is electrically connected with the corresponding signal terminal, and the other end of each patch cord is electrically connected with the other end of the corresponding multiplexing circuit. This application sets up multiplex circuit in first frame district to through the patch cord will set up the signal terminal in second frame district and set up the multiplexer electric connection in first frame district, thereby reduced the frame width in second frame district greatly and walked line density, improved display panel's screen proportion and production yield.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel and a display device.
Background
In the conventional display panel, the data driving chip is directly electrically connected to the data line through the signal terminal disposed at the lower frame to output the pixel voltage to the light emitting pixel, which results in a large number of signal terminals. In order to reduce the number of signal terminals, in the related art, a multiplexing circuit (Demux) is disposed between the data driving chip and the data lines to divide a signal channel of the data driving chip into a plurality of signal channels, and then electrically connected to each of the data lines.
Because the current display technology develops towards the direction of high screen ratio, the lower frame of the display panel is required to be smaller and smaller, and the multiplexer arranged on the lower frame of the display panel occupies more space of the lower frame, so that the realization of the high screen ratio of the display panel is hindered.
Disclosure of Invention
The application provides a display panel and display device, can effectively solve the multiplexing circuit among the current display panel and occupy the great, the intensive technical problem of line layout of lower frame width that the lower frame space leads to.
In one aspect, the present application provides a display panel having a display area and a bezel area, the bezel area including a first bezel area and a second bezel area located on opposite sides of the display area,
the display panel includes:
a substrate;
a driving circuit layer disposed at one side of the substrate, the driving circuit layer including: the pixel driving circuit comprises a plurality of pixel driving circuits arranged in the display area and a plurality of multiplexing circuits arranged in a first frame area, wherein one end of one multiplexing circuit is electrically connected with the plurality of pixel driving circuits;
the signal terminal is arranged on one side of the substrate and is positioned in the second frame area;
the first metal layer is arranged on one side, far away from the substrate, of the driving circuit layer and comprises a plurality of transfer lines, one ends of the transfer lines are electrically connected with the corresponding signal terminals, and the other ends of the transfer lines are electrically connected with the other ends of the corresponding multiplexing circuits.
Optionally, the driving circuit layer further includes: a plurality of dummy pixel driving circuits disposed in the first frame area,
the display panel further includes:
the luminous layer is arranged on one side, far away from the substrate, of the first metal layer and comprises: the pixel driving circuit is electrically connected with the corresponding light-emitting pixels, and the virtual pixel driving circuit is not electrically connected with the light-emitting pixels in the display area;
wherein the dummy pixel driving circuit and the multiplexing circuit are both disposed adjacent to the pixel driving circuit of the display area.
Optionally, the multiplexing circuit is disposed in a gap region between two adjacent dummy pixel driving circuits.
Optionally, the driving circuit layer does not include a dummy pixel driving circuit, and the multiplexing circuit is disposed adjacent to the pixel driving circuit of the display area.
Optionally, the driving circuit layer further includes:
a semiconductor layer disposed at one side of the substrate, the semiconductor layer including: the first semiconductor is arranged in the display area and corresponds to the pixel driving circuit, and the second semiconductor is arranged in the first frame area and corresponds to the multiplexing circuit;
a second metal layer disposed on a side of the semiconductor layer away from the substrate, the second metal layer including: the first grid electrode is positioned in the display area and corresponds to the pixel driving circuit, and the second grid electrode is positioned in the first frame area and corresponds to the multiplexing circuit;
a third metal layer disposed on a side of the second metal layer away from the substrate, the third metal layer comprising: a first source electrode and a first drain electrode which are positioned in the display area and correspond to the pixel driving circuit, and a second source electrode and a second drain electrode which are positioned in the first frame area and correspond to the multiplexing circuit;
the first metal layer is arranged on one side of the third metal layer far away from the substrate, and the patch cord and the pixel driving circuit are at least partially overlapped.
Optionally, the driving circuit layer further includes a fourth metal layer disposed on a side of the third metal layer away from the substrate, where the fourth metal layer includes: and one end of the multiplexing circuit is electrically connected with the pixel driving circuit through the data line.
Optionally, each of the multiplexing circuits includes a data bus, a plurality of data branches, and a plurality of switch units, the data bus is disposed in the second metal layer, the data branches are disposed in the third metal layer, and the switch units include the second semiconductor, the second gate, the second source, and the second drain;
one end of the data bus is electrically connected with the other end of the patch cord, the other end of the data bus is electrically connected with one end of each of the plurality of data branch lines, the other end of each of the data branch lines is electrically connected with the second source electrode, and the second drain electrode is electrically connected with the data line.
Optionally, the driving circuit layer further includes a fifth metal layer, the fifth metal layer is disposed on a side of the second metal layer away from the substrate, and the third metal layer is disposed on a side of the fifth metal layer away from the substrate;
each multiplexing circuit further comprises a plurality of electrostatic protection circuits, and the second drain electrode is electrically connected with the data line through the electrostatic protection circuits;
wherein the ESD protection circuit comprises a first portion, and two adjacent ESD protection circuits in the multiplexing circuit are arranged, wherein the first portion of one of the ESD protection circuits is arranged on the second metal layer, and the first portion of the other ESD protection circuit is arranged on the fifth metal layer.
Optionally, each of the multiplexing circuits includes a data bus, four data branches, and four switching units, wherein,
the light emitting pixel includes: a first light emitting pixel of a first light emitting color, a second light emitting pixel of a second light emitting color, a third light emitting pixel of a third light emitting color,
the four data branches in each multiplexing circuit are electrically connected to one row of the first light-emitting pixels, one row of the second light-emitting pixels, one row of the third light-emitting pixels, and the other row of the second light-emitting pixels through different data lines.
On the other hand, the present application provides a display device, which includes a housing and the display panel described in any one of the above embodiments, wherein the housing has an accommodating space, and the display panel is disposed in the accommodating space.
The application provides a display panel and display device, this application sets up multiplex circuit in first frame district to through the patch cord will set up the signal terminal in second frame district and set up the multiplexer electric connection in first frame district, thereby reduced the frame width in second frame district greatly and walked line density, improved display panel's screen and accounted for than and the production yield.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic plan view illustrating a pixel driving circuit and a multiplexing circuit of a display panel electrically connected by a data line according to an embodiment of the present disclosure;
fig. 2 is a schematic plan view illustrating a display panel according to an embodiment of the present disclosure, in which signal terminals and a multiplexing circuit are electrically connected through a patch cord;
fig. 3 is a schematic view of a film structure of a display panel according to an embodiment of the present disclosure;
fig. 4 is a schematic plan view of a multiplexing circuit according to an embodiment of the present application;
fig. 5 is a schematic plan view of a multiplexing circuit according to a second embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the present application, are given by way of illustration and explanation only, and are not intended to limit the present application. In the present application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials. The following are detailed below, and it should be noted that the order of description of the following examples is not intended to limit the preferred order of the examples.
Example one
Fig. 1 is a schematic plan view illustrating a pixel driving circuit and a multiplexing circuit of a display panel electrically connected by a data line according to an embodiment of the present disclosure; fig. 2 is a schematic plan view illustrating a display panel according to an embodiment of the present disclosure, in which signal terminals and a multiplexing circuit are electrically connected through a patch cord; fig. 3 is a schematic view of a film structure of a display panel according to an embodiment of the present disclosure. Referring to fig. 1, 2 and 3, in one embodiment of the present application, a display panel is provided, where the display panel has a display area 01 and a bezel area 02, the bezel area 02 includes a first bezel area 021 and a second bezel area 022 located on two opposite sides of the display area 01, and the display panel includes: a substrate 10; a driving circuit layer 20 disposed on one side of the substrate 10, the driving circuit layer 20 including: a plurality of pixel driving circuits 21 disposed in the display area 01 and a plurality of multiplexing circuits 22 disposed in the first frame area 021, wherein one end of one multiplexing circuit 22 is electrically connected to the plurality of pixel driving circuits 21; a signal terminal a disposed at one side of the substrate 10 and located in the second frame region 022; the first metal layer 30 is disposed on one side of the driving circuit layer 20 away from the substrate 10, the first metal layer 30 includes a plurality of patch cords 31, one end of each patch cord 31 is electrically connected to the corresponding signal terminal a, and the other end of each patch cord 31 is electrically connected to the other end of the corresponding multiplexing circuit 22.
In the prior art, the signal terminal a is used for receiving a data signal output by a data driving chip (source IC), and the signal terminal a and the multiplexing circuit are both disposed in the second frame region, so that the frame width and the routing density of the second frame region are both large.
In the display panel provided by the present application, the patch cord 31 spans the second frame region 022, the display region 01 and the first frame region 021, and respectively with the second frame region 022 the signal terminal a and the first frame region 021 the multiplexing circuit 22 electrically connected, so that the multiplexing circuit 22 can be disposed in the second frame region 022 of the display panel, and receive the data signal output by the signal terminal a through the patch cord 31, thereby greatly reducing the frame width and the routing density of the second frame region 022 under the condition of ensuring the normal transmission of the data signal, and improving the screen occupation ratio and the production yield of the display panel.
Specifically, the first frame region 021 is located at an upper side of the display region 01, and the second frame region 022 is located at a lower side of the display region 01. Second frame region 022 is provided with signal terminal A, gate drive circuit wire winding, VDD are walked, test line and other circuits, consequently, the wiring layout of second frame region 022 is comparatively intensive, and this application is through with multiplexer circuit 22 shifts to the comparatively loose first frame region 021 of wiring layout, thereby can avoid with multiplexer circuit 22 sets up the great and too intensive problem of wiring layout of second frame region 022 width that second frame region 022 leads to.
Further, the third frame region 023 is located at the left side of the display region 01, and the fourth frame region 024 is located at the right side of the display region 01. At least one of the third frame region 023 and the fourth frame region 024 is provided with a gate driving circuit, and the gate driving circuit is wound with the gate driving circuit and is electrically connected with the gate driving circuit.
In some embodiments of the present application, the driving circuit layer 20 further includes: a plurality of dummy pixel driving circuits (not shown) disposed in the first bezel area 021, the display panel further comprising: a light-emitting layer 404 disposed on a side of the first metal layer 30 away from the substrate 10, the light-emitting layer 404 comprising: the pixel driving circuit 21 is electrically connected with the corresponding light-emitting pixels, and the virtual pixel driving circuit is not electrically connected with the light-emitting pixels in the display area 01; wherein the dummy pixel driving circuit and the multiplexing circuit 22 are disposed adjacent to the pixel driving circuit 21 of the display area 01.
In the display panel provided by the present application, the dummy pixel driving circuit is disposed adjacent to the pixel driving circuit 21 of the display area 01, and is used for preventing external static electricity from directly damaging the pixel driving circuit 21 of the display area 01, and enabling the patterned structure of the pixel driving circuit 21 of the display area 01 to be etched more uniformly in the preparation process of the display panel, thereby ensuring the film forming quality. The virtual pixel driving circuit and the multiplexing circuit 22 are close to the pixel driving circuit 21 of the display area 01, so that the multiplexing circuit 22 can also play a role in preventing external static electricity from directly damaging the pixel driving circuit 21 of the display area 01 and etching the patterned structure of the pixel driving circuit 21 of the display area 01 to be more uniform.
Further, the multiplexing circuit 22 is disposed in a gap region between two adjacent dummy pixel driving circuits.
In the display panel provided by the present application, since the dummy pixel driving circuit occupies a partial space of the first frame region 021, the present application can fully utilize the adjacent two gap regions between the dummy pixel driving circuits by setting the multiplexing circuit 22 in the adjacent two gap regions between the dummy pixel driving circuits without increasing the width of the first frame region 021, so as to complete the setting of the multiplexing circuit 22.
Of course, the present application does not require that the first frame area 021 is provided with the dummy pixel driving circuit, in other embodiments of the present application, the driving circuit layer 20 does not include the dummy pixel driving circuit, and the multiplexing circuit 22 is provided adjacent to the pixel driving circuit 21 of the display area 01. Since the multiplexing circuit 22 adjacent to the pixel driving circuit 21 can also prevent external static electricity from directly damaging the pixel driving circuit 21 of the display area 01 and etch the patterned structure of the pixel driving circuit 21 of the display area 01 more uniformly, the dummy pixel driving circuit of the first frame area 021 can be omitted.
Fig. 4 is a schematic plan view of a multiplexing circuit of a first frame area according to an embodiment of the present disclosure. Referring to fig. 3 and 4, in some embodiments of the present application, the driving circuit layer 20 further includes: the first via hole 24, through which the patch cord 31 is electrically connected to the multiplexing circuit 22, is provided. In order to dispose the multiplexing circuit 22 adjacent to the pixel driving circuit 21 of the display area 01, the first via hole 24 is disposed on a side of the multiplexing circuit 22 away from the display area 01.
In some embodiments of the present application, the driving circuit layer 20 further includes: a semiconductor layer 203 disposed on one side of the substrate 10, the semiconductor layer 203 including: a first semiconductor disposed in the display region 01 and corresponding to the pixel driving circuit 21, and a second semiconductor disposed in the first frame region 021 and corresponding to the multiplexing circuit 22; a second metal layer 205 disposed on a side of the semiconductor layer 203 away from the substrate 10, the second metal layer 205 comprising: a first gate located in the display region 01 and corresponding to the pixel driving circuit 21, and a second gate located in the first frame region 021 and corresponding to the multiplexing circuit 22; a third metal layer 213 disposed on a side of the second metal layer 205 away from the substrate 10, the third metal layer 213 comprising: a first source and a first drain in the display region 01 and corresponding to the pixel driving circuit 21, and a second source and a second drain in the first frame region 021 and corresponding to the multiplexing circuit 22; the first metal layer 30 is disposed on a side of the third metal layer 213 away from the substrate 10, and the patch cord 31 and the pixel driving circuit 21 are at least partially overlapped.
In some embodiments of the present application, the driving circuit layer 20 further includes a fourth metal layer 215 disposed on a side of the third metal layer 213 far from the substrate 10, where the fourth metal layer 215 includes: and a plurality of data lines 23 located in the display area 01, wherein one end of the multiplexing circuit 22 is electrically connected to the pixel driving circuit 21 through the data lines 23.
With continued reference to fig. 3 and 4, in some embodiments of the present application, each of the multiplexing circuits 22 includes a data bus 221, a plurality of data dividers 222, and a plurality of switch units 223, the data bus 221 is disposed in the second metal layer 205, the data dividers 222 are disposed in the third metal layer 213, and the switch units 223 include the second semiconductor, the second gate, the second source, and the second drain; one end of the data bus 221 is electrically connected to the other end of the patch cord 31, the other end of the data bus 221 is electrically connected to one end of each of the data distribution lines 222, the other end of each of the data distribution lines 222 is electrically connected to the second source, and the second drain is electrically connected to the data line 23.
Further, one end of the data bus 221 is electrically connected to the other end of the patch cord 31 through the first via 24.
In some embodiments of the present application, each of the multiplexing circuits 22 includes a data bus 221, four data distribution lines 222, and four switching units 223.
In the conventional technology, each multiplexing circuit includes only three data branches and three switch units, that is, the multiplexing circuit 22 provided in the present application has a larger number of wirings and a more complex structure. This application is through will lay wire quantity more, the structure is more complicated multiplex circuit 22 sets up first frame area 021, and make multiplex circuit 22 closes on the display area 01 pixel drive circuit 21 sets up, thereby can reduce greatly the frame width and the line density of walking of second frame area 022 have improved display panel's screen and have accounted for than and the production yield, play simultaneously and prevent that outside static from directly injuring pixel drive circuit 21 and messenger the display area 01 patterning structure etching's of pixel drive circuit 21 more even effect.
In some embodiments of the present application, the light emitting pixel includes: the first light-emitting pixel of the first light-emitting color, the second light-emitting pixel of the second light-emitting color, and the third light-emitting pixel of the third light-emitting color, wherein the four data branches 222 in each multiplexing circuit 22 are electrically connected to one row of the first light-emitting pixels, one row of the second light-emitting pixels, one row of the third light-emitting pixels, and the other row of the second light-emitting pixels through different data lines 23.
Further, the light emission color of the first light-emitting pixel is red, the light emission color of the second light-emitting pixel is green, and the light emission color of the third light-emitting pixel is blue.
Further, the display panel is, for example, an Organic Light-Emitting Diode (OLED) display panel. Of course, the present application does not limit the type of the display panel, and in other embodiments of the present application, the type of the display panel may also be a liquid crystal display panel or an inorganic light emitting diode display panel.
The film structure of the display area 01 of the display panel is further described below. With continued reference to fig. 3, in some embodiments of the present application, the base board 10 includes a first substrate board 101, a first buffer layer 102, and a second substrate board 103 that are sequentially stacked, and the driving circuit layer 20 includes a light-shielding metal layer 201, a second buffer layer 202, a semiconductor layer 203, a first gate insulating layer 204, the second metal layer 205, a second gate insulating layer 206, a fifth metal layer 207, an interlayer dielectric layer 208, an active layer 209, a third gate insulating layer 210, a sixth metal layer 211, a passivation layer 212, the third metal layer 213, a first planarization layer 214, a fourth metal layer 215, and a second planarization layer 216 that are sequentially stacked in a direction away from the first substrate board 101 of the second substrate board 103; the first metal layer 30 is arranged on the surface of the second flat layer 216 on the side facing away from the substrate 10; a third flat layer 301 covers the surface of one side of the first metal layer 30, which is far away from the substrate 10; a light emitting function layer 40 is formed on a surface of the third flat layer 301 on a side away from the substrate 10, and the light emitting function layer 40 includes a first electrode layer 401, a pixel definition layer 402, a spacer layer 403, the light emitting layer 404, and a cathode layer 405, which are sequentially stacked in a direction in which the second substrate 103 is away from the first substrate 101. Of course, in other embodiments of the present application, the pixel defining layer 402 and the spacer layer 403 may be formed by a single film forming process.
Further, the first via hole 24 penetrates through the second planarization layer 216, the first planarization layer 214, the passivation layer 212, the third gate insulating layer 210, the interlayer dielectric layer 208, and the second gate insulating layer 206, so that the patch cord 31 in the first metal layer 30 is electrically connected to the data bus 221 in the second metal layer through the first via hole 24. It should be noted that the first via hole 24 is formed through at least one etching process.
On the other hand, the application also provides a display device, the display device includes a housing and any one of the above display panels, wherein the housing has an accommodating space, and the display panel is disposed in the accommodating space.
Example two
Fig. 5 is a schematic plan view of a multiplexing circuit of a first bezel area according to a second embodiment of the present application. Referring to fig. 1-3 and 5, a second embodiment of the present application provides a display panel, the display panel having a display area 01 and a border area 02, the border area 02 including a first border area 021 and a second border area 022 located at two opposite sides of the display area 01, the display panel including: a substrate 10; a driving circuit layer 20 disposed on one side of the substrate 10, the driving circuit layer 20 including: a plurality of pixel driving circuits 21 disposed in the display area 01 and a plurality of multiplexing circuits 22 disposed in the first frame area 021, wherein one end of one multiplexing circuit 22 is electrically connected to the plurality of pixel driving circuits 21; a signal terminal a disposed at one side of the substrate 10 and located in the second frame region 022; the first metal layer 30 is disposed on one side of the driving circuit layer 20 away from the substrate 10, the first metal layer 30 includes a plurality of patch cords 31, one end of each patch cord 31 is electrically connected to the corresponding signal terminal a, and the other end of each patch cord 31 is electrically connected to the other end of the corresponding multiplexing circuit 22.
The display panel provided in embodiment two of the present application is similar to the display panel in embodiment one, and this application is not repeated again for the same parts, except that the driving circuit layer 20 further includes a fifth metal layer 207, the fifth metal layer 207 is disposed on one side of the second metal layer 205 far away from the substrate 10, and the third metal layer 213 is disposed on one side of the fifth metal layer 207 far away from the substrate 10; each of the multiplexing circuits 22 further includes a plurality of esd protection circuits 224, and the second drain is electrically connected to the data line 23 through the esd protection circuit 224; wherein the electrostatic protection circuit 224 comprises a first part 2241, two adjacent parts in the multiplexing circuit 22 in the electrostatic protection circuit 224, one of the first part 2241 of the electrostatic protection circuit 224 is located in the second metal layer 205, and the other one of the first part 2241 of the electrostatic protection circuit 224 is located in the fifth metal layer 207.
In the display panel provided by the present application, since each of the multiplexing circuits 22 further includes a plurality of electrostatic protection circuits 224, the electrostatic protection circuits 224 are configured to further enhance the electrostatic protection capability of the multiplexing circuits 22. In addition, in two adjacent esd protection circuits 224 of the multiplexer circuit 22, the first portion 2241 of one of the esd protection circuits 224 is located in the second metal layer 205, and the first portion 2241 of the other esd protection circuit 224 is located in the fifth metal layer 207, so that the esd protection capability of the esd protection circuit 224 can be further improved, and the interference of the two adjacent esd protection circuits 224 of the multiplexer circuit 22 can be reduced.
To sum up, the application provides a display panel and display device, display panel has display area and frame district, the frame district is including being located the first frame district and the second frame district of the relative both sides of display area, display panel includes: a substrate; a driving circuit layer disposed at one side of the substrate, the driving circuit layer including: the pixel driving circuits are arranged in the display area, the multiplexing circuits are arranged in the first frame area, and one end of one multiplexing circuit is electrically connected with the pixel driving circuits; the signal terminal is arranged on one side of the substrate and is positioned in the second frame area; the first metal layer is arranged on one side, far away from the substrate, of the driving circuit layer and comprises a plurality of transfer lines, one ends of the transfer lines are electrically connected with the corresponding signal terminals, and the other ends of the transfer lines are electrically connected with the other ends of the corresponding multiplexing circuits. This application sets up multiplex circuit in first frame district to through the patch cord will set up the signal terminal in second frame district and set up the multiplexer electric connection in first frame district, thereby reduced the frame width in second frame district greatly and walked line density, improved display panel's screen proportion and production yield.
The display panel and the display device provided by the embodiments of the present application are described in detail above, and the principles and embodiments of the present application are described herein by applying specific examples, and the description of the embodiments is only used to help understand the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A display panel is characterized in that the display panel is provided with a display area and a frame area, the frame area comprises a first frame area and a second frame area which are positioned at two opposite sides of the display area,
the display panel includes:
a substrate;
a driving circuit layer disposed at one side of the substrate, the driving circuit layer including: the pixel driving circuit comprises a plurality of pixel driving circuits arranged in the display area and a plurality of multiplexing circuits arranged in a first frame area, wherein one end of one multiplexing circuit is electrically connected with the plurality of pixel driving circuits;
the signal terminal is arranged on one side of the substrate and is positioned in the second frame area;
the first metal layer is arranged on one side, far away from the substrate, of the driving circuit layer and comprises a plurality of transfer lines, one ends of the transfer lines are electrically connected with the corresponding signal terminals, and the other ends of the transfer lines are electrically connected with the other ends of the corresponding multiplexing circuits.
2. The display panel according to claim 1, wherein the driving circuit layer further comprises: a plurality of dummy pixel driving circuits disposed in the first frame area,
the display panel further includes:
the luminous layer is arranged on one side, far away from the substrate, of the first metal layer and comprises: the pixel driving circuit is electrically connected with the corresponding light-emitting pixels, and the virtual pixel driving circuit is not electrically connected with the light-emitting pixels in the display area;
wherein the dummy pixel driving circuit and the multiplexing circuit are both disposed adjacent to the pixel driving circuit of the display area.
3. The display panel according to claim 2, wherein the multiplexing circuit is provided in a gap region between two adjacent dummy pixel driving circuits.
4. The display panel of claim 1, wherein the driving circuit layer does not include dummy pixel driving circuits, and the multiplexing circuit is disposed adjacent to the pixel driving circuits of the display area.
5. The display panel according to claim 1, wherein the driving circuit layer further comprises:
a semiconductor layer disposed at one side of the substrate, the semiconductor layer including: the first semiconductor is arranged in the display area and corresponds to the pixel driving circuit, and the second semiconductor is arranged in the first frame area and corresponds to the multiplexing circuit;
a second metal layer disposed on a side of the semiconductor layer away from the substrate, the second metal layer including: the first grid electrode is positioned in the display area and corresponds to the pixel driving circuit, and the second grid electrode is positioned in the first frame area and corresponds to the multiplexing circuit;
a third metal layer disposed on a side of the second metal layer away from the substrate, the third metal layer comprising: the first source electrode and the first drain electrode are positioned in the display area and correspond to the pixel driving circuit, and the second source electrode and the second drain electrode are positioned in the first frame area and correspond to the multiplexing circuit;
the first metal layer is arranged on one side of the third metal layer far away from the substrate, and the patch cord and the pixel driving circuit are at least partially overlapped.
6. The display panel according to claim 5, wherein the driving circuit layer further comprises a fourth metal layer disposed on a side of the third metal layer away from the substrate, the fourth metal layer comprising: and one end of the multiplexing circuit is electrically connected with the pixel driving circuit through the data line.
7. The display panel according to claim 6, wherein each of the multiplexing circuits includes a data bus line, a plurality of data branches, and a plurality of switching units, the data bus line is disposed in the second metal layer, the data branches are disposed in the third metal layer, and the switching units include the second semiconductor, the second gate electrode, the second source electrode, and the second drain electrode;
one end of the data bus is electrically connected with the other end of the patch cord, the other end of the data bus is electrically connected with one end of each of the plurality of data branch lines, the other end of each of the data branch lines is electrically connected with the second source electrode, and the second drain electrode is electrically connected with the data line.
8. The display panel according to claim 7, wherein the driving circuit layer further comprises a fifth metal layer, the fifth metal layer is disposed on a side of the second metal layer away from the substrate, and the third metal layer is disposed on a side of the fifth metal layer away from the substrate;
each multiplexing circuit further comprises a plurality of electrostatic protection circuits, and the second drain electrode is electrically connected with the data line through the electrostatic protection circuits;
wherein the ESD protection circuit comprises a first portion, and two adjacent ESD protection circuits in the multiplexing circuit, wherein the first portion of one of the ESD protection circuits is located on the second metal layer, and the first portion of the other ESD protection circuit is located on the fifth metal layer.
9. The display panel of claim 6, wherein each of the multiplexing circuits comprises a data bus, four data distribution lines, and four switching units, wherein,
the light emitting pixel includes: a first light emitting pixel of a first light emitting color, a second light emitting pixel of a second light emitting color, a third light emitting pixel of a third light emitting color,
the four data branches in each multiplexing circuit are electrically connected to one row of the first light-emitting pixels, one row of the second light-emitting pixels, one row of the third light-emitting pixels, and the other row of the second light-emitting pixels through different data lines.
10. A display device, comprising a housing and the display panel of any one of claims 1 to 9, wherein the housing has a receiving space, and the display panel is disposed in the receiving space.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210949379.5A CN115311975A (en) | 2022-08-09 | 2022-08-09 | Display panel and display device |
| PCT/CN2023/103631 WO2024032210A1 (en) | 2022-08-09 | 2023-06-29 | Display panel and display apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210949379.5A CN115311975A (en) | 2022-08-09 | 2022-08-09 | Display panel and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115311975A true CN115311975A (en) | 2022-11-08 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210949379.5A Pending CN115311975A (en) | 2022-08-09 | 2022-08-09 | Display panel and display device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN115311975A (en) |
| WO (1) | WO2024032210A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024032210A1 (en) * | 2022-08-09 | 2024-02-15 | 武汉华星光电半导体显示技术有限公司 | Display panel and display apparatus |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102291491B1 (en) * | 2015-01-15 | 2021-08-20 | 삼성디스플레이 주식회사 | Display apparatus and driving method thereof |
| CN109031828B (en) * | 2018-08-23 | 2021-04-30 | 上海中航光电子有限公司 | Array substrate, driving method thereof, display panel and display device |
| CN109887458B (en) * | 2019-03-26 | 2022-04-12 | 厦门天马微电子有限公司 | Display panel and display device |
| CN110197636A (en) * | 2019-06-28 | 2019-09-03 | 厦门天马微电子有限公司 | Display panel and display device |
| CN114999412A (en) * | 2021-09-23 | 2022-09-02 | 荣耀终端有限公司 | Array substrate, display panel, display module and electronic equipment |
| CN115311975A (en) * | 2022-08-09 | 2022-11-08 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
| CN115938272A (en) * | 2022-12-29 | 2023-04-07 | 武汉天马微电子有限公司 | Display panel and display device |
-
2022
- 2022-08-09 CN CN202210949379.5A patent/CN115311975A/en active Pending
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2023
- 2023-06-29 WO PCT/CN2023/103631 patent/WO2024032210A1/en unknown
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024032210A1 (en) * | 2022-08-09 | 2024-02-15 | 武汉华星光电半导体显示技术有限公司 | Display panel and display apparatus |
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| Publication number | Publication date |
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| WO2024032210A1 (en) | 2024-02-15 |
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