CN113870713B - Display panel and display device - Google Patents
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- CN113870713B CN113870713B CN202111152952.1A CN202111152952A CN113870713B CN 113870713 B CN113870713 B CN 113870713B CN 202111152952 A CN202111152952 A CN 202111152952A CN 113870713 B CN113870713 B CN 113870713B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
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- Engineering & Computer Science (AREA)
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- General Physics & Mathematics (AREA)
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- Computer Hardware Design (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The application discloses a display panel and a display device, and belongs to the technical field of display. The display panel may include: the sub-pixels, the data signal lines and the fan-out leads are located in the display area, and the connection leads are located in the non-display area. The fan-out lead wires can be positioned in the display area and do not occupy the space of the non-display area, the width of the non-display area in the display panel is smaller, the screen occupation ratio of the display device comprising the display panel is effectively improved, and the display effect of the display device is effectively improved. And because the fan-out lead wires positioned in the display area and the conductive structures in the sub-pixels are arranged in the same layer, the fan-out lead wires can be arranged in the display area without arranging additional conductive patterns in the display panel, thereby effectively simplifying the manufacturing difficulty of the display panel and reducing the manufacturing cost of the display panel.
Description
Technical Field
The present application relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
With the development of display technology, display devices are increasingly used in products with display functions, such as smart phones, tablet computers, digital cameras, aircraft instruments, televisions, and the like.
The display device may generally include a display panel and a driving chip. The display panel has a display area and a non-display area, and the display panel may include: a plurality of sub-pixels and a plurality of data signal lines in the display area, and a plurality of fan-out leads in the non-display area. Each data signal line may be electrically connected to a column of sub-pixels, and an end of each data signal line may be electrically connected to a fan-out lead, one end of the fan-out lead away from the data signal line being used for connecting with a driving chip. Thus, the driving chip can send driving signals to the data signal lines through the fan-out lead wires, so that the display panel can display corresponding images.
However, the width of the non-display area in the current display panel is large, which results in a relatively low screen occupation of the display panel, and affects the display effect of the display panel.
Disclosure of Invention
The embodiment of the application provides a display panel and a display device. The problem that the display panel screen occupation is relatively low due to the fact that the width of a non-display area in the display panel in the prior art is relatively large can be solved, and the technical scheme is as follows:
in one aspect, there is provided a display panel having a display area and a non-display area located at a periphery of the display area, the display panel comprising:
A plurality of array-arranged sub-pixels, a plurality of data signal lines and a plurality of fan-out leads, wherein the array-arranged sub-pixels, the data signal lines and the fan-out leads are positioned in the display area, one data signal line is electrically connected with one row of the sub-pixels, and the end part of one data signal line is electrically connected with the first end of one fan-out lead;
and a plurality of connection leads located in the non-display area, one of the connection leads being electrically connected to a second end of one of the fan-out leads, the plurality of connection leads being for electrically connecting to a driving chip;
the sub-pixels are provided with conductive structures, and the fan-out leads and the conductive structures are arranged on the same layer and are made of the same material.
Optionally, the sub-pixel includes: and the anode layer and the fan-out lead in the light-emitting device are arranged on the same layer and are made of the same material.
Optionally, the sub-pixel includes: and the shading metal layer and the fan-out lead are arranged on the same layer and are made of the same material.
Optionally, the fan-out lead includes: a first sub-line segment connected with the end of the data signal line, and a second sub-line segment connected with the connecting lead, wherein the first sub-line segment is electrically connected with the second sub-line segment, and the extending direction of the first sub-line segment is intersected with the extending direction of the second sub-line segment;
Wherein an extending direction of one of the first sub-line segment and the second sub-line segment is the same as an extending direction of the data signal line;
or, the extending direction of the first sub-line segment and the extending direction of the second sub-line segment are intersected with the extending direction of the data signal line.
Optionally, the display panel further includes: the plurality of virtual electrodes and the plurality of fan-out leads are uniformly distributed in the display area;
the virtual electrode and the fan-out lead are arranged on the same layer, and the materials are the same.
Optionally, the fan-out lead includes: a third sub-line segment and a fourth sub-line segment which are arranged in different layers and are electrically connected with each other;
the sub-pixel includes: and the first electrode in the pixel driving circuit and the third sub-line segment are arranged in the same layer, and the materials are the same, and the second electrode in the pixel driving circuit and the fourth sub-line segment are arranged in the same layer, and the materials are the same.
Optionally, the number of the third sub-line segments in the fan-out lead is two, and the number of the fourth sub-line segments is one;
wherein, the first end of one of the third sub-line segments in the fan-out lead is electrically connected with the end part of the data signal line, and the first end of the other third sub-line segment is electrically connected with the connecting lead; and two ends of the fourth sub-line segment are respectively and electrically connected with the second ends of the two third sub-line segments.
Optionally, the extending direction of the third sub-line segment is parallel to the extending direction of the data signal line, and the third sub-line segment and the data signal line are arranged in the same layer and are made of the same material;
the fan-out lead further includes: and a switching sub-line segment for connecting an end of the data signal line and the first end of the third sub-line segment.
Optionally, the display panel further includes: the signal transmission lines are positioned in the display area and electrically connected with one row of the sub-pixels, the extending direction of the signal transmission lines is parallel to the extending direction of the fourth sub-line segment, and the signal transmission lines and the fourth sub-line segment are arranged on the same layer and are made of the same material.
Optionally, the first electrode is a source/drain electrode of a thin film transistor in the pixel driving circuit, or the first electrode is a transfer electrode electrically connected to the source/drain electrode in the pixel driving circuit;
the second electrode is one of two electrodes of a storage capacitor in the pixel driving circuit.
Optionally, the plurality of data signal lines include: at least two first data signal lines and at least two second data signal lines;
the plurality of connection leads includes: at least two first connecting leads and at least two second connecting leads;
The at least two first data signal lines are in one-to-one correspondence with the fan-out leads and in one-to-one correspondence with the at least two first connecting leads, and the first data signal lines are electrically connected with the corresponding fan-out leads and the corresponding first connecting leads in sequence;
the at least two second data signal lines are in one-to-one correspondence with the at least two second connection leads, and the second data signal lines are electrically connected with the corresponding second connection leads.
Optionally, the lengths of the second connection leads are the same, and are larger than the lengths of the first connection leads.
Optionally, the length of each first connection lead is inversely related to the length of the corresponding fan-out lead.
In another aspect, there is provided a display apparatus including: a power supply assembly and a display panel as described in any one of the above; the power supply assembly is connected with the display panel and is used for supplying power to the display panel.
The technical scheme provided by the embodiment of the application has the beneficial effects that at least:
a display panel, comprising: the sub-pixels, the data signal lines and the fan-out leads are located in the display area, and the connection leads are located in the non-display area. Since the fan-out lead may be located within the display area, it does not occupy space in the non-display area. Therefore, the width of the non-display area in the display panel is smaller, the screen occupation ratio of the display device comprising the display panel is effectively improved, and the display effect of the display device is effectively improved. And because the fan-out lead wires positioned in the display area and the conductive structures in the sub-pixels are arranged in the same layer, the fan-out lead wires can be arranged in the display area without arranging additional conductive patterns in the display panel, thereby effectively simplifying the manufacturing difficulty of the display panel and reducing the manufacturing cost of the display panel.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a display device according to the related art;
fig. 2 is a schematic structural view of another display device provided in the related art;
FIG. 3 is a schematic view of the film structure of the display panel shown in FIG. 2 at A-A';
FIG. 4 is a top view of a display panel according to an embodiment of the present application;
FIG. 5 is a schematic view of the film structure of the display panel at B-B' shown in FIG. 4;
fig. 6 is a schematic diagram of a film structure of a sub-pixel in a display panel according to an embodiment of the application;
fig. 7 is a schematic diagram of a film structure of another display panel according to an embodiment of the application;
fig. 8 is a schematic diagram of a film structure of another display panel according to an embodiment of the present application;
fig. 9 is a top view of the display panel shown in fig. 7 or 8;
FIG. 10 is a schematic diagram showing a distribution of first sub-segments in sub-pixels arranged in RGB according to an embodiment of the present application;
FIG. 11 is a schematic diagram showing a distribution of second sub-segments in sub-pixels arranged in RGB according to an embodiment of the present application;
fig. 12 is a schematic diagram of a distribution of a first sub-line segment in sub-pixels arranged in RGGB according to an embodiment of the present application;
fig. 13 is a schematic diagram of a distribution of a second sub-line segment in sub-pixels arranged in RGGB according to an embodiment of the present application;
FIG. 14 is another top view of the display panel shown in FIG. 7 or FIG. 8;
FIG. 15 is a schematic diagram showing the distribution of another first sub-line segment and a second sub-line segment in sub-pixels arranged in RGB according to the embodiment of the present application;
FIG. 16 is a schematic diagram showing the distribution of another first sub-line segment and a second sub-line segment in sub-pixels arranged in RGGB according to an embodiment of the present application;
FIG. 17 is a further top view of the display panel shown in FIG. 7 or FIG. 8;
FIG. 18 is a top view of another display panel according to an embodiment of the present application;
FIG. 19 is a schematic view of the film structure of the display panel at C-C' shown in FIG. 18;
fig. 20 is a partial enlarged view at D shown in fig. 18;
FIG. 21 is a top view of a subpixel in the display panel shown in FIG. 18;
Fig. 22 is a schematic diagram showing a relationship between fan-out leads and data signal lines and connection leads according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail with reference to the accompanying drawings.
In the related art, please refer to fig. 1, fig. 1 is a schematic diagram of a display device according to the related art. The display device generally includes: a display panel 00 and a driving chip 01. The display panel 00 has a display area 0a and a non-display area 0b located at the periphery of the display area 0 a.
The display panel 00 may include: a plurality of subpixels (not shown) and a plurality of data signal lines 10 in the display area 0a, and a plurality of fan-out leads 20 in the non-display area 0b. Each data signal line 10 may be electrically connected to a column of sub-pixels, and an end of each data signal line 10 may be electrically connected to one fan-out lead 20, and an end of the fan-out lead 20 remote from the data signal line 10 may be connected to the driving chip 01. The fan-out lead 20 can be used for realizing the electrical connection between the data signal line 10 and the driving chip 01 in the display area 0a, so that the driving chip 01 can send driving signals to the data signal line through the fan-out lead 20, and can send out corresponding light after receiving corresponding driving signals by the sub-pixels, and further, the display panel 00 can display corresponding images.
However, since the length of the driving chip 01 is generally smaller than the width of the display panel 02, the plurality of fan-out leads 20 need to be arranged in the non-display area 0b in a wiring manner converging from both sides to the middle. Such wiring needs to occupy a certain space in the non-display area 0 b. As such, the width of the non-display area 0b is generally large, resulting in a relatively low screen footprint of the display device.
In order to increase the screen ratio of the display device, the fan-out lead 20 may be disposed within the display area 0 a. For example, referring to fig. 2, fig. 2 is a schematic structural diagram of another display device provided in the related art. The ends of the data signal lines 10 in the display panel may be electrically connected to the fan-out leads 20 located in the display area 0a, and the fan-out leads 20 may be arranged in the display area 0a in an inclined wiring manner to ensure that a plurality of fan-out leads arranged in the display area 0a may converge from both sides to the middle. Since the fan-out lead 20 is arranged in the display area 0a, it does not occupy the space of the non-display area 0 b. Therefore, by arranging the fan-out leads in the display area 0a, the width of the non-display area 0b can be ensured to be smaller, and the screen occupation ratio of the display device can be effectively improved.
Since the display area 0a also needs to be arranged with signal lines in a lateral direction (e.g., a gate line, an initial signal line, etc.) and signal lines in a longitudinal direction (e.g., a data signal line 10, a power signal line, etc.). Therefore, when the fan-out lead 20 is arranged in the display area 0a in an inclined wiring manner, the fan-out lead 20 tends to cross the signal line in a lateral direction or the signal line in a longitudinal direction. In order to ensure that a short circuit phenomenon does not occur between various signal lines in the display area 0a, it is necessary to ensure that the fan-out lead 20 is disposed in a different layer from the signal line of the transverse signal line and in a different layer from the signal line of the longitudinal signal line.
For this reason, as shown in fig. 3, fig. 3 is a schematic view of the film structure of the display panel at A-A' shown in fig. 2. The transverse signal lines are generally distributed within the first conductive patterns 30 and the second conductive patterns 40, and the longitudinal signal lines are generally distributed within the third conductive patterns 50. Wherein the first conductive pattern 30 may include: a gate line in the lateral signal line; the second conductive pattern 40 may include: an initial signal line of the transverse signal lines; the third conductive pattern 50 may include: a data signal line 10 and a power signal line among the vertical signal lines. The fan-out lead 20 arranged in the display area 0a needs to be located in the fourth conductive pattern 60, so that the fan-out lead 20 can be ensured not to overlap with the transverse signal line at the crossing position, and also not to overlap with the longitudinal signal line at the crossing position.
Therefore, when the fan-out lead 001 is disposed in the display area 0a, an additional conductive layer (i.e., the fourth conductive pattern 60) is needed to be added to the display panel 00 to manufacture the fan-out lead, which results in a difficult manufacturing and high manufacturing cost of the display panel.
While there are also four-layer conductive layer structures for current display panels, such display panels are directed to high refresh rate display products. That is, it is necessary to ensure that the data signal lines 10 among the longitudinal signal lines are arranged in the fourth conductive patterns 60 to ensure that the distance between the data signal lines 10 and the initial signal lines among the second conductive patterns 40 is long, thereby reducing the influence of the signals loaded on the initial signal lines on the signals loaded on the data signal lines 10. In this case, a fifth conductive layer needs to be additionally added to the display panel 00 to arrange the fan-out lead 20. As such, manufacturing difficulties for display panels in display products with high refresh rates remain large and manufacturing costs remain high.
Referring to fig. 4 and 5, fig. 4 is a top view of a display panel according to an embodiment of the application, and fig. 5 is a schematic diagram of a film structure of the display panel at B-B' shown in fig. 4. The display panel 000 has a display area 00a and a non-display area 00b located at the periphery of the display area 00 a. The display panel 000 may include: a plurality of sub-pixels 300 arranged in an array, a plurality of data signal lines 100 and a plurality of fan-out leads 200 located in the display area 00a, and a plurality of connection leads 400 located in the non-display area 00b.
One of the data signal lines 100 may be electrically connected to one column of the sub-pixels 300, and an end of one of the data signal lines 100 is electrically connected to a first end of one of the fan-out leads 200. One connection lead 400 is electrically connected to a second end of one of the fan-out leads 200, and a plurality of connection leads 400 may be used to electrically connect with a driving chip. In this way, the driving chip may transmit the driving signal to the sub-pixel 300 electrically connected to the data signal line 100 through the plurality of connection leads 400, the plurality of fan-out leads 200, and the plurality of data signal lines 100, so that the sub-pixel 300 may emit light based on the driving signal, and further the display panel 000 may display a corresponding picture.
In addition, the sub-pixel 300 in the display panel has a conductive structure 300a, and the fan-out lead 200 may be disposed in the same layer and material as the conductive structure 300a in the sub-pixel 300. That is, the fan-out lead 200 is formed using the same patterning process as the conductive structures in the sub-pixel 300. It should be noted that, the primary patterning process herein, and the primary patterning process in the following embodiments, each include: photoresist coating, exposure, development, etching, and photoresist stripping.
In this case, since the fan-out lead 200 located in the display area 00a is disposed in the same layer as the conductive structure 300a in the sub-pixel 300. Therefore, the fan-out lead 200 can be disposed in the display area 00a without providing an additional conductive pattern in the display panel, thereby effectively simplifying the manufacturing difficulty of the display panel 00 and reducing the manufacturing cost of the display panel 00.
In summary, the display panel provided in the embodiment of the application includes: the sub-pixels, the data signal lines and the fan-out leads are located in the display area, and the connection leads are located in the non-display area. Since the fan-out lead may be located within the display area, it does not occupy space in the non-display area. Therefore, the width of the non-display area in the display panel is smaller, the screen occupation ratio of the display device comprising the display panel is effectively improved, and the display effect of the display device is effectively improved. And because the fan-out lead wires positioned in the display area and the conductive structures in the sub-pixels are arranged in the same layer, the fan-out lead wires can be arranged in the display area without arranging additional conductive patterns in the display panel, thereby effectively simplifying the manufacturing difficulty of the display panel and reducing the manufacturing cost of the display panel.
Fig. 6 is a schematic diagram of a film structure of a sub-pixel in a display panel according to an embodiment of the application. The display panel 000 may further include: the substrate 001, and each sub-pixel 300 in the display panel 000 may be located on the substrate 001. Each sub-pixel 300 may include: a light emitting device 301, a pixel driving circuit 303, and a light shielding metal layer 302.
Among them, the light emitting device 301 may include: an anode layer 3011, a light-emitting layer 3012, and a cathode layer 3013 are stacked.
The pixel driving circuit 303 may include: at least one thin film transistor, a storage capacitor, and a transfer electrode 3036. The thin film transistor may include: source and drain electrodes 3031, a gate electrode 3032, and an active layer 3033, wherein the source and drain electrodes 3031 are a source electrode and a drain electrode, the source electrode and the drain electrode are all overlapped with the active layer 3033, one of the source electrode and the drain electrode is electrically connected with the anode layer 3011 in the light emitting device 301 through a transit electrode 3036, and the other of the source electrode and the drain electrode needs to be electrically connected with the data signal line 100; the gate electrode 3032 is insulated from the active layer 3033. The storage capacitor may include: two electrodes provided in different layers, for example, the two electrodes may be a first capacitor electrode 3034 and a second capacitor electrode 3035, respectively, the first capacitor electrode 3034 is insulated from the second capacitor electrode 3035, and the front projection of the first capacitor electrode 3034 on the substrate 001 and the front projection of the second capacitor electrode 3035 on the substrate 001 at least partially overlap. Note that the first capacitor electrode 3034 in the storage capacitor may be provided in the same layer as the gate electrode 3032 and made of the same material. It should be noted that, in the embodiment of the present application, the thin film transistor is taken as an example of a top gate thin film transistor to be schematically illustrated, and in other possible implementation manners, the thin film transistor may also be a bottom gate thin film transistor, which is not limited in the embodiment of the present application.
The orthographic projection of the active layer 3033 in the thin film transistor on the substrate 001 is located within the orthographic projection of the light shielding metal layer 302 on the substrate 001. Therefore, the active layer 3033 can be shielded by the shielding metal layer 302, so that light is prevented from irradiating the active layer 3033, the phenomenon that the voltage threshold of the active layer 303c is shifted under the irradiation of the light is effectively avoided, and the electrical property of the thin film transistor is improved.
In an embodiment of the present application, the display panel 000 may include: a substrate 001, and a first conductive pattern 002, a first insulating layer 003, an active layer pattern 004, a second insulating layer 005, a second conductive pattern 006, a third insulating layer 007, a third conductive pattern 008, a fourth insulating layer 009, a fourth conductive pattern 010, a fifth insulating layer 011, a fifth conductive pattern 012, a flat layer 013, an anode pattern 014, a pixel defining layer 015, a light emitting layer 3012, a cathode layer 3013, and an encapsulation layer 016 which are stacked on the substrate 001.
Wherein the first conductive pattern 002 may include: a light shielding metal layer 302 in the sub-pixel 300.
The active layer pattern 004 may include: an active layer 3033 in a thin film transistor.
The second conductive pattern 006 may include: a gate electrode 3032 in a thin film transistor and a first capacitor electrode 3034 in a storage capacitor. In the present application, the second conductive pattern 006 may further include: at least one of a plurality of lateral signal lines, each of which needs to be electrically connected to the pixel driving circuit 303. For example, the second conductive pattern 006 may further include: a gate line, a reset control line, and an enable signal line.
The third conductive pattern 008 may include: a second capacitance electrode 3035 in the storage capacitance. In the present application, the third conductive pattern 008 may further include: at least one of the plurality of lateral signal lines, for example, the third conductive pattern 008 may further include: an initial signal line.
The fourth conductive pattern 010 may include: source and drain electrodes 3031 in the thin film transistor. In the present application, the fourth conductive pattern 010 may further include: at least one of a plurality of longitudinal signal lines, each of which needs to be electrically connected to the pixel driving circuit 303. For example, the fourth conductive pattern 010 may further include: and a power signal line. The power signal line is typically a VDD power signal line.
The fifth conductive pattern 011 may include: and a transfer electrode 3036 in the pixel driving circuit 303. In the present application, the fourth conductive pattern 010 may further include: at least one of the plurality of longitudinal signal lines, for example, the fifth conductive pattern 011 may further include: a data signal line 100.
The anode pattern 014 may include: anode layer 3011 in each light emitting device 301.
The pixel defining layer 015 has a plurality of pixel regions, and one light emitting device 301 may be arranged in each pixel region.
The encapsulation layer 016 is used for encapsulating the light-emitting device 301, so as to prevent water and oxygen from entering the light-emitting device and causing oxidation of the light-emitting device, and the service life of the light-emitting device 301 can be effectively prolonged through the encapsulation layer 016.
It should be noted that, the display panels provided by the embodiments of the present application are all aimed at display products with high refresh rates. Of course, the display panel may also be directed to a display product of a bottom refresh rate, so that only the fifth conductive pattern 011 needs to be eliminated and the data signal line 100 is arranged in the fourth conductive layer 010. The embodiment of the present application is not limited thereto.
As can be seen from the above, the sub-pixel 300 in the embodiment of the application has a plurality of different electrodes, and these electrodes can be used as the conductive structures 300a disposed on the same layer as the fan-out lead 200. For this purpose, the embodiments of the present application will be schematically illustrated by taking the following three alternative implementation manners as examples:
in a first alternative implementation, as shown in fig. 7, fig. 7 is a schematic film structure of another display panel according to an embodiment of the present application. The conductive structure 300a in the sub-pixel 300 is the anode layer 3011 in the light emitting device 301. As such, the anode layer 3011 in the light emitting device 301 may be provided in the same layer and of the same material as the fan-out lead 200. That is, the fanout lead 200 is located within the anode pattern 014 to which the anode layer 3011 belongs, and the anode layer 3011 and the fanout lead 200 are formed by the same patterning process.
In a second alternative implementation manner, as shown in fig. 8, fig. 8 is a schematic film structure of another display panel according to an embodiment of the present application. The conductive structure 300a in the sub-pixel 300 is a light shielding metal layer 302, and the light shielding metal layer 302 and the fan-out lead 200 are arranged on the same layer and made of the same material. That is, the fan-out lead 200 is located in the first conductive pattern 002 to which the light shielding metal layer 302 belongs, and the light shielding metal layer 302 and the fan-out lead 200 are formed by the same patterning process.
In the embodiment of the present application, the extension structures of the fan-out lead 200 in the first and second alternative implementations may be the same. As illustrated in fig. 9, fig. 9 is a top view of the display panel illustrated in fig. 7 or 8. The fan-out lead 200 may include: a first sub-line segment 201 connected to an end of the data signal line 100, and a second sub-line segment 202 connected to the connection lead 400, the first sub-line segment 201 being electrically connected to the second sub-line segment 202, and an extending direction of the first sub-line segment 201 intersecting an extending direction of the second sub-line segment 202. In the present application, the first sub-line 201 and the second sub-line 202 in the fan-out lead 201 may be disposed in the same layer and made of the same material. That is, the first sub-line 201 and the second sub-line 202 are formed by a communication process. When the fan-out lead 201 is disposed in the same layer as the anode layer 3011 or the fan-out lead 201 is disposed in the same layer as the light shielding layer 302, an insulating layer may be present between the conductive pattern where the fan-out lead 201 is located and the conductive pattern where the data signal line 200 is located. For example, when the fan-out lead 201 is disposed in the same layer as the anode layer 3011, a flat layer 013 exists between the anode pattern 014 where the fan-out lead 201 is located and the fifth conductive pattern 012 where the data signal line 200 is located. In this case, the flat layer 013 has connection vias therein, through which the first sub-lines 201 in the fan-out lead 201 can overlap with the ends of the data signal lines 200.
It should be noted that, there are various possible configurations of the first sub-segment 201 and the second sub-segment 202 in the fan-out lead 200, and the following two cases are taken as examples for illustrative purposes in the embodiment of the present application.
In the first case, as shown in fig. 9, fig. 9 is a plan view of the display panel shown in fig. 7 or 8. One of the first and second sub-line segments 201 and 202 of the fan-out lead 200 extends in the same direction as the data signal line 100, and the other one of the first and second sub-line segments 201 and 202 extends in the same direction as the data signal line 100, and the included angle of the intersection is an acute angle. In the present application, the extending direction of the first sub-line segment 201 intersects with the extending direction of the data signal line 100, and the extending direction of the second sub-line segment 202 is the same as the extending direction of the data signal line 100.
The first sub-line segment 201 in the fan-out lead 200 is inclined, the second sub-line segment 202 is vertical, and the wiring effect that the fan-out lead 200 converges from two sides to the middle can be achieved through the first sub-line segment 201 which is arranged in an inclined mode and the second sub-line segment 202 which is arranged in a vertical mode.
In an embodiment of the present application, the plurality of subpixels 300 in the display panel 000 may include: red, green, and blue subpixels R, G, and B. The plurality of sub-pixels 300 may be arranged in different manners. For example, the plurality of sub-pixels 300 may be arranged in RGB, that is, one red sub-pixel R, one green sub-pixel G, and one blue sub-pixel B can constitute one pixel unit. For another example, the plurality of sub-pixels 300 may be arranged in RGGB, that is, one red sub-pixel R, two green sub-pixels G, and one blue sub-pixel B can constitute one pixel unit. For this reason, the distribution of the first sub-line segment 201 and the second sub-line segment 202 in different pixel arrangements will be described below.
When the plurality of sub-pixels 300 in the display panel 000 are arranged in RGB, as shown in fig. 10 and 11, fig. 10 is a schematic diagram of the distribution of the first sub-line segments in the sub-pixels arranged in RGB according to the embodiment of the application, and fig. 11 is a schematic diagram of the distribution of the second sub-line segments in the sub-pixels arranged in RGB according to the embodiment of the application. The first sub-line segment 201 of the fan-out lead 200 is arranged between two inclined rows of sub-pixels in an inclined manner, and the second sub-line segment 202 of the fan-out lead 200 is arranged vertically between two columns of sub-pixels.
It should be noted that, in the embodiment of the present application, the extending direction of the first sub-line segment 201 refers to: the overall extending direction of the first sub-line segment 201 in the length direction is an overall oblique extending direction so as to intersect with the extending direction of the data signal line 100, and the included angle is an acute angle. Of course, the extending direction of the second sub-line segment 202 refers to: the overall extending direction of the second sub-line segment 202 in the length direction is a numerical extending direction as a whole, so as to be the same as the extending direction of the data signal line 100.
When the plurality of sub-pixels 300 in the display panel 000 are arranged in RGGB, as shown in fig. 12 and 13, fig. 12 is a schematic diagram of the distribution of the first sub-line segments in the sub-pixels arranged in RGGB according to the embodiment of the present application, and fig. 13 is a schematic diagram of the distribution of the second sub-line segments in the sub-pixels arranged in RGGB according to the embodiment of the present application. The first sub-line 201 of the fan-out lead 200 is arranged between two inclined rows of sub-pixels in an inclined manner, and the second sub-line of the fan-out lead is arranged between two columns of sub-pixels vertically. It should be noted that, when the first sub-line segment 201 is arranged obliquely and the second sub-line segment 202 is arranged vertically, the overall extension of the first sub-line segment 201 and the second sub-line segment 202 in the length direction is not different, that is, when the plurality of sub-pixels 300 are arranged in RGGB, the first sub-line segment 201 is arranged obliquely so as to intersect with the extending direction of the data signal line 100, and the included angle is also an acute angle; the second sub-line segment 202 has a numerical extending direction as a whole, so as to be the same as the extending direction of the data signal line 100. The present application is not described in detail herein.
In the second case, as shown in fig. 14, fig. 14 is another plan view of the display panel shown in fig. 7 or 8, as shown in fig. 14. The extending direction of the first sub-line segment 201 and the extending direction of the second sub-line segment 202 are both intersected with the extending direction of the data signal line 100. The first sub-line segment 201 and the second sub-line segment 202 in the fan-out lead 200 are both inclined, and an included angle between an extending direction of the first sub-line segment 201 and an extending direction of the second sub-line segment 202 is an acute angle. In this way, the first and second sub-line segments 201 and 202 are disposed obliquely, so that the fan-out lead 200 can be routed from both sides to the middle.
In the embodiment of the present application, when the plurality of sub-pixels 300 in the display panel 000 are arranged in RGB and RGGB, as shown in fig. 15 and 16, fig. 15 is a schematic diagram of the distribution of another first sub-line segment and second sub-line segment in the sub-pixels arranged in RGB provided in the embodiment of the present application, and fig. 16 is a schematic diagram of the distribution of another first sub-line segment and second sub-line segment in the sub-pixels arranged in RGGB provided in the embodiment of the present application. In the embodiment of the present application, the overall extending direction of the first sub-line segment 201 and the first sub-line segment 202 in the length direction, the first sub-line segment 201 and the first sub-line segment 202 intersect with the extending direction of the data signal line 100, and the included angle between the first sub-line segment 201 and the second sub-line segment 202 is an acute angle.
The first sub-line segment 201 and the second sub-line 202 in the fan-out lead 200 are all arranged in an inclined manner, and the first sub-line segment 201 and the second sub-line 202 are electrically connected, so that the first sub-line segment 201 and the second sub-line 202 are arranged between two inclined rows of sub-pixels in an inclined manner.
Alternatively, referring to fig. 17, fig. 17 is a further plan view of the display panel shown in fig. 7 or 8. The display panel further includes: a plurality of dummy electrodes 500 located within the display area 00a. The dummy electrode 500 and the plurality of fan-out leads 200 are uniformly distributed in the display area 00a, and the fan-out leads 200 are disposed in the same layer and the same material as the dummy electrode 500. Since the fan-out lead 200 is located in the display area 00a, there is a reflection difference between the area of the display panel 000 where the fan-out lead 200 is located and the area where the fan-out lead 200 is not located. A plurality of dummy electrodes 500 are disposed in the region of the display area 00a where the fan-out lead 200 is not disposed to compensate for such reflection differences. The plurality of dummy electrodes 500 in the display area 00a are uniformly arranged, and the plurality of dummy electrodes 500 are periodically arranged. Meanwhile, the dummy electrode 500 may be electrically connected to a power signal line (e.g., VDD power signal line or VSS power signal line) in the display panel, and a fixed voltage is applied to the dummy electrode 500 through the power signal line, so that the dummy electrode 500 is prevented from interfering with the normal operation display area 00a of the sub-pixel 300 in the display panel 000. The shape of the dummy electrode 500 is identical to the pattern of the fan-out lead 200.
Referring to fig. 18 and 19, fig. 18 is a top view of another display panel according to an embodiment of the present application, and fig. 19 is a schematic view of a film structure of the display panel at C-C' shown in fig. 18. The fan-out lead 200 may include a third sub-segment 203 and a fourth sub-segment 204 disposed in a different layer and electrically connected to each other. The conductive structure 300a in the sub-pixel 300 is a first electrode and a second electrode, and the first electrode and the third sub-line segment 203 in the pixel driving circuit 303 are arranged in the same layer and are made of the same material; the second electrode and the fourth sub-line segment 204 in the pixel driving circuit 303 are arranged in the same layer and are the same material. That is, the third sub-line segment 203 in the fan-out lead 200 is located in the first electrode of the pixel driving circuit 303, and the third sub-line segment 203 and the first electrode of the pixel driving circuit 303 are formed by a patterning process; the fourth sub-line segment 204 in the fan-out lead 200 is located in the second electrode of the pixel driving circuit 303, and the fourth sub-line segment 204 and the second electrode of the pixel driving circuit 303 are formed by a patterning process.
In the embodiment of the present application, the first electrode in the pixel driving circuit 303 is the source/drain electrode 3031 of the thin film transistor in the pixel driving circuit 303, or the first electrode is the transit electrode 3036 electrically connected to the source/drain electrode 3031 in the pixel driving circuit. The second electrode in the pixel driving circuit 303 is one of two electrodes in the storage capacitance in the pixel driving circuit, that is, one of the first capacitance electrode 3034 and the second capacitance electrode 3035 in the storage capacitance.
Note that, when the third sub-line segment 203 in the fan-out lead 200 is disposed in the same layer as the source/drain electrode 3031 of the thin film transistor in the pixel driving circuit 303, the third sub-line segment 203 in the fan-out lead 200 is located in the fourth conductive layer pattern 010 to which the source/drain electrode 3031 belongs. When the third sub-segment 203 in the fan-out lead 200 is disposed at the same layer as the switching electrode 3036 in the pixel driving circuit, the third sub-segment 203 in the fan-out lead 200 is located in the fifth conductive layer pattern 012 to which the switching electrode 3036 belongs.
When the fourth sub-segment 204 in the fan-out lead 200 is disposed in the same layer as the first capacitor electrode 3034 of the storage capacitor in the pixel driving circuit 303, the fourth sub-segment 204 in the fan-out lead 200 is located in the second conductive layer 006 to which the first capacitor electrode 3034 belongs. When the fourth sub-segment 204 in the fan-out lead 200 is disposed on the same layer as the second capacitor electrode 3035 of the storage capacitor in the pixel driving circuit 303, the fourth sub-segment 204 in the fan-out lead 200 is located in the third conductive pattern 008 to which the second capacitor electrode 3035 belongs.
It should be noted that, in the embodiments of the present application, the third sub-line segment 203 in the fan-out lead 200 is located in the fifth conductive layer pattern 012, and the fourth sub-line segment 204 in the fan-out lead 200 is located in the third conductive layer pattern 008.
In the embodiment of the present application, the number of the third sub-segments 203 in the fan-out lead 200 is two, and the number of the fourth sub-segments 204 is one, wherein the first end of one third sub-segment 203 in the fan-out lead 200 is electrically connected to the end of the data signal line 100, and the first end of the other third sub-segment 203 in the fan-out lead 200 is electrically connected to the connection lead 400. Thus, two ends of the fourth sub-segment 204 in the fan-out lead 200 are electrically connected to the second ends of the two third sub-segments 203, respectively.
Alternatively, referring to fig. 20, fig. 20 is a partially enlarged view at D shown in fig. 18. The extending direction of the third sub-line segment 203 in the fan-out lead 200 is parallel to the extending direction of the data signal line 100, and the third sub-line segment 203 and the data signal line 100 are arranged on the same layer, and the materials are the same, that is, the third sub-line segment 203 and the data signal line 100 are realized through a one-time patterning process. The fan-out lead 200 further includes: a transition sub-segment 203a for connecting an end of the data signal line 100 and a first end of the third sub-segment. For example, when the first end of the first third sub-segment 203 in the fan-out lead 200 is electrically connected to the data signal line 100, a small "U" shape structure is formed between the first third sub-segment 203 and the data signal line 100. Because the driving signal drives the data signal line 100 through the third sub-line segment 203 and the third sub-line segment 204 in the fan-out lead 200, the small "U" structure can ensure that the driving signal is transmitted from the near end of the display panel (i.e., the end of the display panel near the driving chip) to the far end (i.e., the end of the display panel far away from the driving chip), so that the uniformity of the driving signal reaching the far end is better by adjusting the length of the connecting lead 400.
In an embodiment of the present application, please refer to fig. 21, fig. 21 is a top view of a sub-pixel in the display panel shown in fig. 18. The display panel 000 may further include: the signal transmission line 600 is located in the display area 00a and electrically connected to the sub-pixel 300, the extending direction of the signal transmission line 600 is parallel to the extending direction of the fourth sub-line segment 204 in the fan-out lead 200, the signal transmission signal line 305 and the fourth sub-line segment 204 in the fan-out lead 200 are arranged in the same layer, and the materials are the same, that is, the signal transmission signal line 305 and the fourth sub-line segment 204 in the fan-out lead 200 are arranged in the same layer through a single patterning process. The signal transmission line 600 may be: a gate line, a reset control line, an enable signal line, and an initial signal line. When the fourth sub-segment 204 of the fan-out lead 200 is located within the third conductive pattern 008, the signal transmission line 600 may be an initial signal line.
In this case, a first end of one third sub-segment 203 of the fan-out lead 200 may be electrically connected with an end of the data signal line 100 through the transfer sub-segment 203 a; a first end of another third sub-segment 203 in the fan-out lead 200 may be electrically connected with the connection lead 400; the second ends of the two third sub-line segments 203 and the two ends of the fourth sub-line segment 204 may be overlapped by a via hole provided on an insulating layer between the third conductive pattern 008 and the fifth conductive pattern 012.
It should be noted that, when the extending direction of the third sub-line segment 203 in the fan-out lead 200 is parallel to the extending direction of the data signal line 100, the third sub-line segment 203 needs to be arranged between the two columns of sub-pixels 300, and thus, the size of the sub-pixels 300 needs to be compressed in the row direction of the sub-pixels 300 to increase the distance between the two columns of sub-pixels 300, so as to ensure that the data signal line 100 and the third sub-line segment 203 can be arranged between the two columns of sub-pixels 300 at the same time. Similarly, when the extending direction of the fourth sub-line segment 204 in the fan-out lead 200 is parallel to the extending direction of the signal transmission line 600, the fourth sub-line segment 204 needs to be arranged between the two rows of sub-pixels 300, and thus, the size of the sub-pixels 300 needs to be compressed in the row direction of the sub-pixels 300 to increase the distance between the two rows of sub-pixels 300, so as to ensure that the signal transmission line 600 and the fourth sub-line segment 204 can be arranged between the two rows of sub-pixels 300 at the same time.
In the above three alternative implementations, a portion of the data signal lines 100 in the display panel 000 may be electrically connected to the connection leads 400 through the fan-out lead 200, and another portion of the data signal lines 100 may be directly electrically connected to the connection leads 400. For example, referring to fig. 22, fig. 22 is a schematic diagram illustrating a relationship between fan-out leads and data signal lines and connection leads according to an embodiment of the present application. The plurality of data signal lines 100 in the display panel 000 may include: at least two first data signal lines 100a and at least two second data signal lines 100b. The plurality of connection leads 400 in the display panel 000 may include: at least two first connection leads 400a and at least two second connection leads 400b. In an embodiment of the present application, a portion of the plurality of data signal lines 100 (i.e., the first data signal line 100 a) may be electrically connected to a portion of the plurality of connection leads 400 (i.e., the first connection lead 400 a) through the fan-out lead 200; another part of the data signal lines 100 (i.e., the second data signal line 100 b) may be directly electrically connected to another part of the connection leads 400 (i.e., the second connection lead 400 b).
The at least two first data signal lines 100a are in one-to-one correspondence with the plurality of fan-out lead lines 200 and in one-to-one correspondence with the at least two first connection lead lines 400a, and each first data signal line 100a may be electrically connected with the corresponding fan-out lead line 200 and the corresponding first connection lead line 400a in sequence. At least two second data signal lines 100b are in one-to-one correspondence with at least two second connection leads 400b, and each second data signal line 100b may be electrically connected with a corresponding second connection lead 400 b.
In the embodiment of the present application, since the lengths of the data signal lines 100 in the display area 00a are the same, and the second connection lead 400b is directly electrically connected to the second data signal line 100b, the first connection lead 400a needs to be electrically connected to the first data signal line 100a through the fan-out lead 200. Therefore, the lengths of the at least two second connection leads 400b may be the same and both are greater than the length of the first connection lead 400a, and thus it is possible to ensure that the difference between the voltage of the signal transmitted through the first connection lead 400a when transmitted to the first data signal line 100a and the voltage of the signal transmitted through the second connection lead 400b when transmitted to the second data signal line 100b is small.
Illustratively, the length of each first connecting lead 400a is inversely related to the length of the corresponding fan-out lead 200. For example, when the length of the fan-out lead 200 is longer, the length of the corresponding first connection lead 400a is shorter. In one possible case, the length of each first connection lead 400a is the same as the sum of the lengths of the corresponding fan-out leads 200, and is equal to the length of the second connection lead 400 b. In this way, it is possible to ensure that the voltage of the signal transmitted through the first connection lead 400a when transmitted to the first data signal line 100a is approximately the same as the voltage of the signal transmitted through the second connection lead 400b when transmitted to the second data signal line 100 b.
Alternatively, the first connection lead 400a and the second connection lead 400b having the longer length of the at least two first connection leads 400a may each include a portion having an S-shaped trace. Thus, the width of the non-display region 00b can be further reduced, and the screen ratio of the display device including the display panel 000 can be further increased.
The first connection lead 400a and the second connection lead 400b in the above embodiment are divided according to the signal lines to which the connection leads 400 are connected. Of course, the plurality of connection leads 400 in the display panel may be divided into two groups according to the conductive patterns. By way of example, the plurality of connection leads 400 in the display panel 000 may include: a first set of connection leads and a second set of connection leads. Wherein, at least two connecting leads 400 in the first connecting lead group are arranged in the same layer and are made of the same material; at least two connection leads 400 of the second connection lead group are arranged in the same layer and are the same material. At least two connecting leads 400 in the first connecting lead set are arranged in different layers from at least two connecting leads 400 in the second connecting lead set. For example, at least two connection leads 400 in the first connection lead group may belong to the second conductive pattern 006, and at least two connection leads 400 in the second connection lead group may belong to the third conductive pattern 008. And, at least two connection leads 400 in the first connection lead group are staggered with at least two connection leads 400 in the second connection lead group.
In summary, the display panel provided in the embodiment of the application includes: the sub-pixels, the data signal lines and the fan-out leads are located in the display area, and the connection leads are located in the non-display area. Since the fan-out lead may be located within the display area, it does not occupy space in the non-display area. Therefore, the width of the non-display area in the display panel is smaller, the screen occupation ratio of the display device comprising the display panel is effectively improved, and the display effect of the display device is effectively improved. And because the fan-out lead wires positioned in the display area and the conductive structures in the sub-pixels are arranged in the same layer, the fan-out lead wires can be arranged in the display area without arranging additional conductive patterns in the display panel, thereby effectively simplifying the manufacturing difficulty of the display panel and reducing the manufacturing cost of the display panel.
The embodiment of the application also provides a display device. The display device may be: any product or component with display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. The display device may include: a power supply assembly (not shown) and a display panel 000, wherein the display panel may be the display panel in the above-described embodiments, for example, it may be the display panel shown in fig. 4, 7, 8 or 18. The power supply assembly is connected to the display panel 000 for supplying power to the display panel 000 to enable the display panel 000 to display images.
It is noted that in the drawings, the size of layers and regions may be exaggerated for clarity of illustration. Moreover, it will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or intervening layers may be present. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or intervening layers or elements may be present. In addition, it will be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer between the two layers or elements, or more than one intervening layer or element may also be present. Like reference numerals refer to like elements throughout.
In the present disclosure, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The term "plurality" refers to two or more, unless explicitly defined otherwise.
The foregoing description of the preferred embodiments of the present application is not intended to limit the application, but is intended to cover all modifications, equivalents, alternatives, and improvements falling within the spirit and principles of the application.
Claims (12)
1. A display panel having a display area and a non-display area located at a periphery of the display area, the display panel comprising:
a plurality of array-arranged sub-pixels, a plurality of data signal lines and a plurality of fan-out leads, wherein the array-arranged sub-pixels, the data signal lines and the fan-out leads are positioned in the display area, one data signal line is electrically connected with one row of the sub-pixels, and the end part of one data signal line is electrically connected with the first end of one fan-out lead;
and a plurality of connection leads located in the non-display area, one of the connection leads being electrically connected to a second end of one of the fan-out leads, the plurality of connection leads being for electrically connecting to a driving chip;
the sub-pixels are provided with conductive structures, and the fan-out leads and the conductive structures are arranged on the same layer and are made of the same material;
the display panel further includes: the pixel defining layer is provided with a plurality of pixel areas, each pixel area is internally provided with a light emitting device, and the packaging layer is used for packaging the light emitting device;
the sub-pixel includes: the positive pole layer in the light emitting device with fan-out lead wire homolayer sets up, and the material is the same, wherein, the light emitting device includes: an anode layer, a light-emitting layer, and a cathode layer which are stacked;
The display panel further includes: the plurality of virtual electrodes and the plurality of fan-out leads are uniformly distributed in the display area;
the virtual electrodes and the fan-out lead wires are arranged on the same layer, the materials are the same, the virtual electrodes are arranged periodically, and the shape of each virtual electrode is consistent with the pattern of the fan-out lead wires.
2. The display panel of claim 1, wherein the sub-pixel comprises: and the shading metal layer and the fan-out lead are arranged on the same layer and are made of the same material.
3. The display panel of claim 2, wherein the fan-out lead comprises: a first sub-line segment connected with the end of the data signal line, and a second sub-line segment connected with the connecting lead, wherein the first sub-line segment is electrically connected with the second sub-line segment, and the extending direction of the first sub-line segment is intersected with the extending direction of the second sub-line segment;
wherein an extending direction of one of the first sub-line segment and the second sub-line segment is the same as an extending direction of the data signal line;
or, the extending direction of the first sub-line segment and the extending direction of the second sub-line segment are intersected with the extending direction of the data signal line.
4. The display panel of claim 1, wherein the fan-out lead comprises: a third sub-line segment and a fourth sub-line segment which are arranged in different layers and are electrically connected with each other;
the sub-pixel includes: and the first electrode in the pixel driving circuit and the third sub-line segment are arranged in the same layer, and the materials are the same, and the second electrode in the pixel driving circuit and the fourth sub-line segment are arranged in the same layer, and the materials are the same.
5. The display panel of claim 4, wherein the number of third sub-segments in the fan-out lead is two and the number of fourth sub-segments is one;
wherein, the first end of one of the third sub-line segments in the fan-out lead is electrically connected with the end part of the data signal line, and the first end of the other third sub-line segment is electrically connected with the connecting lead; and two ends of the fourth sub-line segment are respectively and electrically connected with the second ends of the two third sub-line segments.
6. The display panel according to claim 5, wherein an extending direction of the third sub-line segment is parallel to an extending direction of the data signal line, and the third sub-line segment is disposed in the same layer as the data signal line and is made of the same material;
The fan-out lead further includes: and a switching sub-line segment for connecting an end of the data signal line and the first end of the third sub-line segment.
7. The display panel of claim 6, further comprising: the signal transmission lines are positioned in the display area and electrically connected with one row of the sub-pixels, the extending direction of the signal transmission lines is parallel to the extending direction of the fourth sub-line segment, and the signal transmission lines and the fourth sub-line segment are arranged on the same layer and are made of the same material.
8. The display panel according to any one of claims 4 to 7, wherein the first electrode is a source/drain electrode of a thin film transistor in the pixel driving circuit, or the first electrode is a transfer electrode electrically connected to the source/drain electrode in the pixel driving circuit;
the second electrode is one of two electrodes of a storage capacitor in the pixel driving circuit.
9. The display panel according to any one of claims 1 or 2, 4 to 7, wherein the plurality of data signal lines include: at least two first data signal lines and at least two second data signal lines;
the plurality of connection leads includes: at least two first connecting leads and at least two second connecting leads;
The at least two first data signal lines are in one-to-one correspondence with the fan-out leads and in one-to-one correspondence with the at least two first connecting leads, and the first data signal lines are electrically connected with the corresponding fan-out leads and the corresponding first connecting leads in sequence;
the at least two second data signal lines are in one-to-one correspondence with the at least two second connection leads, and the second data signal lines are electrically connected with the corresponding second connection leads.
10. The display panel of claim 9, wherein the second connection leads each have a same length and are each longer than the first connection lead.
11. The display panel of claim 10, wherein a length of each of the first connection leads is inversely related to a length of the corresponding fan-out lead.
12. A display device, comprising: a power supply assembly as claimed in any one of claims 1 to 11; the power supply assembly is connected with the display panel and is used for supplying power to the display panel.
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| CN114708797B (en) * | 2022-03-31 | 2024-02-27 | 武汉华星光电技术有限公司 | Display panel and display device |
| WO2023201536A1 (en) * | 2022-04-19 | 2023-10-26 | 京东方科技集团股份有限公司 | Display substrate and manufacturing method therefor, and display device |
| CN114843283A (en) * | 2022-04-19 | 2022-08-02 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
| WO2023201554A1 (en) * | 2022-04-20 | 2023-10-26 | 京东方科技集团股份有限公司 | Display panel and display apparatus |
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