CN110931515B - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
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- CN110931515B CN110931515B CN201911240515.8A CN201911240515A CN110931515B CN 110931515 B CN110931515 B CN 110931515B CN 201911240515 A CN201911240515 A CN 201911240515A CN 110931515 B CN110931515 B CN 110931515B
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- 239000000758 substrate Substances 0.000 title claims abstract description 110
- 239000002184 metal Substances 0.000 claims abstract description 96
- 239000010410 layer Substances 0.000 claims description 148
- 239000000463 material Substances 0.000 claims description 12
- 239000012044 organic layer Substances 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000010409 thin film Substances 0.000 description 5
- 239000010408 film Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
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- 239000003990 capacitor Substances 0.000 description 3
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- 239000002346 layers by function Substances 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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Abstract
The invention provides an array substrate, a display panel and a display device, wherein the array substrate comprises a display area and a step area; a substrate; a plurality of data lines located in the display area; the data lines extend along a second direction and are arranged along a first direction; the fan-out wires are positioned in the step areas and electrically connected with the data lines and used for providing data signals for the data lines; the plurality of fan-out wires comprise a first fan-out wire positioned on the first metal layer, a second fan-out wire positioned on the second metal layer and a third fan-out wire positioned on the third metal layer; in a direction perpendicular to the substrate, the second metal layer is located on one side of the first metal layer, which is far away from the substrate, the third metal layer is located on one side of the second metal layer, which is far away from the first metal layer, and the vertical projections of the first fan-out routing and the second fan-out routing on the substrate are not overlapped. The invention reduces the frame and increases the screen occupation ratio.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a display panel and a display device.
Background
With the development of scientific technology and the progress of society, people increasingly depend on the aspects of information communication and transmission, and display devices as main carriers and material bases for information exchange and transmission become hot spots of research of many scientists.
At present, a display panel and a display device having a high screen ratio and a narrow bezel are becoming a trend. However, the step area needs to be provided with a plurality of fan-out traces, so that the width of the step area cannot be reduced.
Disclosure of Invention
The invention provides an array substrate, a display panel and a display device, which are used for reducing a frame and increasing the screen occupation ratio.
In a first aspect, an embodiment of the present invention provides an array substrate, including a display area and a step area;
a substrate;
a plurality of data lines located in the display area; the data lines extend along a second direction and are arranged along a first direction;
the fan-out wires are positioned in the step areas, electrically connected with the data lines and used for providing data signals for the data lines; the plurality of fan-out wires comprise a first fan-out wire positioned on the first metal layer, a second fan-out wire positioned on the second metal layer and a third fan-out wire positioned on the third metal layer; in a direction perpendicular to the substrate, the second metal layer is located on one side of the first metal layer, which is far away from the substrate, the third metal layer is located on one side of the second metal layer, which is far away from the first metal layer, and the vertical projections of the first fan-out routing and the second fan-out routing on the substrate are not overlapped.
In a second aspect, an embodiment of the present invention provides a display panel, including the array substrate of the first aspect.
In a third aspect, an embodiment of the present invention provides a display device, including the display panel of the second aspect.
In the array substrate provided by the embodiment of the invention, the plurality of fan-out wires are respectively arranged on the first metal layer, the second metal layer and the third metal layer, and compared with the case that the plurality of fan-out wires are arranged on one metal layer or two metal layers, the distance between two adjacent fan-out wires can be reduced, so that the occupied area of the fan-out wires in a step area is reduced, the width of the step area is reduced, the frame is reduced, and the screen occupation ratio is increased. In addition, the first fan-out routing and the second fan-out routing are not overlapped, and overlapping capacitance generated by the first fan-out routing and the second fan-out routing can be prevented on the basis of reducing the frame, so that the increase of loads of the first fan-out routing and the second fan-out routing is prevented.
Drawings
Fig. 1 is a schematic top view of an array substrate according to an embodiment of the present invention;
FIG. 2 is an enlarged schematic view of the region S1 in FIG. 1;
FIG. 3 is a schematic cross-sectional view along the direction AA' in FIG. 2;
FIG. 4 is a schematic cross-sectional view taken along the direction BB' in FIG. 1;
fig. 5 is a schematic cross-sectional view illustrating another array substrate according to an embodiment of the invention;
fig. 6 is a schematic top view illustrating an array substrate according to another embodiment of the present invention;
fig. 7 is a schematic top view illustrating an array substrate according to another embodiment of the present invention;
fig. 8 is a schematic top view illustrating a fan-out trace in an array substrate according to an embodiment of the present invention;
fig. 9 is a schematic top view illustrating a fan-out trace in an array substrate according to another embodiment of the present invention;
fig. 10 is a schematic cross-sectional view illustrating another array substrate according to an embodiment of the invention;
fig. 11 is a schematic cross-sectional view illustrating another array substrate according to an embodiment of the invention;
fig. 12 is a schematic top view illustrating an array substrate according to another embodiment of the present invention;
fig. 13 is a schematic top view illustrating an array substrate according to another embodiment of the present invention;
fig. 14 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 15 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Fig. 1 is a schematic top view of an array substrate according to an embodiment of the present invention, fig. 2 is an enlarged structural view of a region S1 in fig. 1, fig. 3 is a schematic cross-sectional view along a direction AA 'in fig. 2, fig. 4 is a schematic cross-sectional view along a direction BB' in fig. 1, and referring to fig. 1, fig. 2, fig. 3, and fig. 4, the array substrate includes a display region a1 and a step region a 2. The array substrate includes a substrate 10, a plurality of data lines 22, and a plurality of fan-out traces 30. The plurality of data lines 22 are positioned in the display area a1, and the plurality of data lines 22 extend along the second direction and are arranged along the first direction. The plurality of fan-out traces 30 are located at the step area a2, and the fan-out traces 30 are electrically connected to the data lines 22 for providing data signals to the data lines 22. The plurality of fan-out traces 30 includes a first fan-out trace 31 on the first metal layer M1, a second fan-out trace 32 on the second metal layer M2, and a third fan-out trace 33 on the third metal layer M3. In the direction perpendicular to the substrate 10, the second metal layer M2 is located on the side of the first metal layer M1 away from the substrate 10, the third metal layer M3 is located on the side of the second metal layer M2 away from the first metal layer M1, and the vertical projections of the first fan-out trace 31 and the second fan-out trace 32 on the substrate 10 do not overlap.
It should be noted that, an actual array substrate includes a large number of data lines 22 and a large number of fan-out traces 30, and the number of the data lines 22 and the number of the fan-out traces 30 shown in fig. 1 is only an illustration and is not a limitation to the embodiment of the present invention.
In the array substrate provided by the embodiment of the invention, the plurality of fan-out wires are respectively arranged on the first metal layer, the second metal layer and the third metal layer, and compared with the case that the plurality of fan-out wires are arranged on one metal layer or two metal layers, the distance between two adjacent fan-out wires can be reduced, so that the occupied area of the fan-out wires in a step area is reduced, the width of the step area is reduced, the frame is reduced, and the screen occupation ratio is increased. In addition, the first fan-out routing and the second fan-out routing are not overlapped, and the first fan-out routing and the second fan-out routing can be prevented from generating overlapping capacitance on the basis of reducing the frame, so that the increase of loads of the first fan-out routing and the second fan-out routing is prevented.
Optionally, referring to fig. 1, 3 and 4, the array substrate further includes a plurality of scan lines 21, the plurality of scan lines 21 are located in the display area a1, and the plurality of scan lines 21 extend along the first direction and are arranged along the second direction. The scan line 21 is located in the first metal layer M1, and the second metal layer M2 is located between the first metal layer M1 and the data line 22. In the embodiment of the present invention, the first fan-out trace 31 and the scan line 21 are on the same layer, the second fan-out trace 32 is located between the film layers where the first fan-out trace 31 and the data line 22 are located, and the distance between the first fan-out trace 31 and the second fan-out trace 32 is relatively short, so that it is especially necessary to set the first fan-out trace 31 and the second fan-out trace 32 not to overlap, so as to prevent the first fan-out trace 31 and the second fan-out trace 32 from generating overlapping capacitance.
Alternatively, referring to fig. 3 and 4, the first metal layer M1 and the second metal layer M2 are made of the same material. The same material is used for the first fan-out trace 31 located on the first metal layer M1 and the second fan-out trace 32 located on the second metal layer M2, and the first fan-out trace 31 and the second fan-out trace 32 have the same resistivity, so that the difference between the voltage drops on the first fan-out trace 31 and the second fan-out trace 32 is reduced, and the attenuation of the data signals transmitted on the first fan-out trace 31 and the second fan-out trace 32 is the same or similar, so as to ensure the uniformity of the display.
Alternatively, referring to fig. 2 and 3, the line width of the first fan-out trace 31 is equal to the line width of the second fan-out trace 32. The line width of the first fan-out trace 31 is the width of the first fan-out trace 31 in the direction perpendicular to the extending direction thereof, and the line width of the second fan-out trace 32 is the width of the second fan-out trace 32 in the direction perpendicular to the extending direction thereof. In the embodiment of the present invention, the first fan-out trace 31 and the second fan-out trace 32 are made of the same material, and the line width of the first fan-out trace 31 is equal to the line width of the second fan-out trace 32, so that the difference between the voltage drops on the first fan-out trace 31 and the second fan-out trace 32 is further reduced, and the data signals transmitted on the first fan-out trace 31 and the second fan-out trace 32 have the same or similar attenuation, so as to ensure the uniformity of the display.
Illustratively, referring to fig. 1, a plurality of scan lines 21 and a plurality of data lines 22 intersect to form a plurality of sub-pixels 110, and the plurality of sub-pixels 110 are arranged in an array in the display area a 1. One end of the fan-out trace 30 is electrically connected to the data line 22, the other end of the fan-out trace 30 is electrically connected to the driving chip 40, and the driving chip 40 is bound to the step area a2 of the array substrate. The driver chip 40 provides data signals to the data lines 22 through the fan-out traces 30.
Exemplarily, referring to fig. 1, 2, 3 and 4, the array substrate further includes a buffer layer 11, a gate insulating layer 12, a first dielectric layer 13, a second dielectric layer 14, a first organic layer 15, a planarization layer 16, and a pixel defining layer 17, which are sequentially stacked along a direction away from the substrate 10. The array substrate further includes a pixel driving circuit electrically connected to the light emitting unit 70, and a light emitting unit 70, the pixel driving circuit being configured to provide a driving voltage or a driving current to the light emitting unit 70. The pixel driving circuit includes a thin film transistor 50 and a storage capacitor 60, and the thin film transistor 50 includes a source electrode 51, a gate electrode 52, a semiconductor layer 53, and a drain electrode 54. The storage capacitor 60 includes a first plate 61 and a second plate 62. The light emitting unit 70 includes a first electrode 71, a light emitting function layer 72, and a second electrode 73. The light emitting functional layer 72 is located between the first electrode 71 and the second electrode 73, and the holes injected from the first electrode 71 and the electrons injected from the second electrode 73 combine in the light emitting functional layer 72 to form excitons, and the exciton transition generates photons to make the light emitting unit 70 emit light. The scan line 21, the gate 52 and the first plate 61 are located on the first metal layer M1, and the first metal layer M1 is located between the gate insulating layer 12 and the first dielectric layer 13. The second plate 62 is located on the second metal layer M2. The data line 22, the source electrode 51 and the drain electrode 54 are located at the same layer, and the data line 22 is located at the side of the second metal layer M2 away from the substrate 10. The data line 22 may be electrically connected to the first fan-out trace 31 through a via, and the data line 22 may be electrically connected to the second fan-out trace 32 through a via.
Alternatively, referring to fig. 4, the third metal layer M3 is located on the side of the film layer where the data line 22 is located, which is far from the substrate 10. Therefore, the third fan-out trace 33 is located on the film layer where the data line 22 is located and away from the substrate 10, and the third fan-out trace 33 is further away from the first fan-out trace 31 and the second fan-out trace 32, so that the adverse electrical effect of the third fan-out trace 33 on the first fan-out trace 31 and the second fan-out trace 32 is avoided.
Exemplarily, referring to fig. 4, the third fan-out trace 33 is located on a side of the film layer where the data line 22 is located, which is far away from the substrate 10, and the third fan-out trace 33 is electrically connected with the data line 22 through a via.
Optionally, referring to fig. 4, the array substrate further includes a first insulating layer 81 and a second insulating layer 82, the first insulating layer 81 is located between the first metal layer M1 and the second metal layer M2, the second insulating layer 82 is located between the third metal layer M3 and the data line 22, and the thickness of the second insulating layer 82 is greater than that of the first insulating layer 81. In the embodiment of the present invention, the thickness of the second insulating layer 82 is greater than that of the first insulating layer 81, and the second insulating layer 82 has a greater thickness, so that in a direction perpendicular to the plane of the substrate 10, the distance between the third fan-out trace 33 and the data line 22 is greater, and the distance between the third fan-out trace 33 and the first fan-out trace 31 and the second fan-out trace 32 is further greater, thereby further avoiding the adverse electrical effect of the third fan-out trace 33 on the first fan-out trace 31 and the second fan-out trace 32.
Exemplarily, referring to fig. 4, the first insulating layer 81 includes the first dielectric layer 13, and the first insulating layer 81 is an inorganic layer. The second insulating layer 82 includes a first organic layer 15. The thickness of the first organic layer 15 is greater than the thickness of the first dielectric layer 13. A first dielectric layer 13 is arranged between the first metal layer M1 and the second metal layer M2, and a second dielectric layer 14 and a first organic layer 15 are arranged between the second metal layer M2 and the third metal layer M3. In the direction perpendicular to the plane of the substrate 10, the third metal layer M3 is farther spaced from the first metal layer M1, and the third metal layer M3 is farther spaced from the second metal layer M2. Therefore, the third fan-out trace 33 is far away from the first fan-out trace 31 and the second fan-out trace 32.
Fig. 5 is a schematic cross-sectional structure view of another array substrate according to an embodiment of the invention, and referring to fig. 5, the second insulating layer 82 includes a planarization layer 16 and a pixel defining layer 17, and the planarization layer 16 is located between the pixel defining layer 17 and the third metal layer M3. In the embodiment of the present invention, the second insulating layer 82 includes the planarization layer 16 and the pixel defining layer 17, so as to further increase the thickness of the second insulating layer 82, increase the distance between the third fan-out trace 33 and the first fan-out trace 31, and increase the distance between the third fan-out trace 33 and the second fan-out trace 32, thereby further avoiding the adverse electrical effect of the third fan-out trace 33 on the first fan-out trace 31 and the second fan-out trace 32.
For example, referring to fig. 5, the third fan-out trace 33 and the second electrode 73 are in the same layer and made of the same material, and the third fan-out trace 33 and the second electrode 73 can be formed in the same process, thereby saving the process.
Fig. 6 is a schematic top view of another array substrate according to an embodiment of the present invention, and referring to fig. 6, a display area a1 includes a plurality of pixels 100 arranged in an array, where the pixel 100 includes a plurality of sub-pixels 110, and the plurality of sub-pixels 110 includes a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103. Along the second direction, the data line 22 electrically connected to the first sub-pixels 101 and the second sub-pixels 102 is a first data line 221, and the data line 22 electrically connected to the third sub-pixels 103 is a second data line 222. One first data line 221 is electrically connected to one first fan-out trace 31 or one second fan-out trace 32, and one second data line 222 is electrically connected to one third fan-out trace 33. In the embodiment of the present invention, a part of the first sub-pixels 101 is electrically connected to the first fan-out trace 31, another part of the first sub-pixels 101 is electrically connected to the second fan-out trace 32, similarly, a part of the second sub-pixels 102 is electrically connected to the first fan-out trace 31, another part of the second sub-pixels 102 is electrically connected to the second fan-out trace 32, the first fan-out trace 31 located on the first metal layer M1 and the second fan-out trace 32 located on the second metal layer M2 are made of the same material, the first fan-out trace 31 and the second fan-out trace 32 have the same resistivity, so that the difference between the voltage drops on the first fan-out trace 31 and the second fan-out trace 32 is reduced, so that the data signals transmitted on the first fan-out trace 31 and the second fan-out trace 32 have the same or similar attenuation, and the first sub-pixels 101 receiving the data signals transmitted by the first fan-out trace 31 and the first sub-out trace 32 have the same or similar light-emitting brightness Therefore, the second sub-pixel 102 receiving the data signal transmitted by the first fan-out trace 31 and the second sub-pixel 102 receiving the data signal transmitted by the second fan-out trace 32 have the same or similar light emitting brightness, so as to ensure the uniformity of the display.
Alternatively, referring to fig. 6, the pixel 100 includes a plurality of sub-pixels 110 arranged 2 × 3, one row of sub-pixels 110 arranged in the first direction includes the first sub-pixel 101, the third sub-pixel 103 and the second sub-pixel 102, and another row of sub-pixels 110 arranged in the first direction includes the second sub-pixel 102, the third sub-pixel 103 and the first sub-pixel 101.
Fig. 7 is a schematic top view of another array substrate according to an embodiment of the invention, and referring to fig. 7, a first data line 221 is electrically connected to a first fan-out trace 31 or a second fan-out trace 32, and a second data line 222 is electrically connected to a third fan-out trace 33. The pixel 100 includes a plurality of sub-pixels 110 arranged 2 × 4, one row of sub-pixels 110 arranged in the first direction includes a first sub-pixel 101, a third sub-pixel 103, a second sub-pixel 102, and a third sub-pixel 103, and another row of sub-pixels 110 arranged in the first direction includes a second sub-pixel 102, a third sub-pixel 103, a first sub-pixel 101, and a third sub-pixel 103.
Illustratively, referring to fig. 6 and 7, the light emission color of the first sub-pixel 101 is red, the light emission color of the second sub-pixel 102 is blue, and the light emission color of the third sub-pixel 103 is green.
Alternatively, referring to fig. 2, 3, 6 and 7, the vertical projections of the first and third fan-out traces 31 and 33 on the substrate 10 do not overlap, and the vertical projections of the second and third fan-out traces 32 and 33 on the substrate 10 do not overlap. In the embodiment of the present invention, the vertical projections of the first fan-out trace 31 and the third fan-out trace 33 on the substrate 10 are not overlapped, so that the first fan-out trace 31 and the third fan-out trace 33 are prevented from generating overlapping capacitance. The second fan-out routing line 32 and the third fan-out routing line 33 are not overlapped in the vertical projection of the substrate 10, and the second fan-out routing line 32 and the third fan-out routing line 33 are prevented from generating overlapping capacitance.
Fig. 8 is a schematic top view structure diagram of fan-out traces in an array substrate according to an embodiment of the present invention, and referring to fig. 8, a vertical projection of a third fan-out trace 33 and a first fan-out trace 31 on a substrate 10 are overlapped. Since the second metal layer M2 is spaced between the third metal layer M3 and the first metal layer M1 in the direction perpendicular to the plane of the substrate 10, the second fan-out trace 32 is spaced between the third fan-out trace 33 and the first fan-out trace 31. In the direction perpendicular to the plane of the substrate 10, the distance between the third fan-out trace 33 and the first fan-out trace 31 is greater than the distance between the second fan-out trace 32 and the first fan-out trace 31, the distance between the third fan-out trace 33 and the first fan-out trace 31 is greater, and the overlap capacitance when the overlap is generated between the third fan-out trace 33 and the first fan-out trace 31 is smaller, so that the load increase caused by the third fan-out trace 33 and the first fan-out trace 31 is smaller. And because the third fan-out trace 33 overlaps the vertical projection of the first fan-out trace 31 on the substrate 10, the occupied area of the fan-out trace 30 in the stepped area a2 is reduced, the width of the stepped area a2 is reduced, the frame is reduced, and the screen occupation ratio is increased.
In addition, the first fan-out trace 31, the second fan-out trace 32 and the third fan-out trace 33 may be arranged in close proximity to each other, and do not overlap each other in the vertical projection of the substrate 10. I.e. the first, second and third fan-out traces 31, 32, 33 do not coincide with each other in the vertical projection of the substrate 10, while the vertical projections of the three fan-out traces are closely arranged without gaps between each other. Therefore, the space occupied by the gaps between the wires can be saved when the wires are arranged on the same layer, the width of the lower step is reduced, the orthographic projection of the wires on the bottom-sinking substrate is completely not overlapped, the overlapping capacitance generated between the wires can also be avoided, the space intervals between the wires arranged on different layers can be correspondingly increased, and the signal interference between the fan-out wires is further reduced.
Fig. 9 is a schematic top view of a fan-out trace in an array substrate according to another embodiment of the present invention, and referring to fig. 9, a vertical projection of a third fan-out trace 33 and a second fan-out trace 32 on a substrate 10 are overlapped. In the embodiment of the present invention, the third fan-out trace 33 overlaps with the first fan-out trace 31 and the second fan-out trace 32 in the vertical projection of the substrate 10. Thereby further reducing the area occupied by the fan-out traces 30 in the stepped region a2, reducing the width of the stepped region a2, reducing the bezel, and increasing the screen-to-screen ratio. In other embodiments, the third fan-out trace 33 may also not overlap the vertical projection of the first fan-out trace 31 on the substrate 10, but only the vertical projection of the second fan-out trace 32 on the substrate 10. Thus, in some possible embodiments, the third fan-out trace 33 may overlap the vertical projection of the first fan-out trace 31 and/or the second fan-out trace 32 on the substrate 10 to reduce the area occupied by the fan-out trace 30 in the step area a 2.
Alternatively, referring to fig. 9, an overlapping area of the third fan-out trace 33 and the second fan-out trace 32 is smaller than an overlapping area of the third fan-out trace 33 and the first fan-out trace 31. In the embodiment of the present invention, the vertical projection of the third fan-out trace 33 and the first fan-out trace 31 on the substrate 10 are overlapped, and the vertical projection of the third fan-out trace 33 and the second fan-out trace 32 on the substrate 10 are overlapped. In a direction perpendicular to the plane of the substrate 10, a distance between the third fan-out trace 33 and the first fan-out trace 31 is greater than a distance between the third fan-out trace 33 and the second fan-out trace 32, and an overlapping area between the third fan-out trace 33 and the second fan-out trace 32 is smaller than an overlapping area between the third fan-out trace 33 and the first fan-out trace 31. It will be appreciated that overlap capacitance is inversely proportional to distance and overlap capacitance is proportional to the overlap area. In the embodiment of the present invention, the overlapping area of the third fan-out trace 33 and the first fan-out trace 31 with a larger distance is larger, and the overlapping area of the third fan-out trace 33 and the second fan-out trace 32 with a smaller distance is smaller, so that the overlapping capacitance of the third fan-out trace 33 and the first fan-out trace 31 is consistent with the overlapping capacitance of the third fan-out trace 33 and the second fan-out trace 32, so as to balance the electrical influence of the third fan-out trace 33 on the first fan-out trace 31 and the second fan-out trace 32, so that the data signals transmitted on the first fan-out trace 31 and the second fan-out trace 32 have the same or similar attenuation, and thus the uniformity of the display is ensured.
Fig. 10 is a schematic cross-sectional view of another array substrate according to an embodiment of the invention, and referring to fig. 10, the data line 22 is located on the third metal layer M3. In the embodiment of the present invention, the third fan-out trace 33 and the data line 22 are both located on the third metal layer M3, and the third fan-out trace 33 and the data line 22 may be formed by using the same material and in the same process, so as to save the process.
Fig. 11 is a schematic cross-sectional structure view of another array substrate according to an embodiment of the present invention, fig. 12 is a schematic top-view structure view of another array substrate according to an embodiment of the present invention, fig. 13 is a schematic top-view structure view of another array substrate according to an embodiment of the present invention, referring to fig. 11, fig. 12, and fig. 13, and referring to fig. 1 in combination, the array substrate further includes a plurality of scan lines 21, and the plurality of scan lines 21 are located in the display area a1, extend along a first direction, and are arranged along a second direction. The scan line 21 is located in the first metal layer M1, the data line 22 is located in the second metal layer M2, and the second metal layer M2 and the third metal layer M3 are made of the same material. In the embodiment of the present invention, the second fan-out trace 32 and the third fan-out trace 33 are made of the same material, and the second fan-out trace 32 and the third fan-out trace 33 have the same resistivity, so that the difference between the voltage drops of the second fan-out trace 32 and the third fan-out trace 33 is reduced, and the data signals transmitted on the second fan-out trace 32 and the third fan-out trace 33 have the same or similar attenuation, so as to ensure the uniformity of the display.
Exemplarily, referring to fig. 11, fig. 12, and fig. 13 in combination with fig. 1, the scan line 21, the gate 52 of the thin film transistor 50, and the first plate 61 of the storage capacitor 60 are located on the first metal layer M1, and the source 51 of the thin film transistor 50, the drain 54 of the thin film transistor 50, the data line 22, and the second fan-out trace 32 are located on the second metal layer M2.
Alternatively, referring to fig. 11, 12 and 13 in combination with fig. 1, the display area a1 includes a plurality of pixels 100 arranged in an array, the pixel 100 includes a plurality of sub-pixels 110, and the plurality of sub-pixels 110 includes a first sub-pixel 101, a second sub-pixel 102 and a third sub-pixel 103. Along the second direction, the data line 22 electrically connected to the first sub-pixels 101 and the second sub-pixels 102 is a first data line 221, and the data line 22 electrically connected to the third sub-pixels 103 is a second data line 222. One first data line 221 is electrically connected to one second fan-out trace 32 or one third fan-out trace 33, and one second data line 222 is electrically connected to one first fan-out trace 31.
In the embodiment of the present invention, a part of the first sub-pixels 101 is electrically connected to the second fan-out trace 32, another part of the first sub-pixels 101 is electrically connected to the third fan-out trace 33, similarly, a part of the second sub-pixels 102 is electrically connected to the second fan-out trace 32, another part of the second sub-pixels 102 is electrically connected to the third fan-out trace 33, the second fan-out trace 32 located on the second metal layer M2 and the third fan-out trace 33 located on the third metal layer M3 are made of the same material, the second fan-out trace 32 and the third fan-out trace 33 have the same resistivity, so that the difference between the voltage drops of the second fan-out trace 32 and the third fan-out trace 33 is reduced, the attenuation of the data signals transmitted on the second fan-out trace 32 and the third fan-out trace 33 is the same or similar, and the first sub-pixels 101 receiving the data signals transmitted by the second fan-out trace 32 and the first sub-pixels 101 receiving the data signals transmitted by the third fan-out trace 33 have the same or similar light-emitting brightness Therefore, the second sub-pixel 102 receiving the data signal transmitted by the second fan-out trace 32 and the second sub-pixel 102 receiving the data signal transmitted by the third fan-out trace 33 have the same or similar light emitting brightness, so as to ensure the uniformity of the display.
Fig. 14 is a schematic structural diagram of a display panel according to an embodiment of the present invention, and referring to fig. 14, the display panel 400 includes the array substrate 200 in the above embodiment. The display panel 400 may be an organic light emitting display panel, a liquid crystal display panel, an electrophoretic display panel, or the like.
Exemplarily, referring to fig. 14, the display panel 400 further includes an opposite substrate 300 disposed opposite to the array substrate 200, and the opposite substrate 300 may be, for example, a color filter substrate or an encapsulation cover plate. The color filter substrate may include a color resistor, a black matrix, and other known structures, which are not described herein again.
Fig. 15 is a schematic structural diagram of a display device according to an embodiment of the present invention, and as shown in fig. 15, the display device according to an embodiment of the present invention includes the display panel 400. The display device may be a mobile phone shown in fig. 15, or may be a computer, a television, an intelligent wearable device, and the like, which is not particularly limited in this embodiment of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (19)
1. The array substrate is characterized by comprising a display area and a step area;
a substrate;
a plurality of data lines located in the display area; the data lines extend along a second direction and are arranged along a first direction;
the fan-out wires are positioned in the step areas and electrically connected with the data lines and used for providing data signals for the data lines; the plurality of fan-out wires comprise a first fan-out wire positioned on the first metal layer, a second fan-out wire positioned on the second metal layer and a third fan-out wire positioned on the third metal layer; in a direction perpendicular to the substrate, the second metal layer is located on one side, away from the substrate, of the first metal layer, the third metal layer is located on one side, away from the first metal layer, of the second metal layer, and vertical projections of the first fan-out routing and the second fan-out routing on the substrate are not overlapped;
the film layer where the data line is located is a first organic layer; the first fan-out routing and the second fan-out routing are positioned on two sides of the third fan-out routing;
the first fan-out routing line and the second fan-out routing line are closer in distance.
2. The array substrate of claim 1, further comprising a plurality of scan lines in the display area, extending along the first direction and arranged along the second direction;
the scanning line is located on the first metal layer, and the second metal layer is located between the first metal layer and the film layer where the data line is located.
3. The array substrate of claim 2, wherein the first metal layer and the second metal layer are made of the same material.
4. The array substrate of claim 3, wherein a line width of the first fan-out trace is equal to a line width of the second fan-out trace.
5. The array substrate of claim 3, wherein the display area comprises a plurality of pixels arranged in an array, the pixels comprising a plurality of sub-pixels, the plurality of sub-pixels comprising a first sub-pixel, a second sub-pixel and a third sub-pixel;
along the second direction, the data line electrically connected with the first sub-pixels and the second sub-pixels is a first data line, and the data line electrically connected with the third sub-pixels is a second data line;
one first data line is electrically connected with one first fan-out wiring or one second fan-out wiring, and one second data line is electrically connected with one third fan-out wiring.
6. The array substrate of claim 5, wherein the pixel comprises a plurality of the sub-pixels arranged in 2 x 3, one row of the sub-pixels arranged in the first direction comprises the first sub-pixel, the third sub-pixel and the second sub-pixel, and another row of the sub-pixels arranged in the first direction comprises the second sub-pixel, the third sub-pixel and the first sub-pixel.
7. The array substrate of claim 5, wherein the pixel comprises a plurality of the sub-pixels arranged in 2 x 4 rows, one row of the sub-pixels arranged in the first direction comprises the first sub-pixel, the third sub-pixel, the second sub-pixel and the third sub-pixel, and another row of the sub-pixels arranged in the first direction comprises the second sub-pixel, the third sub-pixel, the first sub-pixel and the third sub-pixel.
8. The array substrate of claim 1, wherein the data line is located in the third metal layer.
9. The array substrate of claim 1, wherein the third metal layer is located on a side of the film layer where the data line is located away from the substrate.
10. The array substrate of claim 9, further comprising a first insulating layer and a second insulating layer, wherein the first insulating layer is located between the first metal layer and the second metal layer, the second insulating layer is located between the third metal layer and the film layer where the data line is located, and a thickness of the second insulating layer is greater than a thickness of the first insulating layer.
11. The array substrate of claim 10, wherein the second insulating layer comprises a planarization layer and a pixel defining layer, the planarization layer being located between the pixel defining layer and the third metal layer.
12. The array substrate of claim 1, wherein the third fan-out trace overlaps a perpendicular projection of the first fan-out trace on the substrate.
13. The array substrate of claim 12, wherein the third fan-out trace overlaps a perpendicular projection of the second fan-out trace on the substrate.
14. The array substrate of claim 13, wherein an overlapping area of the third fan-out trace and the second fan-out trace is smaller than an overlapping area of the third fan-out trace and the first fan-out trace.
15. The array substrate of claim 1, wherein the first fan-out trace and the third fan-out trace do not overlap in vertical projection on the substrate, and the second fan-out trace and the third fan-out trace do not overlap in vertical projection on the substrate.
16. The array substrate of claim 1, further comprising a plurality of scan lines in the display area, extending along the first direction and arranged along the second direction;
the scanning lines are located on the first metal layer, the data lines are located on the second metal layer, and the second metal layer and the third metal layer are made of the same material.
17. The array substrate of claim 16, wherein the display area comprises a plurality of pixels arranged in an array, the pixels comprising a plurality of sub-pixels, the plurality of sub-pixels comprising a first sub-pixel, a second sub-pixel and a third sub-pixel;
along the second direction, the data line electrically connected with the plurality of first sub-pixels and the plurality of second sub-pixels is a first data line, and the data line electrically connected with the plurality of third sub-pixels is a second data line;
one first data line is electrically connected with one second fan-out wiring or one third fan-out wiring, and one second data line is electrically connected with one first fan-out wiring.
18. A display panel comprising the array substrate according to any one of claims 1 to 17.
19. A display device characterized by comprising the display panel according to claim 18.
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| CN111653603B (en) * | 2020-06-18 | 2023-08-29 | 京东方科技集团股份有限公司 | Display substrate and display device |
| CN111933674B (en) * | 2020-08-18 | 2024-06-11 | 京东方科技集团股份有限公司 | Display substrate and display device |
| CN113675253B (en) * | 2021-08-24 | 2024-05-24 | 京东方科技集团股份有限公司 | Display panel, manufacturing method thereof and display device |
| CN113870713B (en) * | 2021-09-29 | 2023-11-07 | 成都京东方光电科技有限公司 | Display panel and display device |
| CN115206222A (en) * | 2022-05-30 | 2022-10-18 | 武汉华星光电半导体显示技术有限公司 | Display panel and display terminal |
| CN115148774A (en) * | 2022-06-30 | 2022-10-04 | 厦门天马显示科技有限公司 | Display panel and display device |
| CN118714882A (en) * | 2022-06-30 | 2024-09-27 | 厦门天马显示科技有限公司 | Display panel and display device |
| WO2024087192A1 (en) * | 2022-10-28 | 2024-05-02 | 京东方科技集团股份有限公司 | Display module and preparation method therefor, and display apparatus |
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