CN109031828B - Array substrate, driving method thereof, display panel and display device - Google Patents
Array substrate, driving method thereof, display panel and display device Download PDFInfo
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- CN109031828B CN109031828B CN201810967378.7A CN201810967378A CN109031828B CN 109031828 B CN109031828 B CN 109031828B CN 201810967378 A CN201810967378 A CN 201810967378A CN 109031828 B CN109031828 B CN 109031828B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13458—Terminal pads
Abstract
The invention discloses an array substrate, a driving method thereof, a display panel and a display device, belonging to the technical field of display and comprising the following steps: a display area and a non-display area; the display area comprises a plurality of gate lines and a plurality of data lines; the non-display area comprises a binding area and a multi-path distribution circuit; wherein the binding region is located at a first side of the display region; the multi-path distribution circuit is positioned at the second side of the display area; the multi-path distribution circuit comprises a plurality of sub-circuits, wherein each sub-circuit comprises a signal input end, a first signal output end and a second signal output end; the first signal output end is electrically connected with the second data line, the second signal output end is electrically connected with the third data line, the signal input end is electrically connected with the first end of the first data line, and the conductive bonding pad is electrically connected with the second end of the first data line. Compared with the prior art, the array substrate is beneficial to narrowing the frame and improving the display quality.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a driving method of the array substrate, a display panel and a display device.
Background
With the development of display technology, the resolution of the display device is higher and higher, and more data lines are provided, so that too many lines are provided at the step of the display panel, and the narrow frame at the step is affected. Therefore, in the prior art, a scheme using a DEMUX circuit is proposed, which uses one data channel to time-division multiplex an input data signal.
Referring to fig. 1, fig. 1 is a schematic plan view of a display panel provided in the prior art, which includes a display area 01 and a non-display area 02, where the non-display area includes a DEMUX circuit 03 and a chip 04, where the DEMUX circuit 03 and the chip 04 are both located on a lower frame of the display panel. The display area 01 includes a plurality of data lines 05.
In the display panel shown in fig. 1, the problem in the prior art is described only with the demultiplexer of which the DEMUX circuit 03 has a selection path number of 3. The DEMUX circuit 03 comprises a plurality of sub-circuits 031, which sub-circuits 031 comprise: an input terminal I, three switches 032, and three output terminals O, wherein the input terminal I is electrically connected to the chip 04, and the chip 04 provides the data signal to the data line 05 in a time-sharing manner through the sub-circuit 031. The output terminal O is electrically connected to the data line 05, and the signal at the input terminal I is transmitted to the data line 05 through the sub-circuit 031 in a time-sharing manner.
The first pole of switch 032 is electrically connected to input I, the second pole of switch 032 is electrically connected to output O, and the second poles of three switches 032 are connected to different outputs O respectively. The gates of the three switches 032 are connected to three control lines 033 respectively, and the control lines 033 control the three switches 032 to be turned on in a time-sharing manner, so that the electrical signals at the input end I are transmitted to different data lines 05 in a time-sharing manner.
Because the DEMUX circuit 03 and the chip 04 are both located on the lower frame of the display panel, the lower frame of the display panel is wider, which is not favorable for narrowing the frame of the display panel. In addition, the DEMUX circuit 03 has a complicated circuit structure, thus occupying more space and being more disadvantageous to the narrowing of the frame of the display panel.
Disclosure of Invention
In view of the above, the present invention provides an array substrate, a driving method thereof, a display panel and a display device to improve the above problems.
The invention provides an array substrate, comprising: a display area and a non-display area; the display area comprises a plurality of gate lines and a plurality of data lines, and the gate lines and the data lines are insulated in a crossing manner; the non-display area comprises a binding area and a multi-path distribution circuit; the display device comprises a display area, a binding area and a control area, wherein the binding area is positioned on a first side of the display area and comprises a plurality of conductive bonding pads; the multi-path distribution circuit is positioned on the second side of the display area, and the first side and the second side are positioned on two opposite sides of the display area; the multi-path distribution circuit comprises a plurality of sub-circuits, wherein each sub-circuit comprises a signal input end, a first signal output end and a second signal output end; the data lines are divided into a plurality of data line groups, and the data line groups and the sub-circuits are arranged in a one-to-one correspondence manner; the data line group comprises a first data line, a second data line and a third data line; the first signal output end is electrically connected with the second data line, the second signal output end is electrically connected with the third data line, the signal input end is electrically connected with the first end of the first data line, and the conductive bonding pad is electrically connected with the second end of the first data line.
The invention provides a display panel, which comprises the array substrate provided by the invention.
The invention also provides a display device comprising the display panel provided by the invention.
The invention provides a driving method of an array substrate, wherein the array substrate comprises the following steps: a display area and a non-display area; the display area comprises a plurality of gate lines and a plurality of data lines, and the gate lines and the data lines are insulated in a crossing manner; the non-display area comprises a binding area and a multi-path distribution circuit; the display device comprises a display area, a binding area and a control area, wherein the binding area is positioned on a first side of the display area and comprises a plurality of conductive bonding pads; the multi-path distribution circuit is positioned on the second side of the display area, and the first side and the second side are positioned on two opposite sides of the display area; the multi-path distribution circuit comprises a plurality of sub-circuits, wherein each sub-circuit comprises a signal input end, a first signal output end and a second signal output end; the data lines are divided into a plurality of data line groups, and the data line groups and the sub-circuits are arranged in a one-to-one correspondence manner; the data line group comprises a first data line, a second data line and a third data line; the first signal output end is electrically connected with the second data wire, the second signal output end is electrically connected with the third data wire, the signal input end is electrically connected with the first end of the first data wire, and the conductive bonding pad is electrically connected with the second end of the first data wire;
the driving method comprises the following steps:
at the first moment, the conductive pad is controlled to be electrically connected with the first data line and the second data line, and the conductive pad is controlled to be insulated from the third data line; at the second moment, the control conductive bonding pad is electrically connected with the first data line and the third data line, and the control conductive bonding pad is insulated from the second data line; and at the third moment, the control conductive bonding pad is insulated from the second data line and the third data line, and the control conductive bonding pad is electrically connected with the first data line.
Compared with the prior art, the array substrate, the driving method thereof, the display panel and the display device provided by the invention at least realize the following beneficial effects:
the multi-path distribution circuit is arranged at the upper frame with a simpler structure, so that the area of the lower frame is favorably reduced, and the narrow frame of the array substrate is favorably realized. Compared with the prior art, the circuit structure of the multi-path distribution circuit is simpler on the premise of ensuring the normal work of the multi-path distribution circuit, so that the occupied area of the multi-path distribution circuit is further reduced, and the narrowing of the upper frame is further facilitated.
Of course, it is not necessary for any product in which the present invention is practiced to achieve all of the above-described technical effects simultaneously.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
Fig. 1 is a schematic plan view of a display panel provided in the prior art;
fig. 2 is a schematic plan view illustrating an array substrate according to an embodiment of the present invention;
fig. 3 is a schematic plan view of another array substrate according to an embodiment of the present invention;
fig. 4 is a schematic plan view illustrating another array substrate according to an embodiment of the present invention;
fig. 5 is a schematic cross-sectional view illustrating a display panel according to an embodiment of the invention;
fig. 6 is a schematic plan view illustrating a display panel according to an embodiment of the present invention;
fig. 7 is a schematic plan view of a display device according to an embodiment of the present invention;
fig. 8 is a flowchart of an array substrate driving method according to an embodiment of the present invention;
fig. 9 is a timing diagram of an array substrate according to an embodiment of the invention;
fig. 10 is a flowchart of another driving method of an array substrate according to an embodiment of the invention.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
Referring to fig. 2, fig. 2 is a schematic plan view illustrating an array substrate according to an embodiment of the present invention, where the embodiment provides an array substrate, including:
a display area AA and a non-display area NA;
the display area AA includes a plurality of gate lines 11 and a plurality of data lines 12, the gate lines 11 and the data lines 12 being cross-insulated;
the non-display area NA includes a binding area 20 and a demultiplexing circuit 30; wherein the content of the first and second substances,
the bonding area 20 is located at the first side S of the display area AA, and the bonding area 20 includes a plurality of conductive pads 21;
the multi-path distribution circuit 30 is located at the second side N of the display area AA, and the first side S and the second side N are located at two opposite sides of the display area AA;
the multi-path distribution circuit 30 comprises a plurality of sub-circuits 31, and each sub-circuit 31 comprises a signal input end 3A, a first signal output end 3B and a second signal output end 3C;
the plurality of data lines 12 are divided into a plurality of data line groups 120, and the data line groups 120 and the sub-circuits 31 are arranged in a one-to-one correspondence; the data line group 120 includes a first data line 121, a second data line 122, and a third data line 123;
the first signal output terminal 3B is electrically connected to the second data line 122, the second signal output terminal 3C is electrically connected to the third data line 123, the signal input terminal 3A is electrically connected to the first end 121a of the first data line 121, and the conductive pad 21 is electrically connected to the second end 121B of the first data line 121.
In this embodiment, the display area AA is used for displaying image information and may include a plurality of pixels (not shown).
The gate lines 11 are arranged in parallel, the data lines 12 are arranged in parallel, the gate lines 11 and the data lines 12 are insulated in a crossing manner, and alternatively, the gate lines 11 and the data lines 12 may be arranged vertically.
The non-display area NA includes a binding area 20, and the binding area 20 is located at a first side S of the display area AA. When the array substrate provided by this embodiment is applied to a display panel, the bonding region 20 is used for bonding a chip or a flexible circuit board (not shown), and the chip or the flexible circuit board can be electrically connected through a conductive adhesive and a conductive pad 21.
The multiplexing circuit 30 is located on the second side N of the display area AA, the bonding area 20 and the multiplexing circuit 30 are located on two opposite sides of the display area AA, and optionally, the first side S and the second side N are located on two sides of the data line 12 in the extending direction. The non-display area NA on the first side S of the display area AA is generally referred to as a lower frame, and the non-display area NA on the second side N of the display area AA is generally referred to as an upper frame. In general, the circuit structure at the lower frame is complex, and includes a plurality of circuit structures such as the bonding region 20 and a visual detection circuit (not shown). In addition, the lower frame has more circuits, so the arrangement of circuit wires is more complicated, and the circuit wires may overlap to generate parasitic capacitance, which affects the accuracy of signals of the circuits. The circuit structure shown in the upper frame is relatively simple and usually includes an electrostatic protection circuit (not shown). In this embodiment, the multi-path distribution circuit 30 is disposed at the upper frame with a simple structure, which is beneficial to reducing the area of the lower frame, thereby being beneficial to narrowing the frame of the display panel. Moreover, the circuit structure at the upper frame is simple, and the upper frame can provide more space for arranging the multi-path distribution circuit, so that the routing arrangement of the multi-path distribution circuit 30 is simple.
In addition, in the present embodiment, the demultiplexing circuit 30 includes a plurality of sub-circuits 31, each sub-circuit 31 includes a signal input terminal and two signal output terminals, and the electrical signal at the signal input terminal 3A can be transmitted to the first signal output terminal 3B and the second signal output terminal 3C in a time-sharing manner. One conductive pad time-divisionally supplies a data signal to the data line group 120 corresponding thereto, and one data line group 120 includes three data lines 12. Specifically, the first data line 121 is used to electrically connect the signal input terminal 3A and the conductive pad 21, the first signal output terminal 3B is electrically connected to the second data line 122, the second signal output terminal 3C is electrically connected to the third data line 123, and the first data line 121 may transmit the electrical signal of the conductive pad 21 to the second data line 122 and the third data line 123 in a time-sharing manner. When both the first signal output terminal 3B and the second signal output terminal 3C of the sub circuit 31 are not output, the electric signal of the conductive pad 21 is transmitted to the first data line 121, but not to the second data line 122 and the third data line 123.
In the multi-path distribution circuit 30 provided in this embodiment, the sub-circuit 31 only includes two signal output terminals (the first signal output terminal 3B and the second signal output terminal 3C), and the circuit structure is simple. Compared with the prior art, although the number of signal output ends is reduced, one conductive pad 21 can still provide electric signals for three data lines 12 in a time-sharing mode, and normal operation of the multi-way distribution circuit is guaranteed.
In the array substrate provided by this embodiment, the multi-path distribution circuit 30 is disposed at the upper frame with a simple structure, which is beneficial to reducing the area of the lower frame, thereby being beneficial to narrowing the frame of the array substrate. Moreover, compared with the prior art, on the premise of ensuring the normal work of the multi-path distribution circuit, the circuit structure of the multi-path distribution circuit 30 is simpler, so that the occupied area of the multi-path distribution circuit 30 is further reduced, and the narrowing of the upper frame is further facilitated.
In some optional embodiments, please refer to fig. 3, fig. 3 is a schematic plane structure diagram of another array substrate according to an embodiment of the present invention, in which the sub-circuit 31 includes a first control line 321, a second control line 322, a first switch 331, and a second switch 332;
the gate of the first switch 331 is electrically connected to the first control line 321, the first pole of the first switch 331 is electrically connected to the signal input terminal 3A, and the second pole of the first switch 331 is electrically connected to the first signal output terminal 3B;
the gate of the second switch 332 is electrically connected to the second control line 322, the first pole of the second switch 332 is electrically connected to the signal input terminal 3A, and the second pole of the second switch 332 is electrically connected to the second signal output terminal 3C.
In this embodiment, the gate of the first switch 331 is electrically connected to the first control line 321, and the first control line 321 controls the on or off state of the first switch 331. The gate of the second switch 332 is electrically connected to the second control line 322, and the second control line 322 controls the on or off state of the second switch 332. Optionally, the first switch 331 and the second switch 332 are thin film transistors. In fig. 3, only the first switch 331 and the second switch 332 are N-type thin film transistors for illustration. When the first control line 321 and the second control line 322 are at a high level, the first switch 331 and the second switch 332 are turned on. When the first control line 321 and the second control line 322 are at a low level, the first switch 331 and the second switch 332 are turned off. It can be understood that, in other alternative implementations of the present invention, the first switch 331 and the second switch 332 may be P-type thin film transistors, and details of this embodiment are not repeated herein.
In this embodiment, when it is required to output the data signal from only the first signal output terminal 3B, the first control line 321 controls the first switch 331 to be turned on, and the second control line 322 controls the second switch 332 to be turned off; when it is required to output only the data signal from the second signal output terminal 3C, the first control line 321 controls the first switch 331 to be turned off, and the second control line 322 controls the second switch 332 to be turned on; when it is required that neither the first signal output terminal 3B nor the second signal output terminal 3C outputs the data signal, the first control line 321 controls the first switch 331 to be turned off, and the second control line 322 controls the second switch 332 to be turned off.
Optionally, referring to fig. 4, fig. 4 is a schematic plan view of another array substrate according to an embodiment of the present invention, in which gates of the first switches 331 in the plurality of sub-circuits 31 are electrically connected to the same first control line 321, and gates of the second switches 332 in the plurality of sub-circuits 31 are electrically connected to the same second control line 322. In this embodiment, the plurality of sub-circuits share the first control line 321 and the second control line 322, which can reduce the number of circuit elements in the multi-path distribution circuit 30, thereby further reducing the area occupied by the multi-path distribution circuit on the upper frame, and being beneficial to narrowing the upper frame.
Referring to fig. 5, fig. 5 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the present invention, and the embodiment provides a display panel including the array substrate 100 according to any one of the embodiments of the present invention. Optionally, the display panel provided in the embodiment of the present invention is a liquid crystal display panel, and further includes a color film substrate 200 and a liquid crystal layer 300.
Fig. 5 illustrates a display panel by taking only a liquid crystal display panel as an example. In other alternative embodiments of the present invention, the display panel may also be an electronic paper display panel, an organic light emitting display panel, a micro diode display panel, or other types of display panels, which is not limited in this embodiment.
The display panel provided in the embodiment of the present invention has the beneficial effects of the array substrate provided in the embodiment of the present invention, and specific descriptions of the array substrate in the above embodiments may be specifically referred to, and no further description is given in this embodiment.
Optionally, referring to fig. 6, fig. 6 is a schematic plan view illustrating a display panel according to an embodiment of the present invention, in which the display area AA includes a plurality of sub-pixels P, and the sub-pixels P include a first color sub-pixel P1, a second color sub-pixel P2, and a third color sub-pixel P3; the first data line 121 is electrically connected to the first color sub-pixel P1, the second data line 122 is electrically connected to the second color sub-pixel P2, and the third data line 123 is electrically connected to the third color sub-pixel P3.
Optionally, the sub-pixel P includes a thin film transistor PA and a pixel electrode PB, and when the thin film transistor PA is turned on, a data signal of the data line is transmitted to the pixel electrode PB. In this embodiment, the first data line 121 is used for transmitting data signals to the first color sub-pixel P1, the second data line 122 is used for transmitting data signals to the second color sub-pixel P2, and the third data line 123 is used for transmitting data signals to the third color sub-pixel P3.
Optionally, with continued reference to fig. 6, the sub-pixels P in the same column have the same color. The extending direction of the data line 12 is a column direction. Alternatively, the sub-pixels P electrically connected to the same data line 12 have the same color.
An embodiment of the present invention provides a display device, including the display panel provided in any one of the above embodiments of the present invention. Referring to fig. 7, fig. 7 is a schematic structural diagram of a display device according to an embodiment of the present invention. Fig. 7 provides a display device 1000 including the display panel 100A according to any of the above embodiments of the present invention. The embodiment of fig. 7 only takes a mobile phone as an example to describe the display device 1000, and it should be understood that the display device provided in the embodiment of the present invention may be other display devices with a display function, such as a computer, a television, a vehicle-mounted display device, and the present invention is not limited thereto. The display device provided in the embodiment of the present invention has the beneficial effects of the display panel provided in the embodiment of the present invention, and specific reference may be made to the specific description of the display panel in each of the above embodiments, which is not repeated herein.
Referring to fig. 2 and 8 in combination, fig. 8 is a flowchart illustrating a driving method of an array substrate according to an embodiment of the present invention, which provides a driving method of an array substrate,
the array substrate includes:
a display area AA and a non-display area NA;
the display area AA includes a plurality of gate lines 11 and a plurality of data lines 12, the gate lines 11 and the data lines 12 being cross-insulated;
the non-display area NA includes a binding area 20 and a demultiplexing circuit 30; wherein the content of the first and second substances,
the bonding area 20 is located at the first side S of the display area AA, and the bonding area 20 includes a plurality of conductive pads 21;
the multi-path distribution circuit 30 is located at the second side N of the display area AA, and the first side S and the second side N are located at two opposite sides of the display area AA;
the multi-path distribution circuit 30 comprises a plurality of sub-circuits 31, and each sub-circuit 31 comprises a signal input end 3A, a first signal output end 3B and a second signal output end 3C;
the plurality of data lines 12 are divided into a plurality of data line groups 120, and the data line groups 120 and the sub-circuits 31 are arranged in a one-to-one correspondence; the data line group 120 includes a first data line 121, a second data line 122, and a third data line 123;
the first signal output terminal 3B is electrically connected to the second data line 122, the second signal output terminal 3C is electrically connected to the third data line 123, the signal input terminal 3A is electrically connected to the first end 121a of the first data line 121, and the conductive pad 21 is electrically connected to the second end 121B of the first data line 121;
the driving method comprises the following steps:
step S1: at a first moment, the control conductive pad 21 is electrically connected with the first data line 121 and the second data line 122, and the control conductive pad 21 is insulated from the third data line 123;
step S2: at the second moment, the control conductive pad 21 is electrically connected with the first data line 121 and the third data line 123, and the control conductive pad 21 is insulated from the second data line 122;
step S3: at the third time, the control conductive pad 21 is insulated from the second data line 122 and the third data line 123, and the control conductive pad 21 is electrically connected to the first data line 121.
In this embodiment, the multi-path distribution circuit 30 includes a plurality of sub-circuits 31, each sub-circuit 31 includes a signal input terminal and two signal output terminals, and the electrical signal of the signal input terminal 3A can be transmitted to the first signal output terminal 3B and the second signal output terminal 3C in a time-sharing manner. One sub-circuit time-divisionally supplies data signals to the data line group 120 corresponding thereto, and one data line group 120 includes three data lines 12. Specifically, the first data line 121 is used to electrically connect the signal input terminal 3A and the conductive pad 21, the first signal output terminal 3B is electrically connected to the second data line 122, the second signal output terminal 3C is electrically connected to the third data line 123, and the first data line 121 may transmit the electrical signal of the conductive pad 21 to the second data line 122 and the third data line 123 in a time-sharing manner. When the second data line 122 and the third data line 123 receive the data signal, the data signal of the conductive pad 21 is transmitted to the first data line 121. One conductive pad 21 may transmit a data signal to the first data line 121, the second data line 122, and the third data line 123 in time division.
In the driving method provided in this embodiment, the sub-circuit 31 only includes two signal output terminals (the first signal output terminal 3B and the second signal output terminal 3C), and the circuit structure is simple. Compared with the prior art, although the number of signal output ends is reduced, one conductive pad 21 can still provide electric signals for three data lines 12 in a time-sharing mode, and normal operation of the multi-way distribution circuit is guaranteed.
In some optional embodiments, please refer to fig. 3, 9 and 10, fig. 9 is a timing diagram of an array substrate according to an embodiment of the present invention, fig. 10 is a flowchart of another driving method of an array substrate according to an embodiment of the present invention, the sub-circuit 31 includes a first control line 321, a second control line 322, a first switch 331 and a second switch 332; the gate of the first switch 331 is electrically connected to the first control line 321, the first pole of the first switch 331 is electrically connected to the signal input terminal 3A, and the second pole of the first switch 331 is electrically connected to the first signal output terminal 3B;
the gate of the second switch 332 is electrically connected to the second control line 322, the first pole of the second switch 332 is electrically connected to the signal input terminal 3A, and the second pole of the second switch 332 is electrically connected to the second signal output terminal 3C.
Step S11: at a first time T1, the first control line 321 receives an enable signal to control the first switch 331 to be turned on, the second control line 322 receives a disable signal to control the second switch 332 to be turned off, and the conductive pad 21 transmits a second data signal DA 2;
step S21: at a second time T2, the first control line 321 receives a disable signal to control the first switch 331 to be turned off, the second control line 322 receives an enable signal to control the second switch 332 to be turned on, and the conductive pad 21 transmits a third data signal DA 3;
step S31: at a third time T3, the first control line 321 receives the disable signal to control the first switch 331 to be turned off, the second control line 322 receives the disable signal to control the second switch 332 to be turned off, and the conductive pad 21 transmits the first data signal DA 1.
In this embodiment, only the first switch 331 and the second switch 332 are N-type thin film transistors, and the enable signals of the first control line 321 and the second control line 322 are high level signals.
It should be noted that at the first time T1, the second data signal DA2 of the conductive pad 21 is transmitted to the first data line 121 and the second data line 122; at a second time T2, the third data signal DA3 of the conductive pad 21 is transmitted to the first data line 121 and the first data line 123; at a third time T3, the first data signal DA1 of the conductive pad is transmitted to the first data line 121 to refresh the electrical signal of the first data line 121. Since the charging time of each data line is short, the time of the first time T1 and the time of the second time T2 are short, and the display effect of the display panel is little affected.
According to the embodiment, the array substrate, the driving method thereof, the display panel and the display device provided by the invention at least realize the following beneficial effects:
the multi-path distribution circuit is arranged at the upper frame with a simpler structure, so that the area of the lower frame is favorably reduced, and the narrow frame of the array substrate is favorably realized. Compared with the prior art, the circuit structure of the multi-path distribution circuit is simpler on the premise of ensuring the normal work of the multi-path distribution circuit, so that the occupied area of the multi-path distribution circuit is further reduced, and the narrowing of the upper frame is further facilitated.
Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (10)
1. An array substrate, comprising:
a display area and a non-display area;
the display area comprises a plurality of gate lines and a plurality of data lines, and the gate lines and the data lines are insulated in a crossed mode;
the non-display area comprises a binding area and a multi-path distribution circuit; wherein the content of the first and second substances,
the binding region is positioned in the non-display region on a first side of the display region, and the binding region comprises a plurality of conductive bonding pads;
the multi-path distribution circuit is positioned in the non-display area on the second side of the display area, and the first side and the second side are positioned on two opposite sides of the display area;
the multi-path distribution circuit comprises a plurality of sub-circuits, and each sub-circuit comprises a signal input end, a first signal output end and a second signal output end;
the data lines are divided into a plurality of data line groups, and the data line groups and the sub-circuits are arranged in a one-to-one correspondence manner; the data line group comprises a first data line, a second data line and a third data line;
the first signal output end is electrically connected with the second data line, the second signal output end is electrically connected with the third data line, the signal input end is electrically connected with the first end of the first data line, and the conductive bonding pad is electrically connected with the second end of the first data line.
2. The array substrate of claim 1,
the sub-circuit comprises a first control line, a second control line, a first switch and a second switch;
a gate of the first switch is electrically connected to the first control line, a first pole of the first switch is electrically connected to the signal input terminal, and a second pole of the first switch is electrically connected to the first signal output terminal;
the grid electrode of the second switch is electrically connected with the second control line, the first pole of the second switch is electrically connected with the signal input end, and the second pole of the second switch is electrically connected with the second signal output end.
3. The array substrate of claim 2,
the first switch and the second switch are thin film transistors.
4. The array substrate of claim 2,
the gate of the first switch in the plurality of sub-circuits is electrically connected to the same first control line, and the gate of the second switch in the plurality of sub-circuits is electrically connected to the same second control line.
5. A display panel comprising the array substrate according to any one of claims 1 to 4.
6. The display panel according to claim 5,
the display area comprises a plurality of sub-pixels, and the sub-pixels comprise a first color sub-pixel, a second color sub-pixel and a third color sub-pixel;
the first data line is electrically connected with the first color sub-pixel, the second data line is electrically connected with the second color sub-pixel, and the third data line is electrically connected with the third color sub-pixel.
7. The display panel according to claim 6,
the sub-pixels in the same column have the same color.
8. A display device characterized by comprising the display panel according to any one of claims 5 to 7.
9. A driving method of an array substrate is characterized in that,
the array substrate includes:
a display area and a non-display area;
the display area comprises a plurality of gate lines and a plurality of data lines, and the gate lines and the data lines are insulated in a crossed mode;
the non-display area comprises a binding area and a multi-path distribution circuit; wherein the content of the first and second substances,
the binding region is positioned in the non-display region on a first side of the display region, and the binding region comprises a plurality of conductive bonding pads;
the multi-path distribution circuit is positioned in the non-display area on the second side of the display area, and the first side and the second side are positioned on two opposite sides of the display area;
the multi-path distribution circuit comprises a plurality of sub-circuits, and each sub-circuit comprises a signal input end, a first signal output end and a second signal output end;
the data lines are divided into a plurality of data line groups, and the data line groups and the sub-circuits are arranged in a one-to-one correspondence manner; the data line group comprises a first data line, a second data line and a third data line;
the first signal output end is electrically connected with the second data line, the second signal output end is electrically connected with the third data line, the signal input end is electrically connected with the first end of the first data line, and the conductive bonding pad is electrically connected with the second end of the first data line;
the driving method includes:
at a first moment, controlling the conductive pad to be electrically connected with the first data line and the second data line, and controlling the conductive pad to be insulated from the third data line;
at a second moment, the conductive pad is controlled to be electrically connected with the first data line and the third data line, and the conductive pad is controlled to be insulated from the second data line;
and at a third moment, the conductive pad is controlled to be insulated from the second data line and the third data line, and the conductive pad is controlled to be electrically connected with the first data line.
10. The driving method of the array substrate according to claim 9,
the sub-circuit comprises a first control line, a second control line, a first switch and a second switch;
a gate of the first switch is electrically connected to the first control line, a first pole of the first switch is electrically connected to the signal input terminal, and a second pole of the first switch is electrically connected to the first signal output terminal;
a gate of the second switch is electrically connected to the second control line, a first pole of the second switch is electrically connected to the signal input terminal, and a second pole of the second switch is electrically connected to the second signal output terminal;
at the first moment, the first control line receives an enable signal to control the first switch to be turned on, the second control line receives a non-enable signal to control the second switch to be turned off, and the conductive pad transmits a second data signal;
at the second moment, the first control line receives a non-enable signal to control the first switch to be turned off, the second control line receives an enable signal to control the second switch to be turned on, and the conductive pad transmits a third data signal;
at the third moment, the first control line receives a non-enable signal to control the first switch to be turned off, the second control line receives a non-enable signal to control the second switch to be turned off, and the conductive pad transmits a first data signal.
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| TWI685828B (en) * | 2019-01-03 | 2020-02-21 | 友達光電股份有限公司 | Display apparatus |
| CN109887458B (en) * | 2019-03-26 | 2022-04-12 | 厦门天马微电子有限公司 | Display panel and display device |
| CN110853562A (en) * | 2019-11-14 | 2020-02-28 | 武汉华星光电技术有限公司 | Display panel and display device |
| CN110956927B (en) * | 2019-12-18 | 2021-03-02 | 京东方科技集团股份有限公司 | Display device, stretchable display panel and driving method thereof |
| CN111708238B (en) * | 2020-06-30 | 2023-06-13 | 上海中航光电子有限公司 | Array substrate and display panel |
| CN113009741B (en) * | 2021-03-09 | 2022-07-08 | 北海惠科光电技术有限公司 | Array substrate, display panel and manufacturing method thereof |
| CN114999412A (en) * | 2021-09-23 | 2022-09-02 | 荣耀终端有限公司 | Array substrate, display panel, display module and electronic equipment |
| CN114115606B (en) * | 2021-11-30 | 2023-07-25 | 武汉华星光电半导体显示技术有限公司 | Touch display panel and display device |
| CN115311975A (en) * | 2022-08-09 | 2022-11-08 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101551966A (en) * | 2008-04-03 | 2009-10-07 | 乐金显示有限公司 | Flat panel display |
| CN106066739A (en) * | 2016-07-29 | 2016-11-02 | 厦门天马微电子有限公司 | Array base palte, the display floater comprising it and display device |
| CN206134140U (en) * | 2016-11-01 | 2017-04-26 | 厦门天马微电子有限公司 | Display panel and display device |
| CN108376536A (en) * | 2018-04-24 | 2018-08-07 | 武汉华星光电技术有限公司 | De-mux drives framework, round display panel and smartwatch |
| CN108399900A (en) * | 2018-02-12 | 2018-08-14 | 厦门天马微电子有限公司 | Display device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102137079B1 (en) * | 2014-03-03 | 2020-07-24 | 삼성디스플레이 주식회사 | Organic light emitting display device |
| JP2016109782A (en) * | 2014-12-03 | 2016-06-20 | 三星ディスプレイ株式會社Ｓａｍｓｕｎｇ Ｄｉｓｐｌａｙ Ｃｏ．，Ｌｔｄ． | Display device and drive method |
-
2018
- 2018-08-23 CN CN201810967378.7A patent/CN109031828B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101551966A (en) * | 2008-04-03 | 2009-10-07 | 乐金显示有限公司 | Flat panel display |
| CN106066739A (en) * | 2016-07-29 | 2016-11-02 | 厦门天马微电子有限公司 | Array base palte, the display floater comprising it and display device |
| CN206134140U (en) * | 2016-11-01 | 2017-04-26 | 厦门天马微电子有限公司 | Display panel and display device |
| CN108399900A (en) * | 2018-02-12 | 2018-08-14 | 厦门天马微电子有限公司 | Display device |
| CN108376536A (en) * | 2018-04-24 | 2018-08-07 | 武汉华星光电技术有限公司 | De-mux drives framework, round display panel and smartwatch |
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| Publication number | Publication date |
|---|---|
| CN109031828A (en) | 2018-12-18 |
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